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order number: 300641-004us notice: the intel ? 6300ESB i/o controller hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. intel? 6300ESB i/o controller hub datasheet november 2007
intel ? 6300ESB i/o controller hub ds november 2007 2 order number: 300641-004us information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the intel ? 6300ESB i/o controller hub may contain design defects or errors known as errata which may cause the product to deviate from pu blished specifications.which may cause the product to deviate from published specifications. which may cause the product to deviate fro m published specifications. current characterized errata are available on request. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? 6300ESB i/o controller hub may contain design defects or errors known as errata which may cause the product to deviate from pu blished specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct media, dialogic, dm3, etherexpress, etox, flashfile , i386, i486, i960, icomp, instantip, intel, intel centrino, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intelsx2, intel create & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel play, intel play logo, i ntel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, intel xscale, iplink, itanium, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, smartdie, so lutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress, voicebrick, vtune, and xircom are trademark s or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2007, intel corporation. all rights reserved.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 3 ?intel ? 6300ESB ich intel ? 6300ESB i/o controller hub product features ? 8-bit hub interface ? 266 mbyte/s maximum throughput ? parallel termination scheme for longer trace lengths ? supports lower voltages as per hub interface 1.5 spec ? pci-x bus i/f ? supports pci-x rev 1.0 specification at 66 mhz ? supports pci rev 2.2 specification at 33 mhz ? support external master devices on pci ? 4 @ pci 33 mhz ? 2 @ pci 64/66 mhz ? 4 @ pci-x 64/66 mhz (two slots and two soldered down devices) ? support for 64-bit addressing on pci-x using dac protocol ? pci bus i/f ? supports pci 32b/33 mhz ? 120 mbyte/s throughput ? supports pci rev 2.2 specification at 33 mhz ? supports 4 external master devices @ 33 mhz ? support for 44-bit addressing on pci using dac protocol. ? 4 slots supported ? integrated ide controller ? supports ?native mode? register and interrupts ? supports faster pio timings for non- data cycles ? independent timing of up to four drives, with separate primary and secondary ide cable connections ? supports ultra 100 dma mode transfers up to 100 mbytes/s for reads from disk; 88.88 mbytes/s for writes to disk, as well as ultra66 and ultra33 dma modes. ? pio mode four transfers up to 14 mbytes/s ? integrated serial ata host controllers ? independent dma operation on two ports ? data transfer rates up to 150 mbyte/s ? alternate device id and raid class code option for support of soft raid ? ? power management logic ? acpi 1.0 compliant ? acpi-defined power states s1 (stop grant), s3 (str), s4 (std), s5 (soff) ? acpi power management timer ?smi# generation ?pci pme# ? supports thrmtrip# input, sys_reser# input and slp_s4# output ? support for apm-based legacy power management for non-acpi implementations ? external glue integration ? integrated pull-up, pull-down and series termination resistors on ide, cpu i/f ? integrated pull-down and series resistors on usb ? enhanced hub i/f buffers improve routing flexibility (not available with all memory controller hubs) ? firmware hub (fwh) i/f supports bios memory size up to 8 mbytes ? low pin count (lpc) i/f ? new: no isa/x-bus support ? allows connections of devices such as super i/o, microcontrollers, customers asics ? supports two master/dma devices ? memory size up to 8 mbytes ? enhanced dma controller ? two cascaded 8237 dma controllers ?supports lpc dma ? supports dma collection buffer to provide type-f dma performance for all dma channels ? real-time clock ? 256-byte battery-backed cmos ram ? system tco reduction circuits ? timers to generate smi# and reset upon detection of system hang ? interrupt capability to os-specific manageability extension and os capability to call tco bios timers to detect improper cpu reset ? alert on lan (aol) to enable heartbeats and system event reporting via lan controller ?supports cpu bist ? supports ability to disable external devices
intel ? 6300ESB ich? intel ? 6300ESB i/o controller hub ds november 2007 4 order number: 300641-004us ? usb ? includes one ehci usb2 host controllers, a total of four ports (shared with the uhci ports) ? two uhci host controllers for a total of four ports (shared with ehci ports) ? new: supports a usb 2.0 high-speed debug port ? supports wake-up from sleeping states s1-s4 ? supports legacy keyboard/mouse software with usb-based keyboard and mouse ? smbus ? flexible smbus/smlink architecture to optimize for asf and eliminate board requirements of smbus 2.0 compliance ? supports smbus 2.0 specification ? host interface allows cpu to communicate via smbus ? slave interface allows an external microcontroller to access system resources ? compatible with most 2-wire components that are also i 2 c compatible ? ac'97 link for audio and telephony codecs ? new: third ac_sdata_in line for three codec support ? ac?97 2.2 compliant ? new: independent bus master logic for 8 channels (pcm in/out, mic 1 input, mic 2 input, modem in/out, s/pdif out) ? separate independent pci functions for audio and modem ? support for up four to six channels of pcm audio output (full ac3 decode) ? support for 20-bit sample ? support for acpi device states - d0 and d3 ? interrupt controller ? supports up to 12 pci interrupt pins; four are not shared ? two cascaded 82c59 with 15 interrupts ? supports pci scheme for delivering interrupts as write cycles (msi) ? integrated i/o apic capability with 24 interrupts ? supports serial interrupt protocol ? supports front-side message interrupt delivery ? new: multimedia timers based on 82c54 ? includes three timer comparators ? system timer, refresh request, speaker tone output ? one-shot and periodic interrupts supported ? new: watchdog timer ? two-stage watchdog with independent count values for each stage ? first stage generates an int or smi ? second stage drives external pin active until cleared by a system reset or power cycle ? configuration option for write-once enabling (count values can still change) ? configurable granularity from 1s to 10 min ? new: integrated 16550 compatible uarts ? enable/disable per uarts ? serial interrupts ? can disable when external sio used ? new: port 60/64 emulation ? programmable interrupt generation on writes ? positive decode to port 60/64 emulation registers ? gpio ? four gpos capable of directly driving leds ? two gpos maintain state during and after reset ? 1.5 v operation with 3.3 v i/o. 5 v tolerance on many buffers, including ide. ? package 37.5 x 37.5 mm 689 bga ? process p859.6
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 5 ?intel ? 6300ESB ich system block diagrams figure 1. workstation/pc model b2475-02 cpu graphics sm bus memory 1gb to 4 gb hublink 1.5 agp hl 1.5 pci intel ? 875p mch intel ? 6300ESB i/o controller hub gbe pci-x gbe / scsi lpc fwh / sio ide hard disk sata hard disk sata hard disk ide hard disk / cd-dvd usb 2.0 legacy peripherals ac'97 gpio
intel ? 6300ESB ich? intel ? 6300ESB i/o controller hub ds november 2007 6 order number: 300641-004us figure 2. low to mid-range communication appliance model (diskless) b2476-02 cpu memory 256 mb to 1gb hublink processor system bus hl 1.5 gbe pci-x gbe / 2d graphics hard disk sio gpio's sm bus intel ? 875p mch intel ? 6300ESB i/o controller hub
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 7 ?intel ? 6300ESB ich figure 3. value server, ultra-dense server and low-end server blade b2477-03 cpu sm bus memory 1gb to 2 gb processor system bus hublink 1.5 hl 1.5 gbe pci 2d graphics pci-x gbe lpc bmc ide hard disk hard disk sata hard disk sata hard disk ide usb 2.0 gpio intel ? e7210 mch intel ? 6300ESB i/o controller hub
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 8 order number: 300641-004us contents 1introduction ............................................................................................................49 1.1 about this document .........................................................................................49 2 intel ? 6300ESB ich and system clock domains .....................................................53 3 signal description ....................................................................................................55 3.1 hub interface to host controller ..........................................................................55 3.2 firmware hub interface ......................................................................................56 3.3 pci interface.....................................................................................................57 3.4 pci-x interface .................................................................................................60 3.5 sata interface ..................................................................................................64 3.6 ide interface ....................................................................................................64 3.7 lpc i/f.............................................................................................................66 3.8 interrupt interface.............................................................................................66 3.9 usb interface....................................................................................................67 3.10 power management interface ..............................................................................68 3.11 cpu interface....................................................................................................69 3.12 smbus interface ................................................................................................71 3.13 system management interface ............................................................................71 3.14 real time clock interface ...................................................................................71 3.15 other clocks .....................................................................................................72 3.16 miscellaneous signals .........................................................................................72 3.17 ac?97 link ........................................................................................................73 3.18 universal asynchronous receive and transmit (uart0,1) .......................................73 3.19 general purpose i/o...........................................................................................74 3.20 power and ground .............................................................................................76 3.21 pin straps.........................................................................................................77 3.21.1 functional straps....................................................................................77 3.22 revision and device id table ..............................................................................78 4intel ? 6300ESB ich power planes and pin states ....................................................79 4.1 power planes.....................................................................................................79 4.2 integrated pull-ups and pull-downs......................................................................80 4.3 ide integrated series termination resistors..........................................................81 4.4 output and i/o signals planes and states .............................................................81 4.5 power planes for input signals ............................................................................83 5 functional description .............................................................................................91 5.1 hub interface to pci bridge (d30:f0) ...................................................................91 5.1.1 pci bus interface....................................................................................91 5.1.2 pci-to-pci bridge model ..........................................................................92 5.1.3 idsel to device number mapping .............................................................92 5.1.4 serr# functionality................................................................................92 5.1.5 parity error detection..............................................................................95 5.1.6 standard pci bus configuration mechanism................................................96 5.1.6.1 type 0 to type 0 forwarding ......................................................96 5.1.6.2 type 1 to type 0 conversion.......................................................96 5.1.7 pci dual address cycle (dac) support ......................................................97 5.2 lpc bridge (with system and management functions) (d31:f0)...............................97 5.2.1 lpc cycle types .....................................................................................98 5.2.1.1 start field definition ..................................................................98 5.2.1.2 cycle type/direction (cyctype + dir).........................................99 5.2.1.3 size........................................................................................99 5.2.1.4 sync.......................................................................................99
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 9 contents?intel ? 6300ESB ich 5.2.1.5 sync time-out ...................................................................... 100 5.2.1.6 sync error indication .............................................................. 100 5.2.1.7 lframe# usage ..................................................................... 101 5.2.1.8 i/o cycles.............................................................................. 102 5.2.1.9 bus master cycles ................................................................... 102 5.2.1.10 lpc power management........................................................... 102 5.2.1.11 configuration and intel ? 6300ESB ich implications .................... 102 5.3 dma operation (d31:f0) .................................................................................. 103 5.3.1 dma overview ..................................................................................... 103 5.3.2 channel priority ................................................................................... 104 5.3.2.1 fixed priority.......................................................................... 104 5.3.2.2 rotating priority ..................................................................... 104 5.3.3 address compatibility mode ................................................................... 104 5.3.4 summary of dma transfer sizes ............................................................ 105 5.3.4.1 address shifting when programmed for 16-bit i/o count by words 105 5.3.5 autoinitialize........................................................................................ 105 5.3.6 software commands............................................................................. 106 5.3.6.1 clear byte pointer flip-flop ...................................................... 106 5.3.6.2 dma master clear ................................................................... 106 5.3.6.3 clear mask register ................................................................ 106 5.4 lpc dma ........................................................................................................ 106 5.4.1 asserting dma requests........................................................................ 106 5.4.2 abandoning dma requests .................................................................... 107 5.4.3 general flow of dma transfers............................................................... 108 5.4.4 terminal count (tc) ............................................................................. 108 5.4.5 verify mode ......................................................................................... 108 5.4.6 dma request deassertion...................................................................... 108 5.4.7 sync field/ldrq# rules....................................................................... 109 5.5 8254 timers (d31:f0) ..................................................................................... 110 5.5.1 counter 0, system timer ...................................................................... 110 5.5.2 counter 1, refresh request signal.......................................................... 110 5.5.3 counter 2, speaker tone....................................................................... 110 5.5.4 timer programming .............................................................................. 110 5.5.5 reading from the interval timer............................................................. 111 5.5.5.1 simple read........................................................................... 112 5.5.5.2 counter latch command.......................................................... 112 5.5.5.3 read back command .............................................................. 113 5.6 8259 interrupt controllers (pic) (d31:f0) .......................................................... 113 5.6.1 interrupt handling................................................................................ 114 5.6.1.1 generating interrupts.............................................................. 114 5.6.1.2 acknowledging interrupts ........................................................ 115 5.6.1.3 hardware/software interrupt sequence ..................................... 115 5.6.2 initialization command words (icwx)..................................................... 115 5.6.2.1 icw1 .................................................................................... 116 5.6.2.2 icw2 .................................................................................... 116 5.6.2.3 icw3 .................................................................................... 116 5.6.2.4 icw4 .................................................................................... 116 5.6.3 operation command words (ocw)......................................................... 116 5.6.4 modes of operation .............................................................................. 117 5.6.4.1 fully nested mode................................................................... 117 5.6.4.2 special fully-nested mode........................................................ 117 5.6.4.3 automatic rotation mode (equal priority devices)........................ 117 5.6.4.4 specific rotation mode (specific priority).................................... 117 5.6.4.5 poll mode............................................................................... 118 5.6.4.6 cascade mode ........................................................................ 118 5.6.4.7 edge and level triggered mode ................................................ 118 5.6.4.8 end of interrupt operations...................................................... 118
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 10 order number: 300641-004us 5.6.4.9 normal end of interrupt ........................................................... 119 5.6.4.10 automatic end of interrupt mode ............................................... 119 5.6.5 masking interrupts................................................................................ 119 5.6.5.1 masking on an individual interrupt request ................................ 119 5.6.5.2 special mask mode .................................................................. 119 5.6.6 steering pci interrupts.......................................................................... 119 5.6.7 special handling of irq1 and irq12........................................................ 120 5.7 advanced interrupt controller (apic) (d29:f5).................................................... 121 5.7.1 interrupt handling ................................................................................ 121 5.7.2 smi/nmi/init/extint delivery modes...................................................... 121 5.7.3 boot interrupt ...................................................................................... 122 5.7.4 interrupt mapping................................................................................. 123 5.7.5 apic bus functional description.............................................................. 124 5.7.5.1 apic bus arbitration ................................................................ 125 5.7.5.2 bus message formats .............................................................. 126 5.7.6 pci message-based interrupts................................................................ 132 5.7.6.1 theory of operation................................................................. 132 5.7.6.2 registers and bits associated with pci interrupt delivery ............. 133 5.7.7 processor system bus interrupt delivery ................................................. 133 5.7.7.1 theory of operation................................................................. 133 5.7.7.2 edge-triggered operation......................................................... 134 5.7.7.3 level-triggered operation ........................................................ 134 5.7.7.4 registers associated with processor system bus interrupt delivery 134 5.7.7.5 interrupt message format ........................................................ 134 5.8 serial interrupt (d31:f0).................................................................................. 135 5.8.1 start frame ......................................................................................... 136 5.8.2 data frames ........................................................................................ 136 5.8.3 stop frame.......................................................................................... 137 5.8.4 specific interrupts not supported via serirq........................................... 137 5.8.5 data frame format............................................................................... 137 5.9 real time clock (d31:f0) ................................................................................. 138 5.9.1 rtc overview ...................................................................................... 138 5.9.1.1 update cycles......................................................................... 139 5.9.1.2 interrupts .............................................................................. 139 5.9.1.3 lockable ram ranges .............................................................. 139 5.9.1.4 century rollover ..................................................................... 139 5.9.1.5 clearing battery-backed rtc ram ............................................. 140 5.10 processor interface (d31:f0) ............................................................................ 141 5.10.1 processor interface signals .................................................................... 141 5.10.1.1 a20m# .................................................................................. 141 5.10.1.2 init# .................................................................................... 141 5.10.1.3 ferr#/ignne# (coprocessor error) .......................................... 142 5.10.1.4 nmi ....................................................................................... 143 5.10.1.5 stpclk# and cpuslp# signals................................................. 143 5.10.2 dual processor issues ........................................................................... 143 5.10.2.1 signal differences ................................................................... 143 5.10.2.2 dual processor power management............................................ 143 5.11 power management (d31:f0) ............................................................................ 145 5.11.1 features.............................................................................................. 145 5.11.2 intel ? 6300ESB ich power states and transition rules ............................. 146 5.11.3 system power planes ............................................................................ 148 5.11.4 intel ? 6300ESB ich power planes .......................................................... 148 5.11.5 smi#/sci generation............................................................................ 149 5.11.6 dynamic processor clock control ............................................................ 152 5.11.6.1 throttling using stpclk#......................................................... 153 5.11.6.2 transition rules among s0/cx and throttling states .................... 153
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 11 contents?intel ? 6300ESB ich 5.11.6.3 stpclk# implementation notes ............................................... 154 5.11.7 sleep states ........................................................................................ 155 5.11.7.1 sleep state overview .............................................................. 155 5.11.7.2 initiating sleep state............................................................... 155 5.11.7.3 exiting sleep states ................................................................ 156 5.11.7.4 sx-g3-sx, handling power failures ........................................... 157 5.11.8 thermal management ........................................................................... 158 5.11.8.1 thrm# signal ........................................................................ 158 5.11.8.2 thrm# initiated passive cooling ............................................... 158 5.11.8.3 thrm# override software bit ................................................... 159 5.11.8.4 processor initiated passive cooling (via programmed duty cycle on stpclk#).......................................................... 159 5.11.8.5 active cooling ........................................................................ 159 5.11.9 event input signal usage ...................................................................... 159 5.11.9.1 pwrbtn# - power button ........................................................ 159 5.11.9.2 ri# - ring indicate ................................................................. 160 5.11.9.3 pme# - pci power management event ....................................... 161 5.11.9.4 sys_reset# signal ................................................................ 161 5.11.9.5 thrmtrip# signal.................................................................. 161 5.11.10 alt access mode.................................................................................. 162 5.11.10.1write only registers with read paths in alt access mode ............ 163 5.11.10.2programmable interrupt controller (pic) reserved bits................ 164 5.11.10.3read-only registers with write paths in alt access mode ............ 165 5.11.11 system power supplies, planes, and signals ............................................ 165 5.11.11.1power plane control with slp_s3#, slp_s4# and slp_s5# ......... 165 5.11.11.2pwrok signal ........................................................................ 165 5.11.11.3vrmpwrgd signal.................................................................. 166 5.11.11.4controlling leakage and power consumption during low-power states 167 5.11.12 clock generators.................................................................................. 167 5.11.13 legacy power management theory of operation ....................................... 168 5.11.13.1overview ............................................................................... 168 5.11.13.2apm feature notes.................................................................. 168 5.12 system management (d31:f0).......................................................................... 168 5.12.1 overview of system management functions............................................. 168 5.12.2 tco signal usage................................................................................. 169 5.12.2.1 intruder# signal..................................................................... 169 5.12.2.2 pin straps .............................................................................. 169 5.12.2.3 smlink signals ...................................................................... 169 5.12.3 tco theory of operation ....................................................................... 170 5.12.3.1 overview ............................................................................... 170 5.12.3.2 detecting a system lockup ...................................................... 170 5.12.3.3 handling an os lockup............................................................ 170 5.12.3.4 handling an intruder ............................................................... 171 5.12.3.5 detecting improper fwh programming ...................................... 171 5.12.3.6 handling an ecc error or other memory error ............................ 171 5.12.4 heartbeat and event reporting through smlink/smbus ............................. 172 5.12.4.1 overview ............................................................................... 172 5.13 general purpose i/o ........................................................................................ 176 5.13.1 gpio mapping...................................................................................... 176 5.13.2 power wells......................................................................................... 178 5.13.3 smi# and sci routing .......................................................................... 178 5.13.4 triggering ........................................................................................... 178 5.14 ide controller (d31:f1) ................................................................................... 178 5.14.1 overview ............................................................................................ 178 5.14.2 pio transfers ...................................................................................... 179 5.14.2.1 overview ............................................................................... 179
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 12 order number: 300641-004us 5.14.2.2 ide port decode...................................................................... 179 5.14.2.3 ide legacy mode and native mode ............................................ 179 5.14.2.4 pio ide timing modes ............................................................. 180 5.14.2.5 iordy masking ....................................................................... 181 5.14.2.6 pio 32-bit ide data port accesses............................................. 181 5.14.2.7 pio ide data port prefetching and posting .................................. 181 5.14.3 bus master function.............................................................................. 182 5.14.3.1 physical region descriptor format ............................................. 182 5.14.3.2 line buffer ............................................................................. 183 5.14.3.3 bus master ide timings ........................................................... 183 5.14.3.4 interrupts .............................................................................. 183 5.14.3.5 bus master ide operation ........................................................ 184 5.14.3.6 error conditions ...................................................................... 185 5.14.3.7 8237-like protocol .................................................................. 185 5.14.4 ultra ata/33 protocol............................................................................ 186 5.14.4.1 signal descriptions .................................................................. 186 5.14.4.2 operation............................................................................... 187 5.14.4.3 crc calculation ...................................................................... 187 5.14.5 ultra ata/66 protocol............................................................................ 188 5.14.6 ultra ata/100 protocol .......................................................................... 188 5.14.7 ultra ata/33/66/100 timing .................................................................. 188 5.15 sata host controller (d31:f2) .......................................................................... 189 5.15.1 overview ............................................................................................. 189 5.15.2 theory of operation .............................................................................. 189 5.15.2.1 standard ata emulation........................................................... 189 5.15.2.2 48-bit lba operation (logical block addressing).......................... 189 5.15.3 hot plug operation................................................................................ 189 5.15.4 power management operation ................................................................ 189 5.15.4.1 power state mappings.............................................................. 190 5.15.4.2 power state transitions............................................................ 191 5.15.4.3 smi trapping (apm)................................................................. 191 5.15.5 sata interrupts.................................................................................... 192 5.15.6 sataled#........................................................................................... 192 5.16 multimedia event timers................................................................................... 192 5.16.1 overview ............................................................................................. 192 5.16.2 timer accuracy .................................................................................... 193 5.16.3 interrupt mapping................................................................................. 193 5.16.4 periodic vs. non-periodic modes.............................................................. 193 5.16.5 enabling the timers .............................................................................. 195 5.16.6 interrupt levels.................................................................................... 195 5.16.7 handling interrupts............................................................................... 195 5.16.8 issues related to 64-bit timers with 32-bit processors............................... 195 5.17 usb uhci controllers (d29:f0 and f1)............................................................... 196 5.17.1 overview ............................................................................................. 196 5.17.2 data structures in main memory ............................................................. 196 5.17.2.1 frame list pointer ................................................................... 196 5.17.2.2 transfer descriptors (td) ......................................................... 197 5.17.2.3 queue head (qh).................................................................... 201 5.17.3 data transfers to/from main memory ...................................................... 202 5.17.3.1 executing the schedule ............................................................ 202 5.17.3.2 processing transfer descriptors................................................. 203 5.17.3.3 command register, status register, and td status bit interaction 204 5.17.3.4 transfer queuing .................................................................... 204 5.17.4 data encoding and bit stuffing ............................................................... 208 5.17.5 bus protocol......................................................................................... 208 5.17.5.1 bit ordering............................................................................ 208 5.17.5.2 sync field ............................................................................. 208
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 13 contents?intel ? 6300ESB ich 5.17.5.3 packet field formats ............................................................... 208 5.17.5.4 address fields ........................................................................ 210 5.17.5.5 frame number field ................................................................ 211 5.17.5.6 data field .............................................................................. 211 5.17.5.7 cyclic redundancy check (crc)................................................ 211 5.17.6 packet formats .................................................................................... 211 5.17.6.1 token packets ........................................................................ 211 5.17.6.2 start of frame packets ............................................................ 212 5.17.6.3 data packets .......................................................................... 212 5.17.6.4 handshake packets ................................................................. 213 5.17.6.5 handshake responses ............................................................. 213 5.17.7 usb interrupts..................................................................................... 214 5.17.7.1 overview ............................................................................... 214 5.17.7.2 transaction based interrupts.................................................... 214 5.17.7.3 non-transaction based interrupts ............................................. 216 5.17.8 usb power management ....................................................................... 216 5.17.9 usb legacy keyboard operation ............................................................ 217 5.18 usb ehci controller (d29:f7)........................................................................... 221 5.18.1 overview ............................................................................................ 221 5.18.2 ehc initialization.................................................................................. 221 5.18.2.1 power on............................................................................... 222 5.18.2.2 bios initialization ................................................................... 222 5.18.2.3 driver initialization ................................................................. 222 5.18.2.4 ehc resets ............................................................................ 222 5.18.3 data structures in main memory............................................................. 223 5.18.4 usb 2.0 enhanced host controller dma................................................... 224 5.18.4.1 periodic list execution ............................................................. 224 5.18.4.2 asynchronous list execution .................................................... 226 5.18.5 data encoding and bit stuffing ............................................................... 227 5.18.6 packet formats .................................................................................... 227 5.18.7 usb ehci interrupts and error conditions ............................................... 227 5.18.7.1 aborts on usb ehci-initiated memory reads.............................. 228 5.18.8 usb ehci power management................................................................ 228 5.18.8.1 pause feature ........................................................................ 228 5.18.8.2 suspend feature..................................................................... 229 5.18.8.3 acpi device states ................................................................. 229 5.18.8.4 acpi system states ................................................................ 229 5.18.8.5 low-power system considerations............................................. 229 5.18.9 interaction with classic host controllers .................................................. 230 5.18.9.1 port-routing logic .................................................................. 230 5.18.9.2 device connects ..................................................................... 231 5.18.9.3 device disconnects ................................................................. 231 5.18.9.4 effect of resets on port-routing logic........................................ 232 5.18.10 usb 2.0 legacy keyboard operation ....................................................... 232 5.18.11 usb 2.0 ehci based debug port............................................................. 232 5.18.11.1overview ............................................................................... 233 5.18.11.2theory of operation ................................................................ 233 5.19 smbus controller functional description (d31:f3) ............................................... 237 5.19.1 overview ............................................................................................ 237 5.19.2 host controller..................................................................................... 238 5.19.2.1 command protocols ................................................................ 239 5.19.2.2 i 2 c behavior .......................................................................... 249 5.19.2.3 heartbeat for use with the external lan controller...................... 249 5.19.3 bus arbitration..................................................................................... 249 5.19.4 bus timing .......................................................................................... 249 5.19.4.1 clock stretching ..................................................................... 249 5.19.4.2 bus time out (intel ? 6300ESB ich as smbus master) ................. 250
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 14 order number: 300641-004us 5.19.5 interrupts/smi# ................................................................................... 250 5.19.6 smbalert#......................................................................................... 251 5.19.7 smbus crc generation and checking ...................................................... 251 5.19.8 smbus slave interface........................................................................... 251 5.19.8.1 format of slave write cycle...................................................... 252 5.19.8.2 format of read command ........................................................ 254 5.19.8.3 format of host notify command................................................ 256 5.20 ac?97 controller functional description (audio d31:f5, modem d31:f6) ................. 257 5.20.1 overview ............................................................................................. 257 5.20.1.1 pci power management ........................................................... 260 5.20.2 ac-link overview ................................................................................. 260 5.20.2.1 ac-link output frame (sdout) ................................................. 263 5.20.2.2 output slot 0: tag phase ......................................................... 263 5.20.2.3 output slot 1: command address port ....................................... 264 5.20.2.4 output slot 2: command data port ........................................... 264 5.20.2.5 output slot 3: pcm playback left channel .................................. 264 5.20.2.6 output slot 4: pcm playback right channel ................................ 264 5.20.2.7 output slot 5: modem codec .................................................... 264 5.20.2.8 output slot 6: pcm playback center front channel ...................... 265 5.20.2.9 output slots 7-8: pcm playback left and right rear channels ....... 265 5.20.2.10output slot 9: playback sub woofer channel .............................. 265 5.20.2.11output slots 10-11: reserved ................................................... 265 5.20.2.12output slot 12: i/o control ...................................................... 265 5.20.2.13ac-link input frame (sdin) ..................................................... 265 5.20.2.14input slot 0: tag phase ........................................................... 267 5.20.2.15input slot 1: status address port/slot request bits ..................... 267 5.20.2.16input slot 2: status data port................................................... 268 5.20.2.17input slot 3: pcm record left channel ....................................... 268 5.20.2.18input slot 4: pcm record right channel ..................................... 268 5.20.2.19input slot 5: modem line ......................................................... 268 5.20.2.20input slot 6: optional dedicated microphone record data............. 268 5.20.2.21input slots 7-11: reserved....................................................... 268 5.20.2.22input slot 12: i/o status ......................................................... 268 5.20.2.23register access....................................................................... 269 5.20.3 ac-link low power mode ....................................................................... 270 5.20.3.1 external wake event................................................................ 270 5.20.4 ac?97 cold reset .................................................................................. 271 5.20.5 ac?97 warm reset ................................................................................ 271 5.20.6 system reset....................................................................................... 273 5.20.7 hardware assist to determine ac_sdin used per codec ............................ 273 5.20.8 software mapping of ac_sdin to dma engine .......................................... 274 6 register and memory mapping ............................................................................... 275 6.1 pci devices and functions ................................................................................ 275 6.2 pci configuration map ...................................................................................... 277 6.3 i/o map.......................................................................................................... 278 6.3.1 fixed i/o address ranges ...................................................................... 278 6.3.2 variable i/o decode ranges................................................................... 281 6.4 memory map ................................................................................................... 283 6.4.1 boot-block update scheme .................................................................... 285 7 hub interface to pci bridge registers (d30:f0) ..................................................... 287 7.1 pci configuration registers (d30:f0) ................................................................. 287 7.1.1 offset 00 - 01h: vid?vendor id register (hub-pci?d30:f0).................... 288 7.1.2 offset 02 - 03h: did?device id register (hub-pci?d30:f0) .................... 288 7.1.3 offset 04 - 05h: cmd?command register (hub-pci?d30:f0)................... 289 7.1.4 offset 06 - 07h: pd_sts?primary device status register (hub-pci?d30:f0) .. 290
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 15 contents?intel ? 6300ESB ich 7.1.5 offset 08h: rid?revision identification register (hub-pci?d30:f0) .............................................................................. 291 7.1.6 offset 0ah: scc?sub-class code register (hub-pci?d30:f0).................. 291 7.1.7 offset 0bh: bcc?base-class code register (hub-pci?d30:f0) .............................................................................. 291 7.1.8 offset 0dh: pmlt?primary master latency timer register (hub-pci?d30:f0) .. 292 7.1.9 offset 0eh: headtyp?header type register (hub-pci?d30:f0) .............................................................................. 292 7.1.10 offset 18h: pbus_num?primary bus number register (hub-pci?d30:f0) . 292 7.1.11 offset 19h: sbus_num?secondary bus number register (hub-pci?d30:f0) ... 293 7.1.12 offset 1a: sub_bus_num?subordinate bus number register (hub-pci? d30:f0)293 7.1.13 offset 1bh: smlt?secondary master latency timer register (hub-pci?d30:f0) 293 7.1.14 offset 1ch: iobase?i/o base register (hub-pci?d30:f0) ...................... 294 7.1.15 offset 1dh: iolim?i/o limit register (hub-pci?d30:f0) ........................ 295 7.1.16 offset 1e - 1fh: secsts?secondary status register (hub-pci?d30:f0) ... 295 7.1.17 offset 20 - 21h: membase?memory base register (hub-pci?d30:f0) .............................................................................. 296 7.1.18 offset 22 - 23h: memlim?memory limit register (hub-pci?d30:f0) .............................................................................. 297 7.1.19 offset 24h - 25h: pref_mem_base?prefetchable memory base register (hub-pci?d30:f0) .......................................................... 298 7.1.20 offset 26h-27h: pref_mem_mlt?prefetchable memory limit register (hub-pci?d30:f0) .......................................................... 299 7.1.21 offset 30 - 31h: iobase_hi?i/o base upper 16 bits register (hub-pci? d30:f0)299 7.1.22 offset 32 - 33h: iolim_hi?i/o limit upper 16 bits register (hub-pci?d30:f0) .............................................................................. 300 7.1.23 offset 3ch: int_line?interrupt line register (hub-pci?d30:f0) .............................................................................. 300 7.1.24 offset 3e - 3fh: bridge_cnt?bridge control register (hub-pci?d30:f0). 301 7.1.25 offset 40 - 43h: hi_cmd?hub interface command control register (hub-pci?d30:f0).................................................................. 304 7.1.26 offset 44 - 45h: device_hide?secondary pci device hiding register (hub-pci?d30:f0) ........................................................ 305 7.1.27 offset 50 - 51h: cnf?intel ? 6300ESB ich configuration register (hub-pci? d30:f0)306 7.1.28 offset 58 - 5bh: d30_pne ? perr#_nmi_enable register (hub-pci?d30:f0) 307 7.1.29 offset 70h: mtt?multi-transaction timer register (hub-pci?d30:f0) .............................................................................. 308 7.1.30 offset 82h: pci_mast_sts?pci master status register (hub-pci?d30:f0) 309 7.1.31 offset 90h: err_cmd?error command register (hub-pci?d30:f0) .............................................................................. 309 7.1.32 offset 92h: err_sts?error status register (hub-pci?d30:f0) .............................................................................. 310 7.1.33 offset f8h - fbh: manid? manufacturer?s id .......................................... 310 8 lpc i/f bridge registers (d31:f0) ........................................................................ 311 8.1 pci configuration registers (d31:f0)................................................................. 311 8.1.1 offset 00 - 01h: vid?vendor id register (lpc i/f?d31:f0) ..................... 312 8.1.2 offset 02 - 03h: did?device id register (lpc i/f?d31:f0)...................... 313 8.1.3 offset 04 - 05h: pcicmd?pci command register (lpc i/f?d31:f0) ................................................................................ 313
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 16 order number: 300641-004us 8.1.4 offset 06 - 07h: pcista?pci device status (lpc i/f?d31:f0) ................................................................................ 314 8.1.5 offset 08h: rid?revision id register (lpc i/f?d31:f0)........................... 315 8.1.6 offset 09h: pi?programming interface (lpc i/f?d31:f0) ......................... 315 8.1.7 offset 0ah: scc?sub-class code register (lpc i/f?d31:f0) ................................................................................ 315 8.1.8 offset 0bh: bcc?base-class code register (lpc i/f?d31:f0) ................................................................................ 316 8.1.9 offset 0eh: headtyp?header type register (lpc i/f?d31:f0) ................................................................................ 316 8.1.10 offset 40 - 43h: pmbase?acpi base address (lpc i/f?d31:f0) ................................................................................ 317 8.1.11 offset 44h: acpi_cntl?acpi control (lpc i/f?d31:f0)........................... 317 8.1.12 offset 4e - 4fh: bios_cntl (lpc i/f?d31:f0) ........................................ 319 8.1.13 offset 54h: tco_cntl?tco control (lpc i/f?d31:f0) ............................ 320 8.1.14 offset 58h - 5bh: gpio_base?gpio base address (lpc i/f?d31:f0) ................................................................................ 321 8.1.15 offset 5ch: gpio_cntl?gpio control (lpc i/f?d31:f0).......................... 321 8.1.16 offset pirqa - 60h: pirq[n]_rout?pirq[a,b,c,d] routing control (lpc i/f?d31:f0).......................................................... 322 8.1.17 offset 64h: serirq_cntl?serial irq control (lpc i/f?d31:f0) ................................................................................ 323 8.1.18 offset pirqe - 68h: pirq[n]_rout?pirq[e,f,g,h] routing control (lpc i/f?d31:f0) ..................................................................... 324 8.1.19 offset 88h: d31_err_cfg?device 31 error config register (lpc i/f?d31:f0) . 325 8.1.20 offset 8ah: d31_err_sts?device 31 error status register (lpc i/f?d31:f0) . 325 8.1.21 offset 90h - 91h: pci_dma_cfg?pci dma configuration (lpc i/f?d31:f0) 326 8.1.22 offset d0h - d3h: gen_cntl?general control register (lpc i/f?d31:f0) ................................................................................ 327 8.1.23 offset d4h: gen_sta?general status (lpc i/f?d31:f0).......................... 329 8.1.24 offset d5h: back_cntl?backed up control (lpc i/f?d31:f0) ................................................................................ 330 8.1.25 offset d8h: rtc_conf?rtc configuration register (lpc i/f?d31:f0) ................................................................................ 331 8.1.26 offset e0h: com_dec?lpc i/f communication port decode ranges (lpc i/f?d31:f0) .......................................................... 332 8.1.27 offset e1h: fdd/lpt_dec?lpc i/f fdd and lpt decode ranges (lpc i/f? d31:f0)333 8.1.28 offset e2h: snd_dec?lpc i/f sound decode ranges (lpc i/f?d31:f0) .... 334 8.1.29 offset e3h: fwh_dec_en1?fwh decode enable 1 register (lpc i/f?d31:f0) . 335 8.1.30 offset e4h - e5h: gen1_dec?lpc i/f generic decode range 1 (lpc i/f?d31:f0) 336 8.1.31 offset e6h - e7h: lpc_en?lpc i/f enables (lpc i/f?d31:f0) ................................................................................ 337 8.1.32 offset e8h: fwh_sel1?fwh select 1 register (lpc i/f?d31:f0) ................................................................................ 339 8.1.33 offset ech - edh: gen2_dec?lpc i/f generic decode range 2 (lpc i/f?d31:f0) .................................................................... 340 8.1.34 offset eeh - efh: fwh_sel2?fwh select 2 register (lpc i/f?d31:f0) ................................................................................ 341 8.1.35 offset f0h: fwh_dec_en2?fwh decode enable 2 register (lpc i/f?d31:f0) . 342 8.1.36 offset f2h: func_dis?function disable register (lpc i/f?d31:f0) ................................................................................ 343
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 17 contents?intel ? 6300ESB ich 8.1.37 offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0) ................................................................................ 345 8.1.38 offset f8h: manufacturer?s id ................................................................ 345 8.2 dma i/o registers........................................................................................... 346 8.2.1 dmabase_ca?dma base and current address registers .......................... 348 8.2.2 dmabase_cc?dma base and current count registers ............................. 349 8.2.3 dmamem_lp?dma memory low page registers ....................................... 350 8.2.4 dmacmd?dma command register ........................................................ 350 8.2.5 dmasta?dma status register .............................................................. 351 8.2.6 dma_wrsmsk?dma write single mask register...................................... 352 8.2.7 dmach_mode?dma channel mode register ........................................... 352 8.2.8 dma clear byte pointer register............................................................. 353 8.2.9 dma master clear register .................................................................... 354 8.2.10 dma_clmsk?dma clear mask register .................................................. 354 8.2.11 dma_wrmsk?dma write all mask register ............................................ 355 8.3 timer i/o registers ......................................................................................... 355 8.3.1 tcw ?timer control word register ........................................................ 356 8.3.1.1 rdbk_cmd?read back command............................................ 357 8.3.1.2 ltch_cmd?counter latch command ....................................... 357 8.3.2 sbyte_fmt?interval timer status byte format register........................... 358 8.3.3 counter access ports register ................................................................ 360 8.4 8259 interrupt controller (pic) registers ........................................................... 360 8.4.1 interrupt controller i/o map .................................................................. 360 8.4.2 icw1?initialization command word 1 register........................................ 361 8.4.3 icw2?initialization command word 2 register........................................ 362 8.4.4 icw3?master controller initialization command word 3 register ............... 363 8.4.5 icw3?slave controller initialization command word 3 register................. 363 8.4.6 icw4?initialization command word 4 register........................................ 364 8.4.7 ocw1?operational control word 1 (interrupt mask) register .................... 364 8.4.8 ocw2?operational control word 2 register ............................................ 365 8.4.9 ocw3?operational control word 3 register ............................................ 366 8.4.10 elcr1?master controller edge/level triggered register ........................... 367 8.4.11 elcr2?slave controller edge/level triggered register ............................. 367 8.5 advanced interrupt controller (apic0) ............................................................... 368 8.5.1 apic register map................................................................................ 368 8.5.2 ind?index register ............................................................................. 369 8.5.3 dat?data register .............................................................................. 369 8.5.4 offset fec0_0020h: irqpa?irq pin assertion register............................. 370 8.5.5 offset fec0 - eoir: eoi register ........................................................... 370 8.5.6 offset 00h: id?identification register .................................................... 371 8.5.7 offset 01h: ver?version register.......................................................... 372 8.5.8 offset 02h: arbid?arbitration id register.............................................. 372 8.5.9 offset 03h: boot_config?boot configuration register ........................... 373 8.5.10 offset 10h - 11h (vector 0) through 3e - 3fh (vector 23): redirection table 373 8.6 real time clock registers................................................................................. 375 8.6.1 i/o register address map ...................................................................... 375 8.6.2 indexed registers ................................................................................ 376 8.6.2.1 rtc_rega?register a ............................................................ 377 8.6.2.2 rtc_regb?register b (general configuration) .......................... 378 8.6.2.3 rtc_regc?register c (flag register) ...................................... 380 8.6.3 rtc_regd?register d (flag register).................................................... 380 8.7 cpu interface registers.................................................................................... 381 8.7.1 nmi_sc?nmi status and control register ............................................... 381 8.7.2 nmi_en?nmi enable (and real time clock index) ................................... 382 8.7.3 port92?fast a20 and init register ....................................................... 382
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 18 order number: 300641-004us 8.7.4 coproc_err?coprocessor error register............................................... 383 8.7.5 rst_cnt?reset control register ........................................................... 383 8.8 power management registers (d31:f0) .............................................................. 384 8.8.1 power management pci configuration registers (d31:f0) .......................... 384 8.8.1.1 offset a0h: gen_pmcon_1?general pm configuration 1 register (pm?d31:f0) ......................................................................... 385 8.8.1.2 offset a2h: gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) ......................................................................... 386 8.8.1.3 offset a4h: gen_pmcon_3?general pm configuration 3 register (pm?d31:f0)............................................................. 387 8.8.1.4 offset ach: rst_cnt2?reset control 2 register (pm?d31:f0) .... 388 8.8.1.5 offset b8h - bbh: gpi_rout?gpi routing control register (pm?d31:f0) ......................................................................... 389 8.8.1.6 offset c0h: mon_fwd_en?io monitor forward enable register (pm?d31:f0) ......................................................................... 390 8.8.1.7 offset c4h, c6h, c8h, cah: mon[n]_trp_rng?i/o monitor [4:7] trap range register for devices 4-7 (pm?d31:f0)...................... 390 8.8.1.8 offset cch: mon_trp_msk?i/o monitor trap range mask register for devices 4-7 (pm?d31:f0) ................................................... 391 8.8.2 apm i/o decode ................................................................................... 392 8.8.2.1 apm_cnt?advanced power management control port register ..... 392 8.8.2.2 apm_sts?advanced power management status port register ...... 392 8.8.3 power management i/o registers ........................................................... 393 8.8.3.1 pm1_sts?power management 1 status register......................... 394 8.8.3.2 pm1_en?power management 1 enable register .......................... 396 8.8.3.3 pm1_cnt?power management 1 control.................................... 397 8.8.3.4 pm1_tmr?power management 1 timer register ......................... 398 8.8.3.5 proc_cnt?processor control register ...................................... 398 8.8.3.6 lv2?level 2 register .............................................................. 400 8.8.3.7 gpe0_sts?general purpose event 0 status register................... 400 8.8.3.8 gpe0_en?general purpose event 0 enables register................... 404 8.8.3.9 smi_en?smi control and enable register.................................. 405 8.8.3.10 smi_sts?smi status register.................................................. 407 8.8.3.11 alt_gp_smi_en?alternate gpi smi enable register ................... 410 8.8.3.12 alt_gp_smi_sts?alternate gpi smi status register.................. 411 8.8.3.13 mon_smi?device monitor smi status and enable register........... 411 8.8.3.14 devact_sts?device activity status register............................. 412 8.8.3.15 devtrap_en? device trap enable register ............................... 414 8.8.3.16 bus_addr_track? bus address tracker.................................. 415 8.8.3.17 bus_cyc_track? bus cycle tracker........................................ 415 8.9 system management tco registers (d31:f0)...................................................... 416 8.9.1 tco register i/o map............................................................................ 416 8.9.2 tco1_rld?tco timer reload and current value ..................................... 417 8.9.3 tco1_tmr?tco timer initial value........................................................ 417 8.9.4 tco1_dat_in?tco data in register...................................................... 418 8.9.5 tco1_dat_out?tco data out register ................................................. 418 8.9.6 tco1_sts?tco1 status register........................................................... 419 8.9.7 tco2_sts?tco2 status register........................................................... 421 8.9.8 tco1_cnt?tco1 control register ......................................................... 422 8.9.9 tco2_cnt?tco2 control register ......................................................... 423 8.9.10 tco_message1 and tco_message2 registers ....................................... 423 8.9.11 offset tcobase + oeh: tco_wdstatus?tco2 control register .............. 424 8.9.12 offset tcobase + 10h: sw_irq_gen?software irq generation register... 424 8.10 general purpose i/o registers (d31:f0) ............................................................. 425 8.10.1 gpio register i/o address map .............................................................. 425 8.10.2 offset gpiobase + 00h: gpio_use_sel?gpio use select register ........... 426 8.10.3 offset gpiobase + 04h: gp_io_sel?gpio input/output select register .... 426
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 19 contents?intel ? 6300ESB ich 8.10.4 offset gpiobase + 0ch: gp_lvl?gpio level for input or output register.. 427 8.10.5 offset gpiobase + 18h: gpo_blink?gpo blink enable register ............... 429 8.10.6 offset gpiobase + 2ch: gpi_inv?gpio signal invert register ................. 430 8.10.7 offset gpiobase + 30h:gpio_use_sel2?gpio use select 2 register........ 431 8.10.8 offset gpiobase + 34h: gp_io_sel2?gpio input/output select 2 register 432 8.10.9 offset gpiobase + 38h: gp_lvl2?gpio level for input or output 2 register ... 432 9 ide controller registers (d31:f1) ......................................................................... 435 9.1 pci configuration registers (ide?d31:f1) ......................................................... 435 9.1.1 offset 00 - 01h: vid?vendor id register (lpc i/f?d31:f1) ..................... 436 9.1.2 offset 02 - 03h: did?device id register (lpc i/f?d31:f1)...................... 436 9.1.3 offset 04h - 05h: cmd?command register (ide?d31:f1) ....................... 437 9.1.4 offset 06 - 07h: sts?device status register (ide?d31:f1) ..................... 438 9.1.5 offset 08h: rid?revision id register (ide?d31:f1) ............................... 439 9.1.6 offset 09h: pi?programming interface (ide?d31:f1).............................. 439 9.1.7 offset 0ah: scc?sub class code (ide?d31:f1) ..................................... 440 9.1.8 offset 0bh: bcc?base class code (ide?d31:f1) .................................... 441 9.1.9 offset 0dh: mlt?master latency timer (ide?d31:f1)............................. 441 9.1.10 offset 10h - 13h: pcmd_bar?primary command block base address register (ide?d31:f1) ..................................................... 441 9.1.11 offset 14h - 17h: pcnl_bar?primary control block base address register (ide?d31:f1)............................................................. 442 9.1.12 offset 18h - 1bh: scmd_bar?secondary command block base address register (ide d31:f1) ....................................................... 442 9.1.13 offset 1ch - 1fh: scnl_bar?secondary control block base address register (ide d31:f1) ....................................................... 443 9.1.14 offset 20h - 23h: bm_base?bus master base address register (ide?d31:f1).. 443 9.1.15 offset 24h - 27h: cpba ? ide command posting base address................... 444 9.1.16 offset 2ch - 2dh: ide_svid?subsystem vendor id (ide?d31:f1) ..................................................................................... 445 9.1.17 offset 2eh - 2fh: ide_sid?subsystem id (ide?d31:f1) ......................... 446 9.1.18 offset 3ch: intr_ln?interrupt line register (ide?d31:f1) ..................................................................................... 446 9.1.19 offset 3dh: intr_pn?interrupt pin register (ide?d31:f1) ...................... 447 9.1.20 ide_tim?ide timing register (ide?d31:f1).......................................... 447 9.1.21 offset 44h: slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) ... 451 9.1.22 offset 48h: sdma_cnt?synchronous dma control register (ide?d31:f1). 452 9.1.23 offset 4a - 4bh: sdma_tim?synchronous dma timing register (ide?d31:f1). 453 9.1.24 ide_config?ide i/o configuration register (ide?d31:f1) ..................................................................................... 455 9.2 bus master ide i/o registers (d31:f1) .............................................................. 455 9.2.1 bmic[p,s]?bus master ide command register........................................ 456 9.2.2 bmis[p,s]?bus master ide status register ............................................. 457 9.2.3 bmid[p,s]?bus master ide descriptor table pointer register .................... 459 10 usb uhci controllers registers ............................................................................. 461 10.1 pci configuration registers (d29:f0/f1) ............................................................ 461 10.1.1 offset 00 - 01h: vid?vendor identification register (usb?d29:f0/f1)................................................................................ 462 10.1.2 offset 02 - 03h: did?device identification register (usb?d29:f0/f1)................................................................................ 462 10.1.3 offset 04 - 05h: cmd?command register (usb?d29:f0/f1)................................................................................ 463
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 20 order number: 300641-004us 10.1.4 offset 06 - 07h: sta?device status register (usb?d29:f0/f1) ................................................................................ 464 10.1.5 offset 08h: rid?revision identification register (usb?d29:f0/f1) ................................................................................ 464 10.1.6 offset 09h: pi?programming interface (usb?d29:f0/f1)......................... 465 10.1.7 offset 0ah: scc?sub class code register (usb?d29:f0/f1) ................................................................................ 465 10.1.8 offset 0bh: bcc?base class code register (usb?d29:f0/f1) ................................................................................ 465 10.1.9 offset 0dh: mlt?master latency timer................................................... 465 10.1.10offset 0eh: htype?header type register (usb?d29:f0/f1) ................................................................................ 466 10.1.11offset 20 - 23h: base?base address register (usb?d29:f0/f1) ................................................................................ 467 10.1.12offset 2ch - 2dh: svid?subsystem vendor id (usb?d29:f0/f1) ................................................................................ 467 10.1.13offset 2eh-2fh: sid?subsystem id (usb?d29:f0/f1)............................. 468 10.1.14offset 3ch: intr_ln?interrupt line register (usb?d29:f0/f1) ................................................................................ 468 10.1.15offset 3dh: intr_pn?interrupt pin register (usb?d29:f0/f1) ................................................................................ 469 10.1.16offset 60h: usb_relnum?usb release number register (usb?d29:f0/f1) ................................................................................ 469 10.1.17offset c0 - c1h: usb_legkey?usb legacy keyboard/ mouse control register (usb?d29:f0/f1) ............................................... 469 10.1.18offset c4h: usb_res?usb resume enable register (usb?d29:f0/f1) ...... 472 10.2 usb i/o registers............................................................................................ 473 10.2.1 offset 00 - 01h: usbcmd?usb command register .................................. 473 10.2.2 offset 02 - 03h: usbsta?usb status register......................................... 478 10.2.3 offset base + (04 - 05h): usbintr?interrupt enable register................... 479 10.2.4 offset base + (06 - 07h): frnum?frame number register........................ 481 10.2.5 offset base + (08 - 0bh): frbaseadd?frame list base address ............... 481 10.2.6 offset base + och: sofmod?start of frame modify register .................... 482 10.2.7 portsc[0,1]?port status and control register ........................................ 483 11 usb ehci controller registers (d29:f7) 485 11.1 usb ehci configuration registers (d29:f7) ........................................................ 485 11.1.1 offset 04 - 05h: command register ........................................................ 486 11.1.2 offset 06 - 07h: device status ............................................................... 487 11.1.3 offset 08h: rid?revision id register ..................................................... 489 11.1.4 offset 09h: programming interface ......................................................... 489 11.1.5 offset 0ah: sub class code.................................................................... 489 11.1.6 offset 0bh: base class code .................................................................. 490 11.1.7 offset 0dh: master latency timer........................................................... 490 11.1.8 offset 10 - 13h: memory base address.................................................... 490 11.1.9 offset 2c - 2dh: usb ehci subsystem vendor id ..................................... 491 11.1.10offset 2e - 2fh: sid?usb ehci subsystem id......................................... 491 11.1.11offset 34h: capabilities pointer............................................................... 491 11.1.12offset 3ch: interrupt line...................................................................... 492 11.1.13offset 3dh: interrupt pin ....................................................................... 492 11.1.14offset 50h: pci power management capability id ..................................... 492 11.1.15offset 51h: next item pointer #1............................................................ 493 11.1.16offset 52 - 53h: power management capabilities ...................................... 493 11.1.17offset 54 - 55h: power management control/status .................................. 494 11.1.18offset 58h: debug port capability id....................................................... 495
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 21 contents?intel ? 6300ESB ich 11.1.19 offset 59h: next item pointer #2 ........................................................... 496 11.1.20 offset 5ah - 5bh: debug port base offset................................................ 496 11.1.21 offset 60h: serial bus release number ................................................... 496 11.1.22 offset 61h: frame length adjustment..................................................... 496 11.1.23 offset 62 - 63h: port wake capability ..................................................... 497 11.1.24 offset 64 - 65h: classic usb override ..................................................... 498 11.1.25 offset 68 - 6bh: usb ehci legacy support extended capability ................. 499 11.1.26 offset 6c - 6fh: usb ehci legacy support extended control/status ........... 500 11.1.27 offset 70 - 73h: intel specific usb ehci smi ........................................... 501 11.1.28 offset 80h: access control .................................................................... 503 11.1.29 hs_ ref_v_usb hs reference voltage register........................................ 503 11.2 memory-mapped i/o registers .......................................................................... 503 11.2.1 host controller capability registers ........................................................ 504 11.2.1.1 offset 00h: caplength?capability registers length .................. 504 11.2.1.2 offset 02 - 03h: hciversion?host controller interface version number505 11.2.1.3 offset 04 - 07h: hcsparams?host controller structural parameters .. 505 11.2.1.4 offset 08 - 0bh: hccparams?host controller capability parameters .. 507 11.2.2 host controller operational registers ...................................................... 508 11.2.2.1 offset caplength + 00 - 03h: usb ehci cmd?usb ehci command register.......................................................... 509 11.2.2.2 offset caplength + 04 - 07h: usb ehci sts?usb ehci status . 512 11.2.2.3 offset caplength + 08 - 0bh: usb ehci intr?usb ehci interrupt enable ............................................................. 514 11.2.2.4 offset caplength + 0c - 0fh: frindex?frame index ............... 514 11.2.2.5 offset caplength + 10 - 13h: ctrldssegment?control data structure segment register ..................................................... 515 11.2.2.6 offset caplength + 14 - 17h: periodiclistbase?periodic frame list base address.................................................................... 516 11.2.2.7 offset caplength + 18 - 1bh: asynclistaddr?current asynchronous list address ....................................................... 516 11.2.2.8 offset caplength + 40 - 43h: configflag?configure flag register. 517 11.2.2.9 portsc- port n status and control ........................................... 517 11.2.3 usb 2.0-based debug port register........................................................ 522 11.2.3.1 offset 00h: control/status register........................................... 522 11.2.3.2 offset 04h: usb pids register.................................................. 525 11.2.3.3 offset 08h: data buffer bytes 7:0 ............................................. 525 11.2.3.4 offset 10h: config register ...................................................... 526 12 smbus controller registers (d31:f3) 527 12.1 pci configuration registers (smbus?d31:f3) .................................................... 527 12.1.1 offset 00 - 01h: vid?vendor identification register (smbus?d31:f3)....... 527 12.1.2 offset 02 - 03h: did?device identification register (smbus?d31:f3) ....... 528 12.1.3 offset 04 - 05h: cmd?command register (smbus?d31:f3) ................................................................................ 528 12.1.4 offset 06 - 07h: sta?device status register (smbus?d31:f3) ................................................................................ 529 12.1.5 offset 08h: rid?revision id register (smbus?d31:f3) .......................... 529 12.1.6 offset 09h: pi?programming interface (smbus?d31:f3)......................... 530 12.1.7 offset 0ah: scc?sub class code register (smbus?d31:f3) ................................................................................ 530 12.1.8 offset 0bh: bcc?base class code register (smbus?d31:f3) ................................................................................ 530
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 22 order number: 300641-004us 12.1.9 offset 20 - 23h: smb_base?smbus base address register (smbus?d31:f3) .................................................................... 531 12.1.10offset 2ch - 2dh: svid?subsystem vendor id (smbus?d31:f2/f4)............................................................................ 531 12.1.11offset 2eh - 2fh: sid?subsystem id (smbus?d31:f2/f4)....................... 532 12.1.12offset 3ch: intr_ln?interrupt line register (smbus?d31:f3) ................................................................................ 532 12.1.13offset 3dh: intr_pn?interrupt pin register (smbus?d31:f3) ................................................................................ 532 12.1.14offset 40h: hostc?host configuration register (smbus?d31:f3) ................................................................................ 533 12.2 smbus i/o registers........................................................................................ 533 12.2.1 offset 00h: hst_sts?host status register ............................................. 534 12.2.2 offset 02h: hst_cnt?host control register............................................ 537 12.2.3 offset 03h: hst_cmd?host command register ....................................... 539 12.2.4 offset 04h: xmit_slva?transmit slave address register ......................... 539 12.2.5 offset 05h: hst_d0?data 0 register...................................................... 540 12.2.6 offset 06h: hst_d1?data 1 register...................................................... 540 12.2.7 offset 07h: host_block_db?host block data byte register...................... 541 12.2.8 offset 08h: pec?packet error check register .......................................... 542 12.2.9 offset 09h: rcv_slva?receive slave address register ............................ 542 12.2.10offset 0ah: slv_data?receive slave data register................................. 543 12.2.11offset 0ch: aux_sts?auxiliary status register ....................................... 543 12.2.12offset 0dh: aux_ctl?auxiliary control register ...................................... 544 12.2.13offset 0eh: smlink_pin_ctl?smlink pin control register........................ 544 12.2.14offset 0fh: smbus_pin_ctl?smbus pin control register......................... 545 12.2.15offset 10h: slv_sts?slave status register ............................................ 545 12.2.16offset 11h: slv_cmd?slave command register...................................... 546 12.2.17offset 14h: notify_daddr?notify device address .................................. 547 12.2.18offset 16h: notify_dlow?notify data low byte register ........................ 548 12.2.19offset 17h: notify_dhigh?notify data high byte register ...................... 548 13 ac?97 audio controller registers (d31:f5) ............................................................ 549 13.1 ac?97 audio pci configuration space (d31:f5).................................................... 549 13.1.1 offset 00 - 01h: vid?vendor identification register (audio?d31:f5) ......... 551 13.1.2 offset 02 - 03h: did?device identification register (audio?d31:f5).......... 551 13.1.3 offset 04 - 05h: pcicmd?pci command register (audio?d31:f5)................................................................................... 552 13.1.4 offset 06 - 07h: pcists?pci device status register (audio?d31:f5) ........ 552 13.1.5 offset 08h: rid?revision identification register (audio?d31:f5)................................................................................... 554 13.1.6 offset 09h: pi?programming interface register (audio?d31:f5)................................................................................... 554 13.1.7 offset 0ah: scc?sub class code register (audio?d31:f5)................................................................................... 554 13.1.8 offset 0bh: bcc?base class code register (audio?d31:f5)................................................................................... 555 13.1.9 offset 0eh: hedt?header type register (audio?d31:f5)......................... 555 13.1.10offset 10 - 13h: nambar?native audio mixer base address register (audio?d31:f5) .......................................... 555 13.1.11offset 14 - 17h: nabmbar?native audio bus mastering base address register (audio?d31:f5)................................................... 556 13.1.12offset 18 - 1bh: mmbar?mixer base address register (audio?d31:f5)...... 557 13.1.13offset 1c - 1fh: mbbar?bus master base address register (audio?d31:f5).... 558 13.1.14offset 2d - 2ch: svid?subsystem vendor id register (audio?d31:f5) ..... 559
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 23 contents?intel ? 6300ESB ich 13.1.15 offset 2e - 2fh: sid?subsystem id register (audio?d31:f5) .................................................................................. 559 13.1.16 offset 34h: cap_ptr?capabilities pointer (audio?d31:f5) .................................................................................. 560 13.1.17 offset 3ch: intr_ln?interrupt line register (audio?d31:f5) .................................................................................. 560 13.1.18 offset 3dh: intr_pn?interrupt pin register (audio?d31:f5) .................................................................................. 561 13.1.19 offset 40h: pcid?programmable codec id register (audio?d31:f5) .................................................................................. 561 13.1.20 offset 41h: cfg?configuration register (audio?d31:f5) ......................... 562 13.1.21 offset 50h: pid?pci power management capability id register (audio?d31:f5) 562 13.1.22 offset 52h: pc?power management capabilities register (audio?d31:f5) .. 563 13.1.23 offset 54h: pcs?power management control and status register (audio? d31:f5)563 13.2 ac?97 audio i/o space (d31:f5) ....................................................................... 564 13.2.1 x_bdbar?buffer descriptor base address register .................................. 568 13.2.2 x_civ?current index value register ...................................................... 568 13.2.3 x_lvi?last valid index register ............................................................ 569 13.2.4 x_sr?status register .......................................................................... 569 13.2.5 x_picb?position in current buffer register ............................................. 571 13.2.6 x_piv?prefetched index value register .................................................. 571 13.2.7 x_cr?control register ......................................................................... 572 13.2.8 glob_cnt?global control register........................................................ 572 13.2.9 glob_sta?global status register ......................................................... 574 13.2.10 cas?codec access semaphore register ................................................. 578 13.2.11 sdm?sdata_in map register ............................................................... 578 14 ac?97 modem controller registers (d31:f6) .......................................................... 581 14.1 ac?97 modem pci configuration space (d31:f6) ................................................. 581 14.1.1 offset 00 - 01h: vid?vendor identification register (modem?d31:f6) ...... 582 14.1.2 offset 02 - 03h: did?device identification register (modem?d31:f6) ....... 582 14.1.3 offset 04 - 05h: pcicmd?pci command register (modem?d31:f6).......... 583 14.1.4 offset 06 - 07h: pcista?device status register (modem?d31:f6) ................................................................................ 584 14.1.5 offset 08h: rid?revision identification register (modem?d31:f6) ................................................................................ 585 14.1.6 offset 09h: pi?programming interface register (modem?d31:f6) ................................................................................ 585 14.1.7 offset 0ah: scc?sub class code register (modem?d31:f6) ................................................................................ 585 14.1.8 offset 0bh: bcc?base class code register (modem?d31:f6) ................................................................................ 586 14.1.9 offset 0eh: hedt?header type register (modem?d31:f6) ...................... 586 14.1.10 offset 10 - 13h: mmbar?modem mixer base address register (modem?d31:f6) 586 14.1.11 offset 14 - 17h: mbar?modem base address register (modem?d31:f6) ... 587 14.1.12 offset 2c - 2dh: svid?subsystem vendor id (modem?d31:f6) ................................................................................ 588 14.1.13 offset 2e - 2fh: sid?subsystem id (modem?d31:f6) ............................ 588 14.1.14 offset 34h: cap_ptr?capabilities pointer (modem?d31:f6) ................................................................................ 589 14.1.15 offset 3ch: intr_ln?interrupt line register (modem?d31:f6) ................................................................................ 589 14.1.16 offset 3dh: int_pin?interrupt pin (modem?d31:f6) .............................. 590
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 24 order number: 300641-004us 14.1.17offset 50h: pid?pci power management capability id register (modem? d31:f6)590 14.1.18offset 52h: pc?power management capabilities register (modem?d31:f6) 591 14.1.19offset 54h: pcs?power management control and status register (modem? d31:f6)591 14.2 ac?97 modem i/o space (d31:f6) ..................................................................... 593 14.2.1 x_bdbar?buffer descriptor list base address register............................. 595 14.2.2 x_civ?current index value register ...................................................... 595 14.2.3 x_lvi?last valid index register............................................................. 596 14.2.4 x_sr?status register........................................................................... 596 14.2.5 x_picb?position in current buffer register.............................................. 597 14.2.6 x_piv?prefetch index value register...................................................... 599 14.2.7 x_cr?control register.......................................................................... 599 14.2.8 glob_cnt?global control register ........................................................ 600 14.2.9 glob_sta?global status register ......................................................... 601 14.2.10cas?codec access semaphore register.................................................. 604 15 multimedia timer registers ................................................................................... 605 15.1 memory mapped registers ................................................................................ 605 15.1.1 behavioral rules................................................................................... 605 15.1.2 offset 000-007h: general capabilities and id register............................... 606 15.1.3 offset 010-017h: general config register ................................................ 607 15.1.4 offset 020-027h: general interrupt status register................................... 608 15.1.5 offset 0f0 - 0f7h: main counter value ..................................................... 609 15.1.6 timer n config and capabilities............................................................... 609 15.1.7 timer n comparator value ..................................................................... 613 16 watchdog timer (wdt) (d29:f4) .......................................................................... 615 16.1 product features ............................................................................................. 615 16.2 product overview ............................................................................................ 616 16.3 signal descriptions .......................................................................................... 617 16.4 device 29: function 4 configuration registers ..................................................... 617 16.4.1 configuration registers ......................................................................... 617 16.4.2 memory mapped registers ..................................................................... 618 16.4.3 offset 00h: vid?vendor identification register ........................................ 618 16.4.4 offset 02h: did?device identification register ........................................ 619 16.4.5 offset 04 - 05h: com?command register ............................................... 619 16.4.6 offset 06h - 07h: ds?device status register........................................... 620 16.4.7 offset 08h: rid?revision identification register ...................................... 621 16.4.8 offset 09h: pi?programming interface register ....................................... 622 16.4.9 offset 0ah: scc?sub class code register............................................... 622 16.4.10offset 0bh: bcc?base code class register.............................................. 622 16.4.11offset 0eh: hedt?header type register ................................................. 622 16.4.12offset 10h: bar?base address register.................................................. 623 16.4.13offset 2dh - 2ch: svid?subsystem vendor id ........................................ 623 16.4.14offset 2eh - 2fh: sid?subsystem id...................................................... 624 16.4.15offset 60 - 61h: wdt configuration register ............................................ 625 16.4.16offset 68h: wdt lock register ............................................................... 625 16.4.17offset f8 - fbh: manufacturer?s id .......................................................... 627 16.4.18offset base + 00h: preload value 1 register ............................................ 627 16.4.19offset base + 04h: preload value 2 register ............................................ 628 16.4.20offset base + 08h: general interrupt status register ................................ 628 16.4.21offset base + 0ch: reload register......................................................... 629 16.5 theory of operation......................................................................................... 629 16.5.1 rtc well and wdt_tout# functionality.................................................. 629 16.5.2 register unlocking sequence.................................................................. 629
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 25 contents?intel ? 6300ESB ich 16.5.3 reload sequence.................................................................................. 630 16.5.4 low power state .................................................................................. 630 17 apic1 configuration registers (d29:f5) 631 17.1 apic1 configuration registers (d29:f5) ............................................................. 631 17.1.1 offset 00 - 03h: vid_did?vendor/id register (apic1?d29:f5).................................................................................. 632 17.1.2 offset 04 - 05h: apic1cmd?apic1 command register (apic1?d29:f5) ... 632 17.1.3 offset 06 - 07h: apic1sta?apic1 device status (apic1?d29:f5).................................................................................. 633 17.1.4 offset 08h: rid?revision id register (apic1?d29:f5) ............................ 634 17.1.5 offset 09 - 0bh: cc?class code register (apic1?d29:f5) ....................... 634 17.1.6 offset 0c - 0fh: headtyp?header type register (apic1?d29:f5).................................................................................. 635 17.1.7 offset 2c - 2fh: ss?apic1 subsystem identifiers (apic1?d29:f5).................................................................................. 635 17.1.8 offset 34h: cap_ptr?apic1 capabilities pointer (apic1?d29:f5).................................................................................. 636 17.1.9 offset 3ch: iline?interrupt line (apic1?d29:f5) .................................. 636 17.1.10 offset 3dh: ipin?interrupt pin (apic1?d29:f5) ..................................... 636 17.1.11 offset 40 - 41h: abar?apic1 alternate base address register (apic1?d29:f5) 637 17.1.12 offset 44 - 47h: mbar?apic1 memory base register (apic1?d29:f5) ...... 637 17.1.13 offset 50 - 51h: xid?pci-x identifiers register (apic1?d29:f5).................................................................................. 639 17.1.14 offset 52h: xsr?pci-x status register (apic1?d29:f5) ......................... 639 17.2 advanced interrupt controller (apic) ................................................................. 640 17.2.1 apic1 direct register map ..................................................................... 640 17.2.2 ind?index register ............................................................................. 640 17.2.3 dat?data register .............................................................................. 641 17.2.4 irqpa?irq pin assertion register ......................................................... 641 17.2.5 eoir?eoi register .............................................................................. 642 17.2.6 offset 00h: id?identification register .................................................... 643 17.2.7 offset 01h: ver?version register.......................................................... 643 17.2.8 offset 03h: boot_config?boot configuration register ........................... 644 17.2.9 redirection table ................................................................................. 644 18 pci-x overview (d28:f0) ...................................................................................... 647 18.1 i/o window addressing.................................................................................... 647 18.2 memory window addressing ............................................................................. 648 18.2.1 memory base and limit address registers ............................................... 648 18.2.2 prefetchable memory base and limit address registers, upper 32-bit registers .. 648 18.3 vga addressing .............................................................................................. 649 18.4 configuration addressing.................................................................................. 650 18.4.1 type 0 accesses to the intel ? 6300ESB ich ............................................ 650 18.4.2 type 1 to type 0 translation.................................................................. 650 18.4.3 type 1 to type 1 forwarding ................................................................. 651 18.4.4 type 1 to special cycle forwarding......................................................... 651 18.5 transaction ordering ....................................................................................... 652 18.5.1 comparison of rules vs. a pci ? pci bridge ............................................. 652 18.5.2 other notes......................................................................................... 652 18.6 device 28 ? hub interface to pci-x bridge.......................................................... 653 18.6.1 configuration space registers................................................................ 653 18.6.1.1 register summary .................................................................. 653
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 26 order number: 300641-004us 18.6.1.2 offset 00: id?identifiers ......................................................... 654 18.6.1.3 offset 04: cmd?command ...................................................... 655 18.6.1.4 offset 06: psts?primary status ............................................... 656 18.6.1.5 offset 08: rid?revision id...................................................... 658 18.6.1.6 offset 09: cc?class code........................................................ 659 18.6.1.7 offset 0c: cls?cache line size ............................................... 659 18.6.1.8 offset 0d: plt?primary latency timer ...................................... 660 18.6.1.9 offset 0e: htype?header type ................................................ 660 18.6.1.10offset 18: bnum?bus numbers ................................................ 661 18.6.1.11offset 1b: slt?secondary latency timer .................................. 661 18.6.1.12offset 1c: iobl?i/o base and limit .......................................... 662 18.6.1.13offset 1e: ssts?secondary status ........................................... 663 18.6.1.14offset 20: mbl?memory base and limit .................................... 664 18.6.1.15offset 24: pmbl?prefetchable memory base and limit................. 665 18.6.1.16offset 28: pmbu32?prefetchable memory base upper 32 bits....... 665 18.6.1.17offset 2c: pmlu32?prefetchable memory limit upper 32 bits....... 666 18.6.1.18offset 30: ioblu16?i/o base and limit upper 16 bits................. 666 18.6.1.19offset 34: capp?capabilities list pointer ................................... 667 18.6.1.20offset 3c: intr?interrupt information ...................................... 667 18.6.1.21offset 3e: bctrl?bridge control .............................................. 667 18.6.1.22offset 40: cnf?intel ? 6300ESB i/o controller hub configuration . 671 18.6.1.23offset 42: mtt?multi-transaction timer .................................... 673 18.6.1.24offset 44: strp?pci strap status ............................................ 674 18.6.1.25offset 50: px_capid?pci-x capabilities identifier ...................... 674 18.6.1.26offset 51: px_nxtp?next item pointer ..................................... 674 18.6.1.27offset 52: px_ssts?pci-x secondary status ............................. 675 18.6.1.28offset 54: px_bsts - pci-x bridge status .................................. 676 18.6.1.29offset 58: px_ustc - pci-x upstream split transaction control .... 678 18.6.1.30offset 5c: px_dstc - pci-x downstream split transaction control 678 18.6.1.31offset e0: acnf ? additional intel ? 6300ESB ich configuration .... 680 18.6.1.32offset e4: pcr - pci compensation register ............................... 681 18.6.1.33offset f0: hccr - hub interface command/control register ......... 682 18.6.1.34offset f8h ? offset ffh: prefetch control registers ...................... 682 18.6.1.35offset f8h: pc33 - prefetch control ? 33 mhz ............................. 683 18.6.1.36offset fah: pc66 - prefetch control ? 66 mhz ............................. 683 18.7 pci mode in the pci-x interface......................................................................... 684 18.7.1 summary of changes ............................................................................ 684 18.7.2 transaction types................................................................................. 684 18.7.3 detection of 64-bit environment ............................................................. 685 18.7.4 data bus ............................................................................................. 685 18.7.5 write transactions ................................................................................ 685 18.7.5.1 posted ................................................................................... 685 18.7.5.2 non-posted ............................................................................ 686 18.7.5.3 fast back-to-back ................................................................... 686 18.7.6 read transactions ................................................................................ 686 18.7.6.1 prefetchable ........................................................................... 686 18.7.6.2 delayed ................................................................................. 686 18.7.7 transaction termination ........................................................................ 686 18.7.7.1 normal master termination....................................................... 686 18.7.7.2 master abort termination ......................................................... 686 18.7.7.3 target termination received by the intel ? 6300ESB ich.............. 687 18.7.7.4 target termination initiated by the intel ? 6300ESB ich .............. 687 18.7.8 lock cycles ........................................................................................ 687 18.7.9 error handling...................................................................................... 687 18.7.9.1 data parity errors.................................................................... 689 18.7.9.2 system errors......................................................................... 690 18.8 pci-x interface ............................................................................................... 691 18.8.1 command encoding .............................................................................. 691
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 27 contents?intel ? 6300ESB ich 18.8.2 attributes............................................................................................ 691 18.8.3 special notes for burst transactions ....................................................... 692 18.8.4 device select timing ............................................................................ 692 18.8.5 wait states ......................................................................................... 692 18.8.6 split transactions................................................................................. 693 18.8.6.1 completer attributes ............................................................... 693 18.8.6.2 requirements for accepting split completions ............................ 693 18.8.6.3 split completion messages ....................................................... 693 18.8.6.4 arbitration among multiple split completions.............................. 693 18.8.7 transaction termination as a pci-x target .............................................. 694 18.8.7.1 retry .................................................................................... 694 18.8.7.2 split response........................................................................ 694 18.8.7.3 master-abort .......................................................................... 694 18.8.8 arbitration........................................................................................... 694 18.8.9 bridge buffer requirements ................................................................... 694 18.8.10 locked transactions ............................................................................. 694 18.8.11 error support ...................................................................................... 695 18.8.11.1general ................................................................................. 695 18.8.11.2special parity error rule for split response ................................ 695 18.9 transaction termination translation between interfaces ....................................... 695 18.9.1 behavior of hub interface initiated cycles to pci/pci-x receiving immediate terminations ......................................................... 695 18.9.2 behavior of hub interface initiated cycles to pci-x receiving split terminations. 696 18.9.3 hub interface action on immediate responses to pci-x split completions ... 697 18.9.4 behavior of pci/pci-x initiated cycles to hub interface ............................. 698 18.10 delayed/split transactions ............................................................................... 698 18.10.1 number supported ............................................................................... 698 18.10.2 prefetch algorithm................................................................................ 699 18.10.2.1parameters ............................................................................ 699 18.10.2.2algorithm (single device only) ................................................. 699 18.10.3 algorithm (multiple pci-x devices requesting) ......................................... 700 18.10.4 accesses from multiple agents to same 4k page ...................................... 700 18.11 internal bus/device communication .................................................................. 700 18.12 data return behavior of hub interface initiated reads ......................................... 701 18.13 performance targets........................................................................................ 701 18.13.1 introduction ........................................................................................ 701 18.13.2 definitions and assumptions .................................................................. 701 18.13.3 active master clock counts.................................................................... 702 19 serial i/o unit ....................................................................................................... 703 19.1 features ........................................................................................................ 703 19.2 pin description................................................................................................ 704 19.2.1 universal asynchronous receive and transmit (uart0, uart1) ................. 704 19.3 functional description...................................................................................... 706 19.3.1 host processor interface (lpc) ............................................................... 706 19.4 lpc interface.................................................................................................. 706 19.4.1 lpc cycles .......................................................................................... 706 19.4.1.1 i/o read and write cycles ....................................................... 706 19.4.2 reset policy......................................................................................... 707 19.4.3 lpc transfers ...................................................................................... 707 19.4.3.1 i/o transfers ......................................................................... 707 19.5 logical device 4 and 5: serial ports (uarts)....................................................... 707 19.5.1 overview ............................................................................................ 707 19.5.1.1 uart feature list ................................................................... 708 19.5.1.2 uart operational description ................................................... 709
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 28 order number: 300641-004us 19.5.1.3 internal register descriptions ................................................... 710 19.5.1.4 fifo operation ....................................................................... 723 19.6 logical device 7 (07h): port 60/64 emulation...................................................... 724 19.6.1 feature list ......................................................................................... 724 19.6.2 overview ............................................................................................. 724 19.6.2.1 port 60h emulation (scr60)..................................................... 725 19.6.2.2 port 64h emulation (scr64)..................................................... 725 19.7 serial irq....................................................................................................... 725 19.7.1 timing diagrams for siu_serirq cycle .................................................. 725 19.7.1.1 siu_serirq cycle control ....................................................... 726 19.7.1.2 siu_serirq data frame.......................................................... 727 19.7.1.3 stop cycle control................................................................... 727 19.7.1.4 latency.................................................................................. 728 19.7.1.5 eoi/isr read latency.............................................................. 728 19.7.1.6 reset and initialization............................................................. 728 19.8 configuration .................................................................................................. 728 19.8.1 configuration port address selection ....................................................... 728 19.8.2 primary configuration address decoder ................................................... 728 19.8.2.1 entering the configuration state ............................................... 729 19.8.2.2 exiting the configuration state.................................................. 729 19.8.2.3 configuration sequence ........................................................... 729 19.8.2.4 configuration mode ................................................................. 729 19.8.3 siu configuration registers summary ..................................................... 730 19.8.3.1 global control/configuration registers [00h ? 2fh]..................... 731 19.8.3.2 logical device configuration registers [30h ? ffh] ..................... 731 20 serial ata controller registers (d31:f2) 737 20.1 pci configuration registers (sata?d31:f2) ........................................................ 737 20.1.1 offset 00 - 01h: vid?vendor id register (sata?d31:f2) ........................ 738 20.1.2 offset 02 - 03h: did?device id register (sata?d31:f2)......................... 739 20.1.3 offset 04h - 05h: cmd?command register (sata?d31:f2)....................... 739 20.1.4 offset 06 - 07h: sts?device status register (sata?d31:f2) .................................................................................... 741 20.1.5 offset 09h: pi?programming interface (sata?d31:f2)............................. 742 20.1.6 offset 0ah: scc?sub class code (sata?d31:f2) .................................... 742 20.1.7 offset 0bh: bcc?base class code (sata?d31:f2) ................................... 743 20.1.8 offset 0dh: mlt?master latency timer (sata?d31:f2)............................ 743 20.1.9 offset 10h - 13h: pcmd_bar?primary command block base address register (sata?d31:f2) .................................................... 744 20.1.10offset 14h - 17h: pcnl_bar?primary control block base address register (sata?d31:f2)............................................................ 744 20.1.11offset 18h - 1bh: scmd_bar?secondary command block base address register (ide d31:f1) ....................................................... 745 20.1.12offset 14h - 17h: scnl_bar?secondary control block base address register (ide d31:f1) ....................................................... 745 20.1.13offset 20h - 23h: bar?legacy bus master base address register (sata?d31:f2)........................................................................ 746 20.1.14offset 2ch - 2dh: svid?subsystem vendor id (sata?d31:f2) .................................................................................... 746 20.1.15offset 2eh - 2fh: sid?subsystem id (sata?d31:f2)............................... 747 20.1.16offset 34h: cap?capabilities pointer register (sata?d31:f2) .................................................................................... 747 20.1.17offset 3ch: intr_ln?interrupt line register (sata?d31:f2) .................................................................................... 747 20.1.18offset 3dh: intr_pn?interrupt pin register (sata?d31:f2) .................................................................................... 748
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 29 contents?intel ? 6300ESB ich 20.1.19 offset 40 - 41h: ide_timp?primary ide timing register (sata?d31:f2).................................................................................... 748 20.1.20 ide_tims?secondary ide timing register (sata?d31:f2) ....................... 750 20.1.21 offset 44h: sidetim?slave ide timing register (sata?d31:f2).................................................................................... 750 20.1.22 offset 48h: sdma_cnt?synchronous dma control register (sata?d31:f2) 751 20.1.23 offset 4a - 4bh: sdma_tim?synchronous dma timing register (sata?d31:f2) 752 20.1.24 offset 54h: ide_config?ide i/o configuration register (sata?d31:f2) ... 754 20.1.25 offset 70 - 71h: pid?pci power management capability id (sata?d31:f2) 755 20.1.26 offset 72 - 73h: pc?pci power management capabilities (sata?d31:f2) ... 755 20.1.27 offset 74 - 75h: pmcs?pci power management control and status (sata? d31:f2)756 20.1.28 offset 80 - 81h: mid?message signaled interrupt identifiers (sata?d31:f2) .... 757 20.1.29 offset 82 - 83h: mc?message signaled interrupt message control (sata? d31:f2)757 20.1.30 offset 84 - 87h: ma?message signaled interrupt message address (sata? d31:f2)758 20.1.31 offset 88 - 89h: md?message signaled interrupt message data (sata?d31:f2) 759 20.1.32 offset 90h: map?address map (sata?d31:f2)........................................ 759 20.1.33 offset 92h: pcs?port status and control (sata?d31:f2) ......................... 760 20.1.34 offset a0h: sri?sata registers index (sata?d31:f2) ............................ 760 20.1.35 offset a4h - a7h: srd?sata registers data (sata?d31:f2).................................................................................... 761 20.1.36 sttt?sata tx termination test register a (sata?d31:f2).................................................................................... 762 20.1.37 stot ? sata tx output test register (sata?d31:f2) ............................. 762 20.1.38 offset index 54h - 57h: ser0?sata serror register port 0 (sata?d31:f2) 763 20.1.39 offset index 64h - 67h: ser1?sata serror register port 1 (sata?d31:f2) 763 20.1.40 offset e0h - e3h: bfcs?bist fis control/status register (sata?d31:f2) .. 763 20.1.41 offset e4h - e7h: bftd1?bist fis transmit data1 register (sata?d31:f2)765 20.1.42 offset e8h - ebh: bftd2?bist fis transmit data2 register (sata?d31:f2)766 20.2 bus master ide i/o registers (d31:f2) .............................................................. 766 20.2.1 bmic[p,s]?bus master ide command register (d31:f2) .......................... 767 20.2.2 bmis[p,s]?bus master ide status register (d31:f2) ............................... 768 20.2.3 bmid[p,s]?bus master ide descriptor table pointer register (d31:f2)....... 769 21 package information ............................................................................................. 771 21.1 ball location ................................................................................................... 771 22 electrical characteristics ....................................................................................... 789 22.1 absolute maximum ratings............................................................................... 789 22.2 functional operating range .............................................................................. 789 22.3 dc characteristics ........................................................................................... 790 22.4 ac characteristics ........................................................................................... 796 22.5 timing diagrams and test conditions................................................................. 813 22.5.1 pci-x ................................................................................................. 813 22.5.2 system clocks and general timing ......................................................... 815 22.5.3 ide and ultra ata timing ...................................................................... 817 22.5.4 usb.................................................................................................... 820 22.5.5 smbus ................................................................................................ 821 22.5.6 power and reset .................................................................................. 822 22.5.7 ac?97 and miscellaneous ....................................................................... 824 23 testability ............................................................................................................. 825
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 30 order number: 300641-004us 23.1 test mode description ...................................................................................... 825 23.2 tri-state mode ................................................................................................ 826 23.3 xor chain mode.............................................................................................. 826 23.3.1 xor chain testability algorithm example................................................. 826 index ..................................................................................................................... 835
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 31 contents?intel ? 6300ESB ich figures 1 workstation/pc model.................................................................................................5 2 low to mid-range communication appliance model (diskless) .......................................... 6 3 value server, ultra-dense server and low-end server blade ........................................... 7 4 conceptual system clock diagram ............................................................................. 54 5 power plane usage model .......................................................................................... 80 6 primary device status register error reporting logic.................................................... 93 7 secondary status register error reporting logic .......................................................... 94 8 nmi# generation logic ............................................................................................. 95 9 typical timing for lframe# .................................................................................... 101 10 abort mechanism ................................................................................................... 101 11 intel ? 6300ESB ich dma controller ......................................................................... 103 12 dma request assertion through ldrq# ................................................................... 107 13 port 60 read clearing irq1 and irq12 latch............................................................ 120 14 coprocessor error timing diagram ........................................................................... 142 15 latching processor i/f signals with stopclk#........................................................... 154 16 physical region descriptor table entry...................................................................... 182 17 sata power states................................................................................................. 190 18 transfer descriptor ................................................................................................ 197 19 example queue conditions ...................................................................................... 205 20 usb data encoding ................................................................................................ 208 21 usb legacy keyboard flow diagram......................................................................... 219 22 intel ? 6300ESB ich-usb port connections................................................................ 230 23 intel ? 6300ESB ich based ac?97 controller connection to companion codec(s) ............ 260 24 ac?97 2.2 controller-codec connection ..................................................................... 261 25 ac-link protocol .................................................................................................... 262 26 ac-link powerdown timing ..................................................................................... 270 27 sdin wake signaling.............................................................................................. 271 28 intel ? 6300ESB ich device diagram ........................................................................ 277 29 wdt block diagram ............................................................................................... 616 30 intel ? 6300ESB i/o controller hub appearance to software ........................................ 650 31 type ?1? to type ?0? translation ................................................................................ 651 32 siu block diagram ................................................................................................ 704 33 example uart data frame...................................................................................... 709 34 start frame timing with source sampled a low pulse on irq1 .................................... 725 35 stop frame timing with host using 17 siu_serirq sampling period............................ 726 36 ball diagram (top view - left side) .......................................................................... 771 37 ball diagram (top view - right side) ........................................................................ 772 38 mechanical drawing................................................................................................ 773 39 pci-x 3.3v clock ................................................................................................... 813 40 clock uncertainty (pxpclk[0:4]).............................................................................. 813 41 pci-x output timing .............................................................................................. 814 42 pci-x input timing ................................................................................................ 814 43 pci-x rst# timing for switching to pci-x mode pull-ups............................................. 815 44 clock timing ......................................................................................................... 815 45 valid delay from rising clock edge........................................................................... 816 46 setup and hold times............................................................................................. 816 47 float delay............................................................................................................ 816 48 pulse width ........................................................................................................... 816 49 output enable delay............................................................................................... 817 50 ide pio mode ........................................................................................................ 817 51 ide multiword dma ................................................................................................ 818 52 ultra ata mode (drive initiating a burst read)........................................................... 818 53 ultra ata mode (sustained burst) ............................................................................ 819
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 32 order number: 300641-004us 54 ultra ata mode (pausing a dma burst)...................................................................... 819 55 ultra ata mode (terminating a dma burst) ................................................................ 820 56 usb rise and fall times .......................................................................................... 820 57 usb jitter.............................................................................................................. 821 58 usb eop width ...................................................................................................... 821 59 smbus transaction ................................................................................................. 821 60 smbus timeout ...................................................................................................... 822 61 power sequencing and reset signal timings .............................................................. 822 62 g3 (mechanical off) to s0 timings ............................................................................ 823 63 s0 to s1 to s0 timing ............................................................................................. 823 64 s0 to s5 to s0 timings............................................................................................ 824 65 ac?97 data input and output timings ....................................................................... 824 66 test mode entry (xor chain example) ...................................................................... 826 67 example xor chain circuitry ................................................................................... 826
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 33 contents?intel ? 6300ESB ich tables 1 industry specifications.............................................................................................. 49 2intel ? 6300ESB ich clock domains............................................................................ 53 3 hub interface signals ............................................................................................... 55 4 firmware hub interface signals ................................................................................. 56 5 pci interface signals ................................................................................................ 57 6 pci-x interface signals ............................................................................................. 60 7 sata interface signals ............................................................................................. 64 8 ide interface signals................................................................................................ 64 9 lpc interface signals................................................................................................ 66 10 interrupt signals...................................................................................................... 66 11 usb interface signals ............................................................................................... 67 12 power management interface signals.......................................................................... 68 13 cpu interface signals ............................................................................................... 69 14 sm bus interface signals .......................................................................................... 71 15 system management interface signals........................................................................ 71 16 real time clock interface.......................................................................................... 71 17 other clocks ........................................................................................................... 72 18 miscellaneous signals ............................................................................................... 72 19 ac?97 link signals.................................................................................................... 73 20 universal asynchronous receive and transmit (uart0, 1)............................................. 73 21 general purpose i/o signals ...................................................................................... 75 22 power and ground signals......................................................................................... 76 23 functional strap definitions ....................................................................................... 77 24 revision and device id table..................................................................................... 78 25 intel ? 6300ESB i/o controller hub power planes ......................................................... 79 26 integrated pull-up and pull-down resistors ................................................................. 80 27 ide series termination resistors................................................................................ 81 28 power plane and states for output and i/o signal for desktop configurations .................. 83 29 power plane for input signals for desktop configurations .............................................. 90 30 type 0 configuration cycle device number translation ................................................. 96 31 lpc cycle types supported ....................................................................................... 98 32 start field bit definitions .......................................................................................... 98 33 cycle type bit definitions.......................................................................................... 99 34 transfer size bit definition ........................................................................................ 99 35 sync bit definition................................................................................................... 99 36 response to sync failures ....................................................................................... 100 37 fixed priority ......................................................................................................... 104 38 dma transfer size.................................................................................................. 105 39 address shifting in 16-bit i/o dma transfers ............................................................. 105 40 counter operating modes ........................................................................................ 111 41 interrupt controller core connections ....................................................................... 113 42 interrupt status registers ....................................................................................... 114 43 content of interrupt vector byte .............................................................................. 115 44 interrupt mapping in non-apic ................................................................................ 123 45 apic interrupt mapping, apic0 agent ....................................................................... 124 46 apic interrupt mapping, apic1 agent ....................................................................... 125 47 arbitration cycles................................................................................................... 126 48 apic message formats ........................................................................................... 126 49 eoi message ......................................................................................................... 127 50 short message....................................................................................................... 128 51 apic bus status cycle definition .............................................................................. 129 52 lowest priority message (without focus processor)..................................................... 130 53 remote read message............................................................................................ 131
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 34 order number: 300641-004us 54 interrupt message address format ........................................................................... 134 55 interrupt message data format ................................................................................ 135 56 stop frame explanation .......................................................................................... 137 57 data frame format................................................................................................. 137 58 configuration bits reset by rtcrst# assertion.......................................................... 140 59 init# going active ................................................................................................. 141 60 nmi sources .......................................................................................................... 143 61 dp signal differences .............................................................................................. 143 62 general power states for systems using intel ? 6300ESB ich ...................................... 146 63 state transition rules for intel ? 6300ESB i/o controller hub....................................... 147 64 system power plane ............................................................................................... 148 65 causes of sci ........................................................................................................ 149 66 causes of smi#...................................................................................................... 150 67 causes of tco smi#............................................................................................... 151 68 break events ......................................................................................................... 152 69 sleep types ........................................................................................................... 156 70 causes of wake events ........................................................................................... 156 71 transitions due to power failure............................................................................... 158 72 transitions due to power button............................................................................... 160 73 transitions due to ri# signal .................................................................................. 161 74 write only registers with read paths in alt access mode ............................................ 163 75 pic reserved bits return values............................................................................... 165 76 register write accesses in alt access mode............................................................... 165 77 intel ? 6300ESB ich clock inputs ............................................................................. 167 78 event transitions that cause messages...................................................................... 172 79 gpio implementation ............................................................................................. 176 80 ide legacy i/o ports: command block registers (cs1x# chip select)........................... 180 81 ide transaction timings (pci clocks) ........................................................................ 181 82 interrupt/active bit interaction definition .................................................................. 185 83 ultraata/33 control signal redefinitions ................................................................... 186 84 sata msi vs. pci irq actions .................................................................................. 192 85 legacy routing ...................................................................................................... 193 86 frame list pointer bit description ............................................................................. 196 87 td link pointer ...................................................................................................... 197 88 td control and status ............................................................................................. 198 89 td token .............................................................................................................. 200 90 td buffer pointer.................................................................................................... 201 91 queue head block .................................................................................................. 201 92 queue head link pointer ......................................................................................... 201 93 queue element link pointer ..................................................................................... 201 94 command register, status register and td status bit interaction................................. 204 95 queue advance criteria ........................................................................................... 206 96 usb schedule list traversal decision table ................................................................ 207 97 pid format ............................................................................................................ 209 98 pid types ............................................................................................................. 210 99 address field ......................................................................................................... 210 100 endpoint field ........................................................................................................ 211 101 token format ........................................................................................................ 212 102 sof packet ............................................................................................................ 212 103 data packet format ................................................................................................ 212 104 bits maintained in low power states ......................................................................... 216 105 usb legacy keyboard/mouse control register bit implementation ................................ 217 106 usb legacy keyboard state transitions..................................................................... 220 107 uhci vs. ehci ....................................................................................................... 221 108 ehc resets............................................................................................................ 223
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 35 contents?intel ? 6300ESB ich 109 read policies for periodic dma ................................................................................. 224 110 write policies for periodic dma ................................................................................. 225 111 read policies for asynchronous dma ......................................................................... 226 112 write policies for asynchronous dma ........................................................................ 227 113 effect of resets on port-routing logic....................................................................... 232 114 usb debug port behavior........................................................................................ 233 115 quick protocol ....................................................................................................... 239 116 send/receive byte protocol without pec ................................................................... 239 117 send/receive byte protocol with pec ........................................................................ 240 118 write byte/word protocol without pec ...................................................................... 240 119 write byte/word protocol with pec ........................................................................... 240 120 read byte/word protocol without pec ....................................................................... 242 121 read byte/word protocol with pec ........................................................................... 242 122 process call protocol without pec ............................................................................. 243 123 process call protocol with pec ................................................................................. 243 124 block read/write protocol without pec...................................................................... 245 125 block read/write protocol with pec .......................................................................... 245 126 i 2 c block read protocol .......................................................................................... 246 127 block write-block read process call protocol with/without pec .................................... 248 128 enable for smbalert# ........................................................................................... 250 129 enables for smbus slave write and smbus host events ............................................... 250 130 enables for the host notify command ....................................................................... 251 131 slave write cycle format ........................................................................................ 252 132 slave write registers ............................................................................................. 253 133 command types .................................................................................................... 253 134 read cycle format ................................................................................................. 254 135 data values for slave read registers........................................................................ 255 136 host notify format ................................................................................................. 257 137 features supported by intel ? 6300ESB ich .............................................................. 258 138 ac?97 signals ........................................................................................................ 262 139 input slot 1 bit definitions ...................................................................................... 267 140 output tag slot 0 .................................................................................................. 269 141 ac-link state during pxpcirst# .............................................................................. 273 142 pci devices and functions....................................................................................... 276 143 fixed i/o ranges decoded by intel ? 6300ESB i/o controller hub ................................ 278 144 variable i/o decode ranges .................................................................................... 281 145 memory decode ranges from cpu perspective ........................................................... 283 146 pci configuration registers (d30:f0) ....................................................................... 287 147 offset 00 - 01h: vid?vendor id register (hub-pci?d30:f0) ..................................... 288 148 offset 02 - 03h: did?device id register (hub-pci?d30:f0) ..................................... 288 149 offset 04 - 05h: cmd?command register (hub-pci?d30:f0) .................................... 289 150 offset 06 - 07h: pd_sts?primary device status register (hub-pci?d30:f0) ............... 290 151 offset 08h: rid?revision identification register (hub-pci?d30:f0) ........................... 291 152 offset 0ah: scc?sub-class code register (hub-pci?d30:f0) ................................... 291 153 offset 0bh: bcc?base-class code register (hub-pci?d30:f0) .................................. 291 154 offset 0dh: pmlt?primary master latency timer register (hub-pci?d30:f0) .............. 292 155 offset 0eh: headtyp?header type register (hub-pci?d30:f0) ................................. 292 156 offset 18h: pbus_num?primary bus number register (hub-pci?d30:f0) ................... 292 157 offset 19h: sbus_num?secondary bus number register (hub-pci?d30:f0) ............... 293 158 offset 1a: sub_bus_num?subordinate bus number register (hub-pci?d30:f0) ........ 293 159 offset 1bh: smlt?secondary master latency timer register (hub-pci?d30:f0) .......... 294 160 offset 1ch: iobase?i/o base register (hub-pci?d30:f0) ........................................ 294 161 offset 1dh: iolim?i/o limit register (hub-pci?d30:f0) .......................................... 295 162 offset 1e - 1fh: secsts?secondary status register (hub-pci?d30:f0) ..................... 295 163 offset 20 - 21h: membase?memory base register (hub-pci?d30:f0) ........................ 297
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 36 order number: 300641-004us 164 offset 22 - 23h: memlim?memory limit register (hub-pci?d30:f0) ........................... 297 165 offset 24h - 25h: pref_mem_base?prefetchable memory base register (hub-pci?d30:f0) 298 166 offset 26h-27h: pref_mem_mlt?prefetchable memory limit register (hub-pci?d30:f0) ... 299 167 offset 30 - 31h: iobase_hi?i/o base upper 16 bits register (hub-pci?d30:f0) ......... 299 168 offset 32 - 33h: iolim_hi?i/o limit upper 16 bits register (hub-pci?d30:f0) ........... 300 169 offset 3ch: int_line?interrupt line register (hub-pci?d30:f0) ............................... 300 170 offset 3e - 3fh: bridge_cnt?bridge control register (hub-pci?d30:f0) ................... 301 171 offset 40 - 43h: hi_cmd?hub interface command control register (hub-pci?d30:f0) . 304 172 offset 44 - 45h: device_hide?secondary pci device hiding register (hub-pci?d30:f0) .. 305 173 offset 50 - 51h: cnf?intel? 6300ESB ich configuration register (hub-pci?d30:f0) ... 306 174 offset 58 - 5bh: d30_pne ? perr#_nmi_enable register (hub-pci?d30:f0)............. 307 175 offset 70h: mtt?multi-transaction timer register (hub-pci?d30:f0) ......................... 308 176 offset 82h: pci_mast_sts?pci master status register (hub-pci?d30:f0) ................. 309 177 offset 90h: err_cmd?error command register (hub-pci?d30:f0) ............................ 309 178 offset 92h: err_sts?error status register (hub-pci?d30:f0) .................................. 310 179 offset f8h - fbh: manid? manufacturer?s id ............................................................. 310 180 pci configuration registers (d31:f0) ........................................................................ 311 181 offset 00 - 01h: vid?vendor id register (lpc i/f?d31:f0) ....................................... 312 182 offset 02 - 03h: did?device id register (lpc i/f?d31:f0) ........................................ 313 183 offset 04 - 05h: pcicmd?pci command register (lpc i/f?d31:f0) ........................... 313 184 offset 06 - 07h: pcista?pci device status (lpc i/f?d31:f0) .................................... 314 185 offset 08h: rid?revision id register (lpc i/f?d31:f0) ............................................ 315 186 offset 09h: pi?programming interface (lpc i/f?d31:f0)........................................... 315 187 offset 0ah: scc?sub-class code register (lpc i/f?d31:f0)...................................... 315 188 offset 0bh: bcc?base-class code register (lpc i/f?d31:f0)..................................... 316 189 offset 0eh: headtyp?header type register (lpc i/f?d31:f0) ................................... 316 190 offset 40 - 43h: pmbase?acpi base address (lpc i/f?d31:f0) ................................. 317 191 offset 44h: acpi_cntl?acpi control (lpc i/f?d31:f0) ............................................ 317 192 offset 4e - 4fh: bios_cntl (lpc i/f?d31:f0) .......................................................... 319 193 offset 54h: tco_cntl?tco control (lpc i/f?d31:f0) .............................................. 320 194 offset 58h - 5bh: gpio_base?gpio base address (lpc i/f?d31:f0) .......................... 321 195 offset 5ch: gpio_cntl?gpio control (lpc i/f?d31:f0) ........................................... 321 196 offset pirqa - 60h: pirq[n]_rout?pirq[a,b,c,d] routing control (lpc i/f?d31:f0) .. 322 197 offset 64h: serirq_cntl?serial irq control (lpc i/f?d31:f0) ................................. 323 198 offset pirqe - 68h: pirq[n]_rout?pirq[e,f,g,h] routing control (lpc i/f?d31:f0) ... 324 199 offset 88h: d31_err_cfg?device 31 error config register (lpc i/f?d31:f0).............. 325 200 offset 8ah: d31_err_sts?device 31 error status register (lpc i/f?d31:f0).............. 326 201 offset 90h - 91h: pci_dma_cfg?pci dma configuration (lpc i/f?d31:f0).................. 326 202 offset d0h - d3h: gen_cntl?general control register (lpc i/f?d31:f0).................... 327 203 offset d4h: gen_sta?general status (lpc i/f?d31:f0)............................................ 329 204 offset d5h: back_cntl?backed up control (lpc i/f?d31:f0) ................................... 330 205 offset d8h: rtc_conf?rtc configuration register (lpc i/f?d31:f0) ......................... 331 206 offset e0h: com_dec?lpc i/f communication port decode ranges (lpc i/f?d31:f0) .. 332 207 offset e1h: fdd/lpt_dec?lpc i/f fdd and lpt decode ranges (lpc i/f?d31:f0) ....... 333 208 offset e2h: snd_dec?lpc i/f sound decode ranges (lpc i/f?d31:f0) ...................... 334 209 offset e3h: fwh_dec_en1?fwh decode enable 1 register (lpc i/f?d31:f0).............. 335 210 offset e4h - e5h: gen1_dec?lpc i/f generic decode range 1 (lpc i/f?d31:f0) ......... 336 211 offset e6h - e7h: lpc_en?lpc i/f enables (lpc i/f?d31:f0) ..................................... 337 212 offset e8h: fwh_sel1?fwh select 1 register (lpc i/f?d31:f0) ................................ 339 213 offset ech - edh: gen2_dec?lpc i/f generic decode range 2 (lpc i/f?d31:f0) ........ 340 214 offset eeh - efh: fwh_sel2?fwh select 2 register (lpc i/f?d31:f0)........................ 341 215 offset f0h: fwh_dec_en2?fwh decode enable 2 register (lpc i/f?d31:f0) .............. 342
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 37 contents?intel ? 6300ESB ich 216 offset f2h: func_dis?function disable register (lpc i/f?d31:f0) ............................ 343 217 offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0) ......................... 345 218 offset f8h: manufacturer?s id .................................................................................. 345 219 dmabase_ca?dma base and current address registers ............................................ 346 220 dmabase_ca?dma base and current address registers ............................................ 348 221 dmabase_cc?dma base and current count registers ............................................... 349 222 dmabase_cc?dma base and current count registers ............................................... 350 223 dmacmd?dma command register .......................................................................... 350 224 dmasta?dma status register ................................................................................ 351 225 dma_wrsmsk?dma write single mask register ....................................................... 352 226 dmach_mode?dma channel mode register ............................................................. 352 227 dma clear byte pointer register .............................................................................. 353 228 dma master clear register ...................................................................................... 354 229 dma_clmsk?dma clear mask register .................................................................... 354 230 dma_wrmsk?dma write all mask register .............................................................. 355 231 timer i/o registers ................................................................................................ 355 232 tcw ?timer control word register.......................................................................... 356 233 rdbk_cmd?read back command ........................................................................... 357 234 ltch_cmd?counter latch command....................................................................... 358 235 sbyte_fmt?interval timer status byte format register ............................................ 359 236 counter access ports register.................................................................................. 360 237 pic registers......................................................................................................... 360 238 icw1?initialization command word 1 register.......................................................... 361 239 icw2?initialization command word 2 register.......................................................... 362 240 icw3?master controller initialization command word 3 register................................. 363 241 icw3?slave controller initialization command word 3 register .................................. 363 242 icw4?initialization command word 4 register.......................................................... 364 243 ocw1?operational control word 1 (interrupt mask) register...................................... 364 244 ocw2?operational control word 2 register.............................................................. 365 245 ocw3?operational control word 3 register.............................................................. 366 246 elcr1?master controller edge/level triggered register ............................................. 367 247 elcr2?slave controller edge/level triggered register............................................... 367 248 apic direct registers.............................................................................................. 368 249 apic indirect registers ........................................................................................... 369 250 ind?index register............................................................................................... 369 251 dat?data register ................................................................................................ 370 252 offset fec0_0020h: irqpa?irq pin assertion register .............................................. 370 253 offset fec0 - eoir: eoi register ............................................................................. 371 254 offset 00h: id?identification register ...................................................................... 371 255 offset 01h: ver?version register............................................................................ 372 256 offset 02h: arbid?arbitration id register ............................................................... 372 257 offset 02h: arbid?arbitration id register ............................................................... 373 258 offset 10h - 11h (vector 0) through 3e - 3fh (vector 23): redirection table.................. 373 259 delivery mode encoding .......................................................................................... 375 260 rtc i/o registers .................................................................................................. 376 261 rtc (standard) ram bank....................................................................................... 376 262 rtc_regd?register d (flag register) ..................................................................... 377 263 rtc_regb?register b (general configuration) ......................................................... 378 264 rtc_regc?register c (flag register)...................................................................... 380 265 rtc_regd?register d (flag register) ..................................................................... 380 266 nmi_sc?nmi status and control register................................................................. 381 267 nmi_en?nmi enable (and real time clock index) ..................................................... 382 268 port92?fast a20 and init register ......................................................................... 382 269 coproc_err?coprocessor error register ................................................................ 383 270 rst_cnt?reset control register ............................................................................ 383
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 38 order number: 300641-004us 271 power management pci configuration registers (d31:f0) ............................................ 384 272 offset a0h: gen_pmcon_1?general pm configuration 1 register (pm?d31:f0) ............ 385 273 offset a2h: gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) ............ 386 274 offset a4h: gen_pmcon_3?general pm configuration 3 register (pm?d31:f0) ............ 387 275 offset ach: rst_cnt2?reset control 2 register (pm?d31:f0) ................................... 388 276 offset b8h - bbh: gpi_rout?gpi routing control register (pm?d31:f0)..................... 389 277 offset c0h: mon_fwd_en?io monitor forward enable register (pm?d31:f0) .............. 390 278 offset c4h, c6h, c8h, cah: mon[n]_trp_rng?i/o monitor [4:7] trap range register for devices 4-7 (pm?d31:f0)...................................................................... 391 279 offset cch: mon_trp_msk?i/o monitor trap range mask register for devices 4-7 (pm? d31:f0)391 280 apm register map................................................................................................... 392 281 apm_cnt?advanced power management control port register .................................... 392 282 apm_sts?advanced power management status port register ..................................... 392 283 acpi and legacy i/o register map............................................................................ 393 284 pm1_sts?power management 1 status register........................................................ 394 285 pm1_en?power management 1 enable register ......................................................... 396 286 pm1_cnt?power management 1 control................................................................... 397 287 pm1_tmr?power management 1 timer register ........................................................ 398 288 proc_cnt?processor control register ..................................................................... 398 289 lv2?level 2 register ............................................................................................. 400 290 gpe0_sts?general purpose event 0 status register .................................................. 401 291 gpe0_en?general purpose event 0 enables register .................................................. 404 292 smi_en?smi control and enable register ................................................................. 405 293 smi_sts?smi status register................................................................................. 408 294 alt_gp_smi_en?alternate gpi smi enable register .................................................. 410 295 alt_gp_smi_sts?alternate gpi smi status register................................................. 411 296 mon_smi?device monitor smi status and enable register .......................................... 411 297 devact_sts?device activity status register............................................................ 412 298 devtrap_en? device trap enable register .............................................................. 414 299 bus_addr_track? bus address tracker ................................................................. 415 300 bus_cyc_track? bus cycle tracker ....................................................................... 416 301 tco i/o register map ............................................................................................. 416 302 tco1_rld?tco timer reload and current value ....................................................... 417 303 tco1_tmr?tco timer initial value ......................................................................... 417 304 tco1_dat_in?tco data in register ....................................................................... 418 305 tco1_dat_out?tco data out register................................................................... 418 306 tco1_sts?tco1 status register ............................................................................ 419 307 tco2_sts?tco2 status register ............................................................................ 421 308 tco1_cnt?tco1 control register ........................................................................... 422 309 tco2_cnt?tco2 control register ........................................................................... 423 310 tco_message1 and tco_message2 registers ......................................................... 423 311 offset tcobase + oeh: tco_wdstatus?tco2 control register ................................ 424 312 offset tcobase + 10h: sw_irq_gen?software irq generation register..................... 424 313 registers to control gpio ........................................................................................ 425 314 offset gpiobase + 00h: gpio_use_sel?gpio use select register ............................. 426 315 offset gpiobase + 04h: gp_io_sel?gpio input/output select register...................... 426 316 offset gpiobase + 0ch: gp_lvl?gpio level for input or output register.................... 427 317 offset gpiobase + 18h: gpo_blink?gpo blink enable register ................................. 429 318 offset gpiobase + 2ch: gpi_inv?gpio signal invert register ................................... 430 319 offset gpiobase + 30h:gpio_use_sel2?gpio use select 2 register.......................... 431 320 offset gpiobase + 34h: gp_io_sel2?gpio input/output select 2 register ................. 432 321 offset gpiobase + 38h: gp_lvl2?gpio level for input or output 2 register ............... 432 322 pci configuration map (ide-d31:f1)......................................................................... 435 323 offset 00 - 01h: vid?vendor id register (lpc i/f?d31:f1) ....................................... 436
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 39 contents?intel ? 6300ESB ich 324 offset 02 - 03h: did?device id register (lpc i/f?d31:f1) ....................................... 436 325 offset 04h - 05h: cmd?command register (ide?d31:f1) ......................................... 437 326 offset 06 - 07h: sts?device status register (ide?d31:f1)....................................... 438 327 offset 08h: rid?revision id register (ide?d31:f1) ................................................. 439 328 offset 09h: pi?programming interface (ide?d31:f1) ............................................... 439 329 offset 0ah: scc?sub class code (ide?d31:f1) ....................................................... 440 330 offset 0bh: bcc?base class code (ide?d31:f1)...................................................... 441 331 offset 0dh: mlt?master latency timer (ide?d31:f1) .............................................. 441 332 offset 10h - 13h: pcmd_bar?primary command block base address register (ide?d31:f1) 441 333 offset 14h - 17h: pcnl_bar?primary control block base address register (ide?d31:f1) ... 442 334 offset 18h - 1bh: scmd_bar?secondary command block base address register (ide d31:f1)442 335 offset 1ch - 1fh: scnl_bar?secondary control block base address register (ide d31:f1) . 443 336 offset 20h - 23h: bm_base?bus master base address register (ide?d31:f1) ............. 443 337 offset 24h - 27h: cpba ? ide command posting base address .................................... 444 338 offset 2ch - 2dh: ide_svid?subsystem vendor id (ide?d31:f1) ............................. 445 339 offset 2eh - 2fh: ide_sid?subsystem id (ide?d31:f1)........................................... 446 340 offset 3ch: intr_ln?interrupt line register (ide?d31:f1) ...................................... 446 341 offset 3dh: intr_pn?interrupt pin register (ide?d31:f1)........................................ 447 342 ide_tim?ide timing register (ide?d31:f1) ........................................................... 448 343 offset 44h: slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) ............... 451 344 offset 48h: sdma_cnt?synchronous dma control register (ide?d31:f1) .................. 452 345 offset 4a - 4bh: sdma_tim?synchronous dma timing register (ide?d31:f1) ............ 453 346 ide_config?ide i/o configuration register (ide?d31:f1) ....................................... 455 347 bus master ide i/o registers .................................................................................. 455 348 bmic[p,s]?bus master ide command register ......................................................... 456 349 bmis[p,s]?bus master ide status register............................................................... 457 350 bmid[p,s]?bus master ide descriptor table pointer register ...................................... 459 351 pci configuration map (usb?d29:f0/f1) ................................................................. 461 352 offset 00 - 01h: vid?vendor identification register (usb?d29:f0/f1) ........................ 462 353 offset 02 - 03h: did?device identification register (usb?d29:f0/f1) ........................ 462 354 offset 04 - 05h: cmd?command register (usb?d29:f0/f1)...................................... 463 355 offset 06 - 07h: sta?device status register (usb?d29:f0/f1) ................................. 464 356 offset 08h: rid?revision identification register (usb?d29:f0/f1)............................. 464 357 offset 09h: pi?programming interface (usb?d29:f0/f1) .......................................... 465 358 offset 0ah: scc?sub class code register (usb?d29:f0/f1) ..................................... 465 359 offset 0bh: bcc?base class code register (usb?d29:f0/f1) .................................... 465 360 offset 0dh: mlt?master latency timer .................................................................... 466 361 offset 0eh: htype?header type register (usb?d29:f0/f1) ...................................... 466 362 offset 20 - 23h: base?base address register (usb?d29:f0/f1) ................................ 467 363 offset 2ch - 2dh: svid?subsystem vendor id (usb?d29:f0/f1).............................. 467 364 offset 2eh-2fh: sid?subsystem id (usb?d29:f0/f1) .............................................. 468 365 offset 3ch: intr_ln?interrupt line register (usb?d29:f0/f1) ................................. 468 366 offset 3dh: intr_pn?interrupt pin register (usb?d29:f0/f1) .................................. 469 367 offset 60h: usb_relnum?usb release number register (usb?d29:f0/f1) ................ 469 368 offset c0 - c1h: usb_legkey?usb legacy keyboard/ mouse control register (usb?d29:f0/ f1)470 369 offset c4h: usb_res?usb resume enable register (usb?d29:f0/f1) ....................... 472 370 usb i/o registers .................................................................................................. 473 371 offset 00 - 01h: usbcmd?usb command register.................................................... 474 372 run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation ................. 477 373 offset 02 - 03h: usbsta?usb status register .......................................................... 478
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 40 order number: 300641-004us 374 offset base + (04 - 05h): usbintr?interrupt enable register..................................... 479 375 offset base + (06 - 07h): frnum?frame number register ......................................... 481 376 offset base + (08 - 0bh): frbaseadd?frame list base address ................................. 481 377 offset base + och: sofmod?start of frame modify register ...................................... 482 378 portsc[0,1]?port status and control register.......................................................... 483 379 offset 04 - 05h: command register.......................................................................... 486 380 offset 06 - 07h: device status ................................................................................. 487 381 offset 08h: rid?revision id register....................................................................... 489 382 offset 09h: programming interface ........................................................................... 489 383 offset 0ah: sub class code ..................................................................................... 489 384 offset 0bh: base class code .................................................................................... 490 385 offset 0dh: master latency timer............................................................................. 490 386 offset 10 - 13h: memory base address...................................................................... 490 387 offset 2c - 2dh: usb ehci subsystem vendor id ....................................................... 491 388 offset 2e - 2fh: sid?usb ehci subsystem id .......................................................... 491 389 offset 34h: capabilities pointer ................................................................................ 491 390 offset 3ch: interrupt line........................................................................................ 492 391 offset 3dh: interrupt pin ......................................................................................... 492 392 offset 50h: pci power management capability id ....................................................... 492 393 offset 51h: next item pointer #1 ............................................................................. 493 394 offset 52 - 53h: power management capabilities ........................................................ 493 395 offset 54 - 55h: power management control/status .................................................... 494 396 offset 58h: debug port capability id......................................................................... 495 397 offset 59h: next item pointer #2 ............................................................................. 496 398 offset 5ah - 5bh: debug port base offset .................................................................. 496 399 offset 60h: serial bus release number ..................................................................... 496 400 offset 61h: frame length adjustment ....................................................................... 497 401 offset 62 - 63h: port wake capability ....................................................................... 498 402 offset 64-65h: cuo - classic usb override ................................................................ 499 403 offset 68 - 6bh: usb ehci legacy support extended capability ................................... 499 404 offset 6c - 6fh: usb ehci legacy support extended control/status ............................. 500 405 offset 70 - 73h: intel specific usb ehci smi ............................................................. 501 406 offset 80h: access control....................................................................................... 503 407 hs_ ref_v_usb hs reference voltage register .......................................................... 503 408 offset 00h: caplength?capability registers length.................................................. 504 409 offset 02 - 03h: hciversion?host controller interface version number ...................... 505 410 offset 04 - 07h: hcsparams?host controller structural parameters ............................ 505 411 offset 08 - 0bh: hccparams?host controller capability parameters............................ 507 412 offset caplength + 00 - 03h: usb ehci cmd?usb ehci command register............... 509 413 offset caplength + 04 - 07h: usb ehci sts?usb ehci status ................................. 512 414 offset caplength + 08 - 0bh: usb ehci intr?usb ehci interrupt enable.................. 514 415 offset caplength + 0c - 0fh: frindex?frame index............................................... 515 416 offset caplength + 10 - 13h: ctrldssegment?control data structure segment register 516 417 offset caplength + 14 - 17h: periodiclistbase?periodic frame list base address ... 516 418 offset caplength + 18 - 1bh: asynclistaddr?current asynchronous list address .... 517 419 offset caplength + 40 - 43h: configflag?configure flag register .......................... 517 420 portsc- port n status and control........................................................................... 518 421 offset 00h: control/status register .......................................................................... 522 422 offset 04h: usb pids register ................................................................................. 525 423 offset 08h: data buffer bytes 7:0............................................................................. 525 424 offset 10h: config register...................................................................................... 526 425 offset 00 - 01h: vid?vendor identification register (smbus?d31:f3)......................... 527 426 offset 02 - 03h: did?device identification register (smbus?d31:f3) ......................... 528 427 offset 04 - 05h: cmd?command register (smbus?d31:f3) ...................................... 528
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 41 contents?intel ? 6300ESB ich 428 offset 06 - 07h: sta?device status register (smbus?d31:f3).................................. 529 429 offset 08h: rid?revision id register (smbus?d31:f3) ............................................ 529 430 offset 09h: pi?programming interface (smbus?d31:f3) .......................................... 530 431 offset 0ah: scc?sub class code register (smbus?d31:f3)...................................... 530 432 offset 0bh: bcc?base class code register (smbus?d31:f3) .................................... 530 433 offset 20 - 23h: smb_base?smbus base address register (smbus?d31:f3).............. 531 434 offset 2ch - 2dh: svid?subsystem vendor id (smbus?d31:f2/f4).......................... 531 435 offset 2eh - 2fh: sid?subsystem id (smbus?d31:f2/f4) ........................................ 532 436 offset 3ch: intr_ln?interrupt line register (smbus?d31:f3).................................. 532 437 offset 3dh: intr_pn?interrupt pin register (smbus?d31:f3)................................... 532 438 offset 40h: hostc?host configuration register (smbus?d31:f3) ............................. 533 439 smb i/o registers.................................................................................................. 533 440 offset 00h: hst_sts?host status register .............................................................. 535 441 offset 02h: hst_cnt?host control register ............................................................. 537 442 offset 03h: hst_cmd?host command register ........................................................ 539 443 offset 04h: xmit_slva?transmit slave address register........................................... 539 444 offset 05h: hst_d0?data 0 register ....................................................................... 540 445 offset 06h: hst_d1?data 1 register ....................................................................... 540 446 offset 07h: host_block_db?host block data byte register ....................................... 541 447 offset 08h: pec?packet error check register............................................................ 542 448 offset 09h: rcv_slva?receive slave address register.............................................. 542 449 offset 0ah: slv_data?receive slave data register .................................................. 543 450 offset 0ch: aux_sts?auxiliary status register ........................................................ 543 451 offset 0dh: aux_ctl?auxiliary control register ....................................................... 544 452 offset 0eh: smlink_pin_ctl?smlink pin control register ......................................... 544 453 offset 0fh: smbus_pin_ctl?smbus pin control register .......................................... 545 454 offset 10h: slv_sts?slave status register ............................................................. 546 455 offset 11h: slv_cmd?slave command register ....................................................... 546 456 offset 14h: notify_daddr?notify device address ................................................... 547 457 offset 16h: notify_dlow?notify data low byte register ......................................... 548 458 offset 17h: notify_dhigh?notify data high byte register........................................ 548 459 pci configuration map (audio?d31:f5) .................................................................... 549 460 offset 00 - 01h: vid?vendor identification register (audio?d31:f5) .......................... 551 461 offset 02 - 03h: did?device identification register (audio?d31:f5)........................... 551 462 offset 04 - 05h: pcicmd?pci command register (audio?d31:f5).............................. 552 463 offset 06 - 07h: pcists?pci device status register (audio?d31:f5).......................... 553 464 offset 08h: rid?revision identification register (audio?d31:f5) ............................... 554 465 offset 09h: pi?programming interface register (audio?d31:f5) ................................ 554 466 offset 0ah: scc?sub class code register (audio?d31:f5) ........................................ 554 467 offset 0bh: bcc?base class code register (audio?d31:f5)....................................... 555 468 offset 0eh: hedt?header type register (audio?d31:f5) .......................................... 555 469 offset 10 - 13h: nambar?native audio mixer base address register (audio?d31:f5) ... 556 470 offset 14 - 17h: nabmbar?native audio bus mastering base address register (audio? d31:f5)557 471 offset 18 - 1bh: mmbar?mixer base address register (audio?d31:f5) ....................... 557 472 offset 1c - 1fh: mbbar?bus master base address register (audio?d31:f5)................ 558 473 offset 2d - 2ch: svid?subsystem vendor id register (audio?d31:f5)....................... 559 474 offset 2e - 2fh: sid?subsystem id register (audio?d31:f5) .................................... 559 475 offset 34h: cap_ptr?capabilities pointer (audio?d31:f5)......................................... 560 476 offset 3ch: intr_ln?interrupt line register (audio?d31:f5).................................... 560 477 offset 3dh: intr_pn?interrupt pin register (audio?d31:f5) ..................................... 561 478 offset 40h: pcid?programmable codec id register (audio?d31:f5)........................... 561 479 offset 41h: cfg?configuration register (audio?d31:f5) ........................................... 562 480 offset 50h: pid?pci power management capability id register (audio?d31:f5)........... 562 481 offset 52h: pc?power management capabilities register (audio?d31:f5).................... 563
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 42 order number: 300641-004us 482 offset 54h: pcs?power management control and status register (audio?d31:f5) ........ 563 483 intel ? 6300ESB i/o controller hub audio mixer register configuration .......................... 565 484 native audio bus master control registers ................................................................. 566 485 x_bdbar?buffer descriptor base address register .................................................... 568 486 x_civ?current index value register ........................................................................ 569 487 x_lvi?last valid index register .............................................................................. 569 488 x_sr?status register ............................................................................................ 570 489 x_picb?position in current buffer register ............................................................... 571 490 x_piv?prefetched index value register .................................................................... 571 491 x_cr?control register ........................................................................................... 572 492 glob_cnt?global control register.......................................................................... 573 493 glob_sta?global status register ........................................................................... 575 494 cas?codec access semaphore register ................................................................... 578 495 sdm?sdata_in map register ................................................................................. 578 496 pci configuration map (modem?d31:f6) .................................................................. 581 497 offset 00 - 01h: vid?vendor identification register (modem?d31:f6)......................... 582 498 offset 02 - 03h: did?device identification register (modem?d31:f6) ......................... 582 499 offset 04 - 05h: pcicmd?pci command register (modem?d31:f6) ............................ 583 500 offset 06 - 07h: pcista?device status register (modem?d31:f6) ............................. 584 501 offset 08h: rid?revision identification register (modem?d31:f6).............................. 585 502 offset 09h: pi?programming interface register (modem?d31:f6)............................... 585 503 offset 0ah: scc?sub class code register (modem?d31:f6) ...................................... 585 504 offset 0bh: bcc?base class code register (modem?d31:f6) ..................................... 586 505 offset 0eh: hedt?header type register (modem?d31:f6) ........................................ 586 506 offset 10 - 13h: mmbar?modem mixer base address register (modem?d31:f6) .......... 587 507 offset 14 - 17h: mbar?modem base address register (modem?d31:f6) ..................... 587 508 offset 2c - 2dh: svid?subsystem vendor id (modem?d31:f6) ................................. 588 509 offset 2e - 2fh: sid?subsystem id (modem?d31:f6)............................................... 589 510 offset 34h: cap_ptr?capabilities pointer (modem?d31:f6)....................................... 589 511 offset 3ch: intr_ln?interrupt line register (modem?d31:f6) .................................. 589 512 offset 3dh: int_pin?interrupt pin (modem?d31:f6) ................................................ 590 513 offset 50h: pid?pci power management capability id register (modem?d31:f6)......... 590 514 offset 52h: pc?power management capabilities register (modem?d31:f6) .................. 591 515 offset 54h: pcs?power management control and status register (modem?d31:f6) ...... 591 516 intel ? 6300ESB i/o controller hub modem mixer register configuration........................ 593 517 modem registers.................................................................................................... 594 518 x_bdbar?buffer descriptor list base address register............................................... 595 519 x_civ?current index value register ........................................................................ 595 520 x_lvi?last valid index register .............................................................................. 596 521 x_sr?status register ............................................................................................ 596 522 x_picb?position in current buffer register ............................................................... 597 523 x_piv?prefetch index value register........................................................................ 599 524 x_cr?control register ........................................................................................... 599 525 glob_cnt?global control register.......................................................................... 600 526 glob_sta?global status register ........................................................................... 602 527 cas?codec access semaphore register ................................................................... 604 528 memory-mapped registers....................................................................................... 605 529 offset 000-007h: general capabilities and id register ................................................ 606 530 offset 010-017h: general config register.................................................................. 607 531 offset 020-027h: general interrupt status register .................................................... 608 532 offset 0f0 - 0f7h: main counter value....................................................................... 609 533 timer n config and capabilities ................................................................................ 610 534 timer n comparator value ....................................................................................... 613 535 wdt interface........................................................................................................ 617 536 configuration registers ........................................................................................... 617
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 43 contents?intel ? 6300ESB ich 537 memory mapped registers....................................................................................... 618 538 offset 00h: vid?vendor identification register ......................................................... 618 539 offset 02h: did?device identification register.......................................................... 619 540 offset 04 - 05h: com?command register ................................................................ 619 541 offset 06h - 07h: ds?device status register ............................................................ 620 542 offset 08h: rid?revision identification register........................................................ 621 543 offset 09h: pi?programming interface register ........................................................ 622 544 offset 0ah: scc?sub class code register ................................................................ 622 545 offset 0bh: bcc?base code class register ............................................................... 622 546 offset 0eh: hedt?header type register .................................................................. 623 547 offset 10h: bar?base address register ................................................................... 623 548 offset 2dh - 2ch: svid?subsystem vendor id ......................................................... 624 549 offset 2eh - 2fh: sid?subsystem id ....................................................................... 624 550 offset 60 - 61h: wdt configuration register ............................................................. 625 551 offset 68h: wdt lock register ................................................................................ 626 552 offset f8 - fbh: manufacturer?s id ........................................................................... 627 553 offset base + 00h: preload value 1 register.............................................................. 627 554 offset base + 04h: preload value 2 register.............................................................. 628 555 offset base + 08h: general interrupt status register ................................................. 628 556 offset base + 0ch: reload register .......................................................................... 629 557 apic1 configuration map (d29:f5) ........................................................................... 631 558 offset 00 - 03h: vid_did?vendor/id register (apic1?d29:f5) ................................. 632 559 offset 04 - 05h: apic1cmd?apic1 command register (apic1?d29:f5) ..................... 632 560 offset 06 - 07h: apic1sta?apic1 device status (apic1?d29:f5) .............................. 633 561 offset 08h: rid?revision id register (apic1?d29:f5).............................................. 634 562 offset 09 - 0bh: cc?class code register (apic1?d29:f5)......................................... 634 563 offset 0c - 0fh: headtyp?header type register (apic1?d29:f5).............................. 635 564 offset 2c - 2fh: ss?apic1 subsystem identifiers (apic1?d29:f5) ............................. 635 565 offset 34h: cap_ptr?apic1 capabilities pointer (apic1?d29:f5)............................... 636 566 offset 3ch: iline?interrupt line (apic1?d29:f5) .................................................... 636 567 offset 3dh: ipin?interrupt pin (apic1?d29:f5) ....................................................... 636 568 offset 40 - 41h: abar?apic1 alternate base address register (apic1?d29:f5) ........... 637 569 offset 44 - 47h: mbar?apic1 memory base register (apic1?d29:f5) ........................ 638 570 offset 50 - 51h: xid?pci-x identifiers register (apic1?d29:f5) ................................ 639 571 offset 52h: xsr?pci-x status register (apic1?d29:f5) ........................................... 639 572 apic1 direct registers............................................................................................ 640 573 apic indirect registers ........................................................................................... 640 574 ind?index register............................................................................................... 641 575 dat?data register ................................................................................................ 641 576 irqpa?irq pin assertion register ........................................................................... 642 577 eoir?eoi register ................................................................................................ 642 578 offset 00h: id?identification register ...................................................................... 643 579 offset 01h: ver?version register............................................................................ 643 580 offset 03h: boot_config?boot configuration register ............................................. 644 581 redirection table ................................................................................................... 644 582 configuration addressing ........................................................................................ 650 583 comparison of rules vs. a pci ? pci bridge ............................................................... 652 584 configuration space register summary..................................................................... 653 585 offset 00: id?identifiers ........................................................................................ 654 586 offset 04: cmd?command ..................................................................................... 655 587 offset 06: psts?primary status.............................................................................. 657 588 offset 08: rid?revision id .................................................................................... 658 589 offset 09: cc?class code ...................................................................................... 659 590 offset 0c: cls?cache line size .............................................................................. 659 591 offset 0d: plt?primary latency timer ..................................................................... 660
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 44 order number: 300641-004us 592 offset 0e: htype?header type ............................................................................... 660 593 offset 18: bnum?bus numbers ............................................................................... 661 594 offset 1b: slt?secondary latency timer.................................................................. 661 595 offset 1c: iobl?i/o base and limit ......................................................................... 662 596 offset 1e: ssts?secondary status .......................................................................... 663 597 offset 20: mbl?memory base and limit.................................................................... 664 598 offset 24: pmbl?prefetchable memory base and limit ................................................ 665 599 offset 28: pmbu32?prefetchable memory base upper 32 bits ...................................... 665 600 offset 2c: pmlu32?prefetchable memory limit upper 32 bits ...................................... 666 601 offset 30: ioblu16?i/o base and limit upper 16 bits ................................................ 666 602 offset 34: capp?capabilities list pointer .................................................................. 667 603 offset 3c: intr?interrupt information ..................................................................... 667 604 offset 3e: bctrl?bridge control ............................................................................. 668 605 offset 40: cnf?intel? 6300ESB i/o controller hub configuration................................ 671 606 offset 42: mtt?multi-transaction timer ................................................................... 673 607 offset 44: strp?pci strap status............................................................................ 674 608 offset 50: px_capid?pci-x capabilities identifier...................................................... 674 609 offset 51: px_nxtp?next item pointer..................................................................... 674 610 offset 52: px_ssts?pci-x secondary status ............................................................ 675 611 offset 54: px_bsts - pci-x bridge status ................................................................. 676 612 offset 58: px_ustc - pci-x upstream split transaction control ................................... 678 613 offset 5c: px_dstc - pci-x downstream split transaction control ............................... 679 614 offset e0: acnf ? additional intel? 6300ESB ich configuration................................... 680 615 offset e4: pcr - pci compensation register .............................................................. 681 616 offset f0: hccr - hub interface command/control register ........................................ 682 617 offset f8h: pc33 - prefetch control ? 33 mhz ............................................................ 683 618 offset fah: pc66 - prefetch control ? 66 mhz ............................................................ 683 619 intel ? 6300ESB i/o controller hub pci transactions ................................................... 684 620 pci-x interface command encoding.......................................................................... 691 621 intel ? 6300ESB ich implementation of requester attribute fields ................................ 692 622 devsel# timing .................................................................................................... 692 623 intel ? 6300ESB ich implementation completer attribute fields ................................... 693 624 split completion messages....................................................................................... 693 625 immediate terminations of completion required cycles to pci/pci-x ............................ 695 626 immediate terminations of posted write cycles to pci/pci-x ....................................... 696 627 split terminations of completion required cycles to pci-x........................................... 696 628 hub interface response to pci-x split completion terminations of completion required cycles 697 629 terminations of completion required cycles to hub interface....................................... 698 630 universal asynchronous receive and transmit (uart0, uart1).................................... 704 631 address map .......................................................................................................... 706 632 supported lpc cycle types...................................................................................... 706 633 i/o sync bits description......................................................................................... 707 634 uart clock divider support ..................................................................................... 708 635 baud rate examples ............................................................................................... 708 636 siu signal reset states........................................................................................... 710 637 internal register descriptions .................................................................................. 710 638 receive buffer register (rbr) .................................................................................. 711 639 transmit holding register (thr) .............................................................................. 711 640 interrupt enable register (ier) ................................................................................ 712 641 interrupt conditions................................................................................................ 713 642 interrupt identification register (iir) ........................................................................ 713 643 interrupt identification register decode .................................................................... 714 644 fifo control register (fcr) ..................................................................................... 714 645 line control register (lcr)...................................................................................... 716
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 45 contents?intel ? 6300ESB ich 646 line status register (lsr) ...................................................................................... 718 647 modem control register (mcr) ................................................................................ 720 648 modem status register (msr) ................................................................................. 721 649 scratch pad register (scr) ..................................................................................... 722 650 divisor latch register low (dll).............................................................................. 722 651 divisor latch register high (dlh) ............................................................................ 723 652 scratch pad register p60 (scr60)............................................................................ 725 653 scratch pad register p64 (scr64)............................................................................ 725 654 siu_serirq sampling periods................................................................................. 727 655 configuration registers summary ............................................................................ 730 656 global control registers.......................................................................................... 731 657 logical device 4 (serial port 0) ................................................................................ 732 658 logical device 5 (serial port 1) ................................................................................ 734 659 logical device 7 (port emulation) ............................................................................. 735 660 pci configuration map (sata?d31:f2) ..................................................................... 737 661 offset 00 - 01h: vid?vendor id register (sata?d31:f2).......................................... 738 662 offset 02 - 03h: did?device id register (sata?d31:f2) .......................................... 739 663 offset 04h - 05h: cmd?command register (sata?d31:f2)........................................ 739 664 offset 06 - 07h: sts?device status register (sata?d31:f2) ..................................... 741 665 offset 09h: pi?programming interface (sata?d31:f2) .............................................. 742 666 offset 0ah: scc?sub class code (sata?d31:f2)...................................................... 742 667 offset 0bh: bcc?base class code (sata?d31:f2) .................................................... 743 668 offset 0dh: mlt?master latency timer (sata?d31:f2) ............................................. 743 669 offset 10h - 13h: pcmd_bar?primary command block base address register (sata?d31:f2) 744 670 offset 14h - 17h: pcnl_bar?primary control block base address register (sata?d31:f2) .. 744 671 offset 18h - 1bh: scmd_bar?secondary command block base address register (ide d31:f1)745 672 offset 14h - 17h: scnl_bar?secondary control block base address register (ide d31:f1) . 745 673 offset 20h - 23h: bar?legacy bus master base address register (sata?d31:f2) ......... 746 674 offset 2ch - 2dh: svid?subsystem vendor id (sata?d31:f2).................................. 746 675 offset 2eh - 2fh: sid?subsystem id (sata?d31:f2) ................................................ 747 676 offset 34h: cap?capabilities pointer register (sata?d31:f2).................................... 747 677 offset 3ch: intr_ln?interrupt line register (sata?d31:f2) ..................................... 747 678 offset 3dh: intr_pn?interrupt pin register (sata?d31:f2) ...................................... 748 679 offset 40 - 41h: ide_timp?primary ide timing register (sata?d31:f2) ..................... 748 680 offset 44h: sidetim?slave ide timing register (sata?d31:f2)................................. 750 681 offset 48h: sdma_cnt?synchronous dma control register (sata?d31:f2) ................. 751 682 offset 4a - 4bh: sdma_tim?synchronous dma timing register (sata?d31:f2) ........... 752 683 offset 54h: ide_config?ide i/o configuration register (sata?d31:f2)..................... 754 684 offset 70 - 71h: pid?pci power management capability id (sata?d31:f2).................. 755 685 offset 72 - 73h: pc?pci power management capabilities (sata?d31:f2) ..................... 755 686 offset 74 - 75h: pmcs?pci power management control and status (sata?d31:f2)....... 756 687 offset 80 - 81h: mid?message signaled interrupt identifiers (sata?d31:f2)................ 757 688 offset 82 - 83h: mc?message signaled interrupt message control (sata?d31:f2) ........ 757 689 offset 84 - 87h: ma?message signaled interrupt message address (sata?d31:f2) ....... 758 690 offset 88 - 89h: md?message signaled interrupt message data (sata?d31:f2) ........... 759 691 offset 90h: map?address map (sata?d31:f2) ......................................................... 759 692 offset 92h: pcs?port status and control (sata?d31:f2) ........................................... 760 693 offset a0h: sri?sata registers index (sata?d31:f2) .............................................. 760 694 offset a4h - a7h: srd?sata registers data (sata?d31:f2)...................................... 761 695 sttt?sata tx termination test register a (sata?d31:f2) ....................................... 762 696 stot ? sata tx output test register (sata?d31:f2)............................................... 762
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 46 order number: 300641-004us 697 offset index 54h - 57h: ser0?sata serror register port 0 (sata?d31:f2) .................. 763 698 offset index 64h - 67h: ser1?sata serror register port 1 (sata?d31:f2) .................. 763 699 offset e0h - e3h: bfcs?bist fis control/status register (sata?d31:f2) .................... 763 700 offset e4h - e7h: bftd1?bist fis transmit data1 register (sata?d31:f2) ................. 765 701 offset e8h - ebh: bftd2?bist fis transmit data2 register (sata?d31:f2) ................. 766 702 bus master ide i/o registers ................................................................................... 766 703 bmic[p,s]?bus master ide command register (d31:f2) ............................................ 767 704 bmis[p,s]?bus master ide status register (d31:f2) ................................................. 768 705 bmid[p,s]?bus master ide descriptor table pointer register (d31:f2)......................... 769 706 signal list (alphabetical list) ................................................................................... 774 707 signal list (by location) .......................................................................................... 781 708 dc current characteristics (preliminary).................................................................... 790 709 dc characteristic input signal association ................................................................. 790 710 dc input characteristics.......................................................................................... 791 711 dc characteristic output signal association ............................................................... 793 712 dc output characteristics........................................................................................ 794 713 other dc characteristics ......................................................................................... 794 714 clock timings ........................................................................................................ 796 715 pci-x interface timings .......................................................................................... 799 716 pci interface timing ............................................................................................... 800 717 ide pio and multiword dma modetiming ................................................................... 801 718 ultra ata timing (mode 0, mode 1, mode 2)............................................................... 802 719 ultra ata timing (mode 3, mode 4, mode 5)............................................................... 804 720 universal serial bus timing...................................................................................... 806 721 sata interface timings ........................................................................................... 808 722 smbus timing ........................................................................................................ 808 723 ac?97 timing ......................................................................................................... 809 724 lpc timing ............................................................................................................ 809 725 miscellaneous timings ............................................................................................. 809 726 uart timings ........................................................................................................ 810 727 power sequencing and reset signal timings .............................................................. 811 728 power management timings..................................................................................... 812 729 clock uncertainty parameters .................................................................................. 813 730 pci-x measurement condition parameters ................................................................. 815 731 test mode selection................................................................................................ 825 732 xor test pattern example ....................................................................................... 827 733 xor chain #1 (rtcrst# asserted for 4 pci clocks while pwrok active)............................................................................................... 827 734 xor chain #2 (rtcrst# asserted for 5 pci clocks while pwrok active)............................................................................................... 828 735 xor chain #3 (rtcrst# asserted for 6 pci clocks while pwrok active)............................................................................................... 829 736 xor chain #4 (rtcrst# asserted for 7 pci clocks while pwrok active)............................................................................................... 831 737 xor chain #5 (rtcrst# asserted for 59 pci clocks while pwrok active)............................................................................................... 831 738 xor chain #6 (rtcrst# asserted for 52 pci clocks while pwrok active)...................... 834 739 xor chain #7 (rtcrst# asserted for 60 pci clocks while pwrok active)...................... 834
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 47 contents?intel ? 6300ESB ich revision history date revision description november 2007 004 ? included specification changes from specification update, version 011 ? figure 61 : updated to replace v_cpu_io with vcchi ? included specifications clarifications from specification update, version 011 ? table 727 and table 728 : updated t175, t176 & t184 timing definitions to clarify which vcc supplies apply to each ? section 5.11.1 and 5.11.6: clarified wording regarding support of c2 state for dual processors, dual core and processors with hyperthreading tec h n o lo gy. ? table 191 : remove incorrect references to tco in note ? section 5.7.1: removed references to three wire apic bus. 6300ESB does not support this feature. ? ta b l e 3 1 : moved note 1 refernces from i/o to memory cycles ? table 727 : changed note 2 to require that 3.3v and 1.5v rails must power up or down together ? removed all references to processor speed strapping. processors used in conjunction with 6300ESB do not use this feature. ? table 319 : modified register defintions to reflect that signals are configured as native functions after a full reset. ? section 19.1 : add note to indicate that sius are not completely 16550 compatible. ? table 635 : added % error rates. ? section 5.10.2.2 : changed to clarify where multiple processor or multiple core configurations can generate stop grant cycles in the mch supports it. ? included documentation changes 2 to 13 from specification update, version 011 ? table 568 : revised to allow bit column to align correctly. ? section 22.2 : added case temperature under bias value ? changed all references to pcirst# to pxpcirst# ? table 317 : changed register deult value to 00000000h ? figure 5 : correct typo in diagram ? ta b l e 2 8 : change gpio[21] after reset value to logic ?1? ? corrected product features section to show that pci-x rev 1.0 is supported ? ta b l e 2 2 : correct v5ref definition ? table 573 : correct indexes for reserved registers ? table 581 : revised naming and definitions for bits 10:8 and 7:0. added note at bottom of table. ? table 728 : revised ?slp_s5# inactive to slp_s4#? parameter timing values ? ta b le 3 1 3 : removed gpo_ttl register listing. this register was not relevant to 6300ESB ? ta b le 2 9 , figure 61 and figure 62 : removed references to lan_rst and rsm_pwrok signals which do not exist in 6300ESB ? ta b le 7 3 1 , figure 66 : updated to correct timing requirements for entering test mode. ? section 5.7 and section 8.5 : removed pci register references for apic0. apic0 registers are purely memory mapped.
intel ? 6300ESB ich?contents intel ? 6300ESB i/o controller hub ds november 2007 48 order number: 300641-004us change bars a change bar to left of text, a table row or a figure heading indicates this item is either new or modified from the previous version of the document. december 2004 003 ? included changes from previous spec updates ? updated section 22.1 ? updated section 22.2 ? updated dc characteristics section 22.3 ? -updated ac characteristics section 22.4 june 2004 002 ? clarified wdt reload register bit details; listed usb hs reference voltage register bits. february 2004 001 ? initial release of this document. date revision description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 49 1?intel ? 6300ESB ich introduction 1 1.1 about this document this datasheet is intended for original equipment manufacturers (oems) and bios vendors creating products based on the intel ? 6300ESB i/o controller hub (ich). this manual assumes a working knowledge of the vocabulary and principles of usb, ide, ac?97, smbus, pci, acpi, and lpc. although some details of these features are described herein, refer to the individual industry specifications listed in ta b l e 1 for the complete details. table 1. industry specifications specification location low pin count interface specification, revision 1.0 (lpc) http://developer.intel.com/design/chipsets/ industry/lpc.htm audio codec ?97 component specification, version 2.2 (ac?97) http://www.intel.com/labs/media/audio/ index.htm pci-x specification, revision 1.0 http://www.pcisig.com/specifications/pcix_20/ pci_x/ system management bus specification, version 2.0 (smbus) http://www.smbus.org/specs/ pci local bus specification, revision 2.2 (pci) http://pcisig.com/specs.htm universal serial bus revision 2.0/1.0 specification (usb) http://www.usb.org advanced configuration and power interface, version 1.0b (acpi) http://www.teleport.com/~acpi/ enhanced host controller interface specification for universal serial bus, revision 0.96 (ehci) http://developer.intel.com/technology/usb/ ehcispec.htm sata 1.0 specification http://www.serialata.org/collateral/index.shtml other industry specifications http://www.intel.com/design/motherbd/bv/ bv_industryspecs.htm
intel ? 6300ESB ich?1 intel ? 6300ESB i/o controller hub ds november 2007 50 order number: 300641-004us this document contains these chapters: chapter 1, ?introduction? introduces the intel ? 6300ESB ich and provides information on manual organization. chapter 3, ?signal description? provides a detailed description of each intel ? 6300ESB ich signal. signals are arranged according to interface. details are provided about the drive characteristics (input/output, open drain, etc.) of all signals. chapter 2, ?intel? 6300ESB ich and system clock domains? provides a list of each clock domain associated with the intel ? 6300ESB ich in an intel ? 6300ESB ich-based system. chapter 4, ?intel? 6300ESB ich power planes and pin states? provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. chapter 5, ?functional description? provides a detailed description of the functions in the intel ? 6300ESB ich. all pci buses, devices, and functions in this manual are abbreviated using the following nomenclature; bus:device:function. this manual abbreviates buses as b0 and b1, devices as d8, d29, d30 and d31 and functions as f0, f1, f2, f3, f4, f5, f6 and f7. for example device 31 function 5 is abbreviated as d31:f5, bus 1 device 8 function 0 is abbreviated as b1:d8:f0. generally, the bus number will not be used, and may be considered to be bus 0. note that the intel ? 6300ESB ich?s external pci bus is typically bus 1, but may be assigned a different number depending upon system configuration. chapter 6, ?register and memory mapping? provides an overview of the registers, fixed i/o ranges, variable i/o ranges, and memory ranges decoded by the intel ? 6300ESB ich. chapter 7, ?hub interface to pci bridge registers (d30:f0)? provides a detailed description of all registers that reside in the hub interface to pci bridge. this bridge resides at device 30, function 0 (d30:f0). chapter 8, ?lpc i/f bridge registers (d31:f0)? provides a detailed description of all registers that reside in the lpc bridge. this bridge resides at device 31, function 0 (d31:f0). this function contains registers for many different units within the intel ? 6300ESB ich including dma, timers, interrupts, cpu interface, gpio, power management, system management and rtc. chapter 9, ?ide controller registers (d31:f1)? provides a detailed description of all registers that reside in the ide controller. this controller resides at device 31, function 1 (d31:f1). chapter 10, ?usb uhci controllers registers? provides a detailed description of all registers that reside in the three uhci host controllers. these controllers reside at device 29, functions 0, 1 and 2 (d29:f0/f1/f2). chapter 11, ?usb ehci controller registers (d29:f7)? provides a detailed description of all registers that reside in the ehci host controller. this controller resides at device 29, function 7 (d29:f7). chapter 12, ?smbus controller registers (d31:f3)? provides a detailed description of all registers that reside in the smbus controller. this controller resides at device 31, function 3 (d31:f3).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 51 1?intel ? 6300ESB ich chapter 13, ?ac?97 audio controller registers (d31:f5)? provides a detailed description of all registers that reside in the audio controller. this controller resides at device 31, function 5 (d31:f5). note that this section of the eds does not include the native audio mixer registers. accesses to the mixer registers are forwarded over the ac-link to the codec where the registers reside. chapter 14, ?ac?97 modem controller registers (d31:f6)? provides a detailed description of all registers that reside in the modem controller. this controller resides at device 31, function 6 (d31:f6). note that this section of the eds does not include the modem mixer registers. accesses to the mixer registers are forwarded over the ac-link to the codec where the registers reside. chapter 15, ?multimedia timer registers? provides a detailed description of all registers that reside in the multimedia event timer memory mapped register space. chapter 16, ?watchdog timer (wdt) (d29:f4)? provides a detailed description of the configuration registers in the wdt controller. these registers reside at device 29, function 4 (d29:f4). chapter 17, ?apic1 configuration registers (d29:f5)? provides a detailed description of the configuration registers in the apic1 controller. these registers reside at device 29, function 5 (d29:f5). chapter 18, ?pci-x overview (d28:f0)? provides a detailed description of the configuration registers of the pci-x controller. these registers reside at device 28, function 0 (d28:f0). chapter 19, ?serial i/o unit? describes the siu, its features, lpc interface, serial ports and port 60/64 emulation along with a description of the registers in the siu. these registers reside at device 31, function 0 (d31:f0). chapter 20, ?serial ata controller registers (d31:f2)? provides a detailed description of the registers that reside in the sata controller which encompasses a pci device. this controller resides at device 31, function 2 (d31:f2). chapter 21, ?package information? provides ballout information, signal lists and mechanical drawings. chapter 22, ?electrical characteristics? provides ac and dc characteristics and ac timings. chapter 23, ?testability? provides information on test modes and scan chains.
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intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 53 2?intel ? 6300ESB ich intel ? 6300ESB ich and system clock domains 2 warning: this section is provided for background purposes and should not be considered by implementers and validators as part of the behavioral definition of the intel ? 6300ESB ich. tab l e 2 presents the intel ? 6300ESB ich clock domains. figure 4 shows the assumed connection of the various system components, including the clock generator in desktop systems. for complete details of the system clocking solution, refer to the system?s clock generator component specification. table 2. intel ? 6300ESB ich clock domains clock domain frequency source usage hub interface 66.66 mhz main clock generator hub interface, cpu i/f, agp. shut off during s3 or below. pci 33.33 mhz main clock generator the intel ? 6300ESB ich, pci, lpc i/f. this remains on during s0-s1 states, and may be shut off during s3-s5. the pci clock to peripherals may be shut off using the clkrun# protocols. usb/sio 48.00 mhz main clock generator usb 1.0 controllers in the intel ? 6300ESB ich, external super i/o. shut off in s3 or below. usb2.0 48.00 mhz internal usb 2.0 logic close to the pins. shut off when the 48 mhz clock input is shut off (s1 for low power, as well as s3 or below) osc 14.31818 m hz main clock generator used by acpi timer. also used by the multimedia timers logic. shut off in s1 for low power, as well as s3 or below. ac?97 12.288 mhz ac?97 codec ac?97 link. generated by ac?97 codec. may be shut off by codec in d3, as well as s1 for low power, and s3 or below. rtc 32.768 khz intel ? 6300ESB ich rtc, power management. the intel ? 6300ESB ich has its own oscillator. always running, even in g3 state. pci-x 66 mhz external uart 14.7456, 48 mhz main clock generator and/or discrete clock circuit. uart clock input. note: some clock chips provide a 14.318x mhz clock output. the intel ? 6300ESB ich?s uart clock must use a 14.7456 mhz frequency; most clock chips do not provide this frequency. an option will be to use the 48.0 mhz clock. sata 100 mhz main clock generator 1.5 ghz clock generated internal to the intel ? 6300ESB ich for use by sata phy.
intel ? 6300ESB ich?2 intel ? 6300ESB i/o controller hub ds november 2007 54 order number: 300641-004us figure 4. conceptual system clock diagram intel ? 6300ESB ich pci clocks (33 mhz) clock gen. 14.31818 mh z 48 mhz 32 khz xtal susclk# (32 khz) ac?97 codec(s) 12.288 mhz 66 mhz 33 mhz 14.31818 mhz 48 mhz 100 mhz diff. pair
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 55 3?intel ? 6300ESB ich signal description 3 this section provides a detailed description of each signal. the signals are arranged in functional groups according to their associated interface. the ?#? symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present, the signal is asserted when at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin od open drain output pin i/o bi-directional input/output pin 3.1 hub interface to host controller table 3. hub interface signals name type description hi[11:0] i/o hub interface signals hi_stbs i/o hub interface strobe second: one of two differential strobe signals used to transmit and receive data through the hub interface. hub interface 1.5 mode this signal is not differential and is the second of the two strobe signals. hi_stbf i/o hub interface strobe first: one of two differential strobe signals used to transmit and receive data through the hub interface. hub interface 1.5 mode this signal is not differential and is the first of the two strobe signals. hicomp i/o hub interface compensation: used for hub interface buffer compensation. note: the intel ? 6300ESB ich will only support rcomp, not the zcomp mode. hiclk i hub interface clock: 66 mhz clock input for hub interface. it is also used for some other internal units. this clock will stop during s3-s5 states.
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 56 order number: 300641-004us 3.2 firmware hub interface hiref i hub interface voltage reference. analog input, expected voltage 350mv hi_vswing i hub interface voltage swing: analog input used to control the voltage swing and impedance strength of hub interface pins. expected voltage is 800 mv. notes: 1. refer to the platform design guide for expected voltages. 2. refer to the platform design guide for resistor values and routing guidelines for each hub interface mode. notes: 1. the hub interface signals are all in a separate power plane, called the hub interface plane. 2. during the s3, s4, and s5 states, power to the hub interface is assumed to be off. during s0 and s1 states, power to the hub interface must be on. table 4. firmware hub interface signals name type description fwh[3:0] / lad[3:0] i/o firmware hub signals. muxed with lpc address signals. internal pull-ups are provided. fwh[4] / lframe# i/o firmware hub signals. muxed with lpc lframe# signal. lframe#: indicates the start of an lpc cycle, or an abort. note: all lpc/fwh signals are in the core well. table 3. hub interface signals
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 57 3?intel ? 6300ESB ich 3.3 pci interface table 5. pci interface signals (sheet 1 of 3) signal name type description ad[31:0] i/o pci address/data: ad[31:0] signals are multiplexed. during the first clock of a transaction, ad[31:0] contain the physical address (32 bits). after the first clock, ad[31:0] contain data. c/ be[3:0]# i/o bus command and byte enables: the command and byte enable signals are multiplexed. during the address phase of a transaction, c/ be[3:0]# define the bus command. during the data phase c/be[3:0]# are used as byte enables. all command encoding not shown are reserved. c/be[3:0]# command type comment 0 0 0 0 interrupt acknowledge 0 0 0 1 special cycle 0 0 1 0 i/o read 0 0 1 1 i/o write 0 1 1 0 memory read 0 1 1 1 memory write 1 0 1 0 configuration read 1 0 1 1 configuration write 1 1 0 0 memory read multiple 1 1 0 1 dac mode address to be latched (target only) 1 1 1 0 memory read line 1 1 1 1 memory write and invalidate the intel ? 6300ESB ich will not use reserved values, and will not respond if a pci master generates a cycle using a reserved value. see pci section for details on how these commands are supported depending on the intel ? 6300ESB ich?s role in the pci cycle (target or initiator). as a target, the intel ? 6300ESB ich can support dac mode addressing for 44 bits. devsel# i/o device select: the intel ? 6300ESB ich asserts devsel# to claim a pci transaction. as an output, the intel ? 6300ESB ich asserts devsel# when a pci master peripheral attempts an access to an internal intel ? 6300ESB ich address or an address destined for hub interface (main memory or agp). as an input, devsel# indicates the response to an intel ? 6300ESB ich-initiated transaction on the pci bus. devsel# is tri- stated from the leading edge of pxpcirst#. devsel# remains tri-stated by the intel ? 6300ESB ich until driven as a target. frame# i/o cycle frame: frame# is driven by the current initiator to indicate the beginning and duration of an access. while frame# is asserted data transfers continue. when frame# is negated the transaction is in the final data phase. frame# is an input to the intel ? 6300ESB ich when it is the target. frame# is an output when the intel ? 6300ESB ich is the initiator. frame# remains tri-stated by the intel ? 6300ESB ich until driven as an initiator. irdy# i/o initiator ready: irdy# indicates the intel ? 6300ESB ich?s ability, as an initiator, to complete the current data phase of the transaction. it is used in conjunction with trdy#. a data phase is completed on any clock both irdy# and trdy# are sampled asserted. during a write, irdy# indicates the intel ? 6300ESB ich has valid data present on ad[31:0]. during a read, it indicates the intel ? 6300ESB ich is prepared to latch data. irdy# is an input to the intel ? 6300ESB ich when the intel ? 6300ESB ich is the target and an output when the intel ? 6300ESB ich is an initiator. irdy# remains tri-stated by the intel ? 6300ESB ich until driven as an initiator.
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 58 order number: 300641-004us trdy# i/o target ready: trdy# indicates the intel ? 6300ESB ich?s ability to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. a data phase is completed when both trdy# and irdy# are sampled asserted. during a read, trdy# indicates that the intel ? 6300ESB ich, as a target, has placed valid data on ad[31:0]. during a write, it indicates the intel ? 6300ESB ich, as a target is prepared to latch data. trdy# is an input to the intel ? 6300ESB ich when the intel ? 6300ESB ich is the initiator and an output when the intel ? 6300ESB ich is a target. trdy# is tri-stated from the leading edge of pxpcirst#. trdy# remains tri-stated by the intel ? 6300ESB ich until driven as a target. stop# i/o stop: stop# indicates that the intel ? 6300ESB ich, as a target, is requesting an initiator to stop the current transaction. as an initiator, stop# causes the intel ? 6300ESB ich to stop the current transaction. stop# is an output when the intel ? 6300ESB ich is a target and an input when the intel ? 6300ESB ich is an initiator. stop# is tri-stated from the leading edge of pxpcirst#, and remains tri-stated until driven by the intel ? 6300ESB ich as a slave. par i/o calculated/checked parity: par is ?even? parity and is calculated on 36 bits ? ad[31:0] plus c/be[3:0]#. ?even? parity means that the number of ?1?s within the 36 bits plus par are counted and the sum is always even. par is always calculated on 36 bits regardless of the valid byte enables. par is generated for address and data phases, and is only ensured to be valid one pci clock after the corresponding address or data phase. par is driven and tri-stated identically to the ad[31:0] lines, except that par is delayed by exactly one pci clock. par is an output during the address phase (delayed one clock) for all intel ? 6300ESB ich initiated transactions. it is also an output during the data phase (delayed one clock) when the intel ? 6300ESB ich is the initiator of a pci write transaction, and when it is the target of a read transaction. the intel ? 6300ESB ich checks parity on the data phase when it is the initiator of pci read transactions and when it is the target of pci write transactions. it also checks parity on the address phase when it is the target of pci transitions. if a parity error is detected, the intel ? 6300ESB ich will set the appropriate internal status bits, and has the option to generate an nmi# or smi#. perr# i/o parity error: driven by an external pci device when it receives data that has a parity error. driven by the intel ? 6300ESB ich when it detects a parity error. the intel ? 6300ESB ich can either generate an nmi# or smi# upon detecting a parity error (either detected internally or reported via perr# signal) when serving as an initiator. req[0:3]# i pci requests: supports up to 4 external masters on the pci bus. gnt[0:3]# o pci grants: supports up to 4 external masters on the pci bus. pciclk i note: pci clock: 33 mhz clock. pciclk provides timing for all transactions on the pci bus, as well as many units inside the intel ? 6300ESB ich. this clock can be stopped in s1 or s3, s4, or s5 states. this signal is not 5 v tolerant. table 5. pci interface signals (sheet 2 of 3) signal name type description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 59 3?intel ? 6300ESB ich plock# i/o pci lock: indicates an exclusive bus operation and may require multiple transactions to complete. the intel ? 6300ESB ich ich asserts plock# when it is doing non-exclusive transactions on pci. plock# is ignored when pci masters are granted the bus. serr# i/od system error: serr# can be pulsed active by any pci device that detects a system error condition. upon sampling serr# active, the intel ? 6300ESB ich can be programmed to generate an nmi or smi#. implemented as i/o open drain. this allows the intel ? 6300ESB ich to drive these signals due to internal sources. pme# i/od pci power management event: driven by pci peripherals to wake the system from low-power states s1-s5. if can also cause an sci from the s0 state. note that in some cases the intel ? 6300ESB ich may drive pme# active (low) due to an internal wake event. it will not drive pme# high (but it may be pulled up using the internal pull-up resistor). note: pme# is in the resume power plane and has an internal pull-up resistor. note: pme# is also used in the pci-x segment. table 5. pci interface signals (sheet 3 of 3) signal name type description
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 60 order number: 300641-004us 3.4 pci-x interface table 6. pci-x interface signals (sheet 1 of 4) name type description pxad[31:0] i/o pci-x address/data: these signals are a multiplexed address and data bus. during the address phase or phases of a transaction, the initiator drives a physical address on pxad[31:0]. during the data phases of a transaction, the initiator drives write data, or the target drives read data. the intel ? 6300ESB ich will drive all 0?s on pxad[31:0] during the address phase of all pci-x special cycles. pxad[63:32 ] i/o pc-x address/data: these signals are a multiplexed address and data bus. this bus provides an additional 32 bits to the pci-x bus. during the data phases of a transaction, the initiator drives the upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when pxreq64# and pxack64# are both asserted. when not driven pxad[63:32] are pulled up to a valid logic level through external resistors. note: when not driven pxad[63:32] are pulled up to a valid logic level through external resistors. pxc/ be#[3:0] i/o bus command and byte enables : the command and byte enable signals are multiplexed on the same pci-x pins. during the address phase of a transaction, pxc/be#[3:0] define the bus command. during the data phase pxc/be[3:0]# define the byte enables. pxc/be#[3:0] command type 0 0 0 0 interrupt acknowledge 0 0 0 1 special cycle 0 0 1 0 i/o read 0 0 1 1 i/o write 0 1 1 0 memory read 0 1 1 1 memory write 1 0 1 0 configuration read 1 0 1 1 configuration write 1 1 0 0 memory read multiple 1 1 1 0 memory read line 1 1 1 1 memory write and invalidate all command encodings not shown are reserved. the intel ? 6300ESB ich does not decode reserved values, and therefore will not respond when a pci-x master generates a cycle using one of the reserved values. pxc/ be#[7:4] i/o bus command and byte enables upper 4 bits: these signals are a multiplexed command field and byte enable field. for both reads and write transactions, the initiator will drive byte enables for the pxad[63:32] data bits on pxc/be#[7:4] during the data phases when pxreq64# and pxack64# are both asserted. when not driven, pxc/be#[7:4] are pulled up to a valid logic level through external resistors. pxdevsel# i/o device select: the intel ? 6300ESB ich asserts pxdevsel# to claim a pci transaction. as an output, the intel ? 6300ESB ich asserts devsel# when a pci master peripheral attempts an access to an internal intel ? 6300ESB ich address or an address destined for the hub interface (main memory or agp). as an input, devsel# indicates the response to an intel ? 6300ESB ich-initiated transaction on the pci bus. devsel# is tri-stated from the leading edge of pxpcirst#. pxdevsel# remains tri-stated by the intel ? 6300ESB ich until driven by a target device.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 61 3?intel ? 6300ESB ich pxframe# i/o cycle frame: the current initiator drives pxframe# to indicate the beginning and duration of a pci transaction. while the initiator asserts pxframe#, data transfers continue. when the initiator negates pxframe#, the transaction is in the final data phase.pxframe# is an input to the intel ? 6300ESB ich when the intel ? 6300ESB ich is the target, and pxframe# is an output from the intel ? 6300ESB ich when the intel ? 6300ESB ich is the initiator. pxframe# remains tri-stated by the intel ? 6300ESB ich until driven by an initiator. pxirdy# i/o initiator ready: pxirdy# indicates the intel ? 6300ESB ich's ability, as an initiator, to complete the current data phase of the transaction. it is used in conjunction with pxtrdy#. a data phase is completed on any clock both pxirdy# and pxtrdy# are sampled asserted. during a write, pxirdy# indicates the intel ? 6300ESB ich has valid data present on pxad[31:0]. during a read, it indicates the intel ? 6300ESB ich is prepared to latch data. pxirdy# is an input to the intel ? 6300ESB ich when the intel ? 6300ESB ich is the target and an output from the intel ? 6300ESB ich when the intel ? 6300ESB ich is an initiator. pxirdy# remains tri-stated by the intel ? 6300ESB ich until driven by an initiator. pxtrdy# i/o target ready: pxtrdy# indicates the intel ? 6300ESB ich's ability as a target to complete the current data phase of the transaction pxtrdy# is used in conjunction with irdy#. a data phase is completed when both pxtrdy# and pxirdy# are sampled asserted. during a read, pxtrdy# indicates that the intel ? 6300ESB ich, as a target, has placed valid data on pxad[31:0]. during a write, pxtrdy# indicates the intel ? 6300ESB ich, as a target is prepared to latch data pxtrdy# is an input to the intel ? 6300ESB ich when the intel ? 6300ESB ich is the initiator and an output from the intel ? 6300ESB ich when the intel ? 6300ESB ich is a target. pxtrdy# is tri-stated from the leading edge of pxpcirst#. pxtrdy# remains tri-stated by the intel ? 6300ESB ich until driven by a target. pxstop# i/o stop: pxstop# indicates that the intel ? 6300ESB ich, as a target, is requesting the initiator to stop the current transaction. pxstop# causes the intel ? 6300ESB ich, as an initiator, to stop the current transaction. pxstop# is an output when the intel ? 6300ESB ich is a target and an input when the intel ? 6300ESB ich is an initiator. pxstop# is tri-stated from the leading edge of pxpcirst#. pxstop# remains tri-stated until driven by the intel ? 6300ESB ich. pxpar i/o calculated/checked parity: pxpar uses ?even? parity calculated on 36 bits, pxad[31:0] plus pxc/be[3:0]#. ?even? parity means that the intel ? 6300ESB ich counts the number of ?1?s within the 36 bits plus pxpar and the sum is always even. the intel ? 6300ESB ich always calculates pxpar on 36 bits regardless of the valid byte enables. the intel ? 6300ESB ich generates pxpar for address and data phases and only ensures pxpar to be valid one pci clock after the corresponding address or data phase. the intel ? 6300ESB ich drives and tri-states pxpar identically to the pxad[31:0] lines except that the intel ? 6300ESB ich delays par by exactly one pxpci clock. pxpar is an output during the address phase (delayed one clock) for all intel ? 6300ESB ich initiated transactions. pxpar is an output during the data phase (delayed one clock) when the intel ? 6300ESB ich is the initiator of a pci-x write transaction, and when it is the target of a read transaction. the intel ? 6300ESB ich checks parity when it is the target of a pc-x write transaction. when a parity error is detected, the intel ? 6300ESB ich will set the appropriate internal status bits, and has the option to generate an nmi# or smi#. table 6. pci-x interface signals (sheet 2 of 4) name type description
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 62 order number: 300641-004us pxperr# i/o parity error: an external pci-x device drives pxperr# when it receives data that has a parity error. the intel ? 6300ESB ich drives pxperr# when it detects a parity error. the intel ? 6300ESB ich may either generate an nmi# or smi# upon detecting a parity error (either detected internally or reported via the pxperr# signal) when serving as an initiator. pxreq[1:0] # pxreq[2]# /gpio[0] pxreq[3]# / gpio[1] i pci-x requests: supports up to four masters on the pci-x bus. the intel ? 6300ESB ich accepts four request inputs, pxreq[3:0]# into its internal bus arbiter. the intel ? 6300ESB ich request input to the arbiter is an internal signal. note: when operating in pci 64b/66mhz, only two external masters should be used,pxreq0, pxreq1. pxreq[2]# is muxed with gpio[0] pxreq[3]# is muxed with gpio[1] pxgnt[1:0] # pxgnt[2]# / gpio[16] pxgnt[3]# / gpio[17] o pci-x grants: supports up to 4 masters on the pci-x bus. pxgnt[2]# is muxed with gpio[16] pxgnt[3]# is muxed with gpio[17] note: when operating in pci 64b/66 mhz, only two external masters should be used: pxgnt0, pxgnt1. pxpclki i pci-x clock in: this signal is connected to an output of the low skew pci clock buffer tree(pxpclko[4]. it is used by the pll to synchronize the pci clock driven from pxpclko[4] to the clock used for the internal pci-x logic. pxpclko[4: 0] o pci-x clock output: 33/66 mhz clock for a pci device. pxpclko[4] is connected to the pxpclki input. in pci 64/66 mode pxpclko(1:0) are ensured to be driven. pxpciclk i pci-x clock: pxpciclk is the clock for the internal pci-x circuitry. 66mhz primary input clock. pxrcomp i/o impedance compensation: used to determine the impedance between the intel ? 6300ESB ich and the pci-x slots. raserr# od ras error: this pin indicates that a ras error has been logged. this is an active low signal that is a logical or of all the ras error events. if one of these errors is active, the pin is low. if none are active, then the pin is high. pxpcirst# o pci/pci-x reset: the intel ? 6300ESB ich asserts pxpcirst# to reset devices that reside on the pci-x bus. the intel ? 6300ESB ich asserts pxpcirst# during power-up and when s/w initiates a hard reset sequence through the rc (cf9h) register. the intel ? 6300ESB ich drives pxpcirst# inactive a minimum of 1 ms after pwrok is driven active. the intel ? 6300ESB ich drives pxpcirst# active a minimum of 1 ms when initiated through the rc (cf9h) register. note: pxpcirst# is in the resume power plane. this signal also causes the legacy pci bus and external pci-x bus to reset pxplock# i/o pci-x lock: indicates an exclusive bus operation and may require multiple transactions to complete. the intel ? 6300ESB ich asserts pxplock# when it performs exclusive transactions on the pci-x bus. plock# is ignored when pci-x masters are granted the bus. the intel ? 6300ESB ich does not propagate locked transaction upstream. table 6. pci-x interface signals (sheet 3 of 4) name type description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 63 3?intel ? 6300ESB ich pxserr# i/od system error: pxserr# may be pulsed active by any pc-x device that detects a system error condition except intel ? 6300ESB ich. the intel ? 6300ESB ich samples pxserr# as an input and conditionally forwards it to the hub interface. upon sampling pxserr# active, the intel ? 6300ESB ich may be programmed to generate an nmi or smi#. pme# i/od pci power management event : pci-x peripherals drive pme# to wake the system from low-power states s1?s5. pme# assertion may also be enabled to generate a sci from the s0 state. in some cases the intel ? 6300ESB ich may drive pme# active due to an internal wake event. the intel ? 6300ESB ich will not drive pme# high, but it will be pulled up to vccsus3_3 by an internal pull-up resistor. note: pme# is in the resume power plane and has an internal pull- up resistor. pme# control logic is in the primary pci bus logic and not the pci-x bridge pxm66en i 66mhz enable: this input signal from the pci-x bus indicates the speed of the pci-x bus. when it is high, the bus speed is 66 mhz and when it is low, the bus speed is 33 mhz. this signal will be used to generate appropriate clock (33 or 66mhz) on the pci-x bus. pxpcixcap i pci-x capable: indicates whether all devices on the pci-x bus are pci-x devices, so that the intel ? 6300ESB ich may switch into pci-x mode pxpar64 i/o pci-x interface upper 32-bits parity: this carries the even parity of the 36 bits of pxad[63:32] and pxc/be#[7:4] for both address and data phases. when not driven, pxpar64 is pulled up to a valid logic level through external resistors pxreq64# i/o pci-x interface request 64-bit transfer: this is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. it has the same timing as pxframe#. when the intel ? 6300ESB ich is the initiator, this signal is an output. when the intel ? 6300ESB ich is the target this signal is an input pxack64# i/o pci-x interface acknowledge 64-bit transfer: this is asserted by the target only when pxreq64# is asserted by the initiator, to indicate the target?s ability to transfer data using 64 bits. it has the same timing as pxdevsel# pcixsbrst # o pci-x secondary bus reset : the intel ? 6300ESB ich asserts pcixsbrst# to reset devices that reside on the pci-x bus. the intel ? 6300ESB ich asserts pcixsbrst# when the pxpcirst# pin is asserted or when sbr bit is set. table 6. pci-x interface signals (sheet 4 of 4) name type description
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 64 order number: 300641-004us 3.5 sata interface 3.6 ide interface table 7. sata interface signals name type description sata0txp sata0txn o serial ata 0 differential transmit pair: outbound high speed differential signals to port 0. sata0rxp sata0rxn i serial ata 0 differential receive pair: inbound high speed differential signals from port 0. sata1txp sata1txn o serial ata 1 differential transmit pair: outbound high speed differential signals to port 1. sata1rxp sata1rxn i serial ata 1 differential receive pair: inbound high speed differential signals from port 1. sataclkp, sataclkn i differential sata clock: 100 mhz clock input from the clock generator sataled# od serial ata led#: output indicates serial ata drive activity when it is driven low satarbiasp satarbiasn i serial ata resistor bias: analog connection point for a external resistor to ground. table 8. ide interface signals (sheet 1 of 2) name type description pdcs1#, sdcs1# o primary and secondary ide device chip selects for 100 range: for ata command register block. this output signal is connected to the corresponding signal on the primary or secondary ide connector. pdcs3#, sdcs3# o primary and secondary ide device chip select for 300 range: for ata control register block. this output signal is connected to the corresponding signal on the primary or secondary ide connector. pda[2:0], sda[2:0] o primary and secondary ide device address: these output signals are connected to the corresponding signals on the primary or secondary ide connectors. they are used to indicate which byte in either the ata command block or control block is being addressed. pdd[15:0], sdd[15:0] i/o primary and secondary ide device data: these signals directly drive the corresponding signals on the primary or secondary ide connector. there is a weak internal pull-down resistor on pdd[7] and sdd[7]. pddreq, sddreq i primary and secondary ide device dma request: these input signals are directly driven from the drq signals on the primary or secondary ide connector. it is asserted by the ide device to request a data transfer, and used in conjunction with the pci bus master ide function and are not associated with any at compatible dma channel. there is a weak internal pull-down resistor on these signals. notes: 1. the ide signals are 5v tolerant. 2. the ide signals have integrated series terminating resistors. 3. all signals may be tri-stated or driven low for mobile swap bays.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 65 3?intel ? 6300ESB ich pddack#, sddack# o primary and secondary ide device dma acknowledge: these signals directly drive the dak# signals on the primary and secondary ide connectors. each is asserted by the intel ? 6300ESB ich to indicate to ide dma slave devices that a given data transfer cycle (assertion of dior# or diow#) is a dma data transfer cycle. this signal is used in conjunction with the pci bus master ide function and are not associated with any at-compatible dma channel. pdior# / (pdwstb / prdmardy#) sdior# / (sdwstb / srdmardy#) o primary and secondary disk i/o read (pio and non-ultra dma): this is the command to the ide device that it may drive data onto the pdd or sdd lines. data is latched by the intel ? 6300ESB ich on the deassertion edge of pdior# or sdior#. the ide device is selected either by the ata register file chip selects (pdcs1# or sdcs1#, pdcs3# or sdcs3#) and the pda or sda lines, or the ide dma acknowledge (pddak# or sddak#). primary and secondary disk write strobe (ultra dma writes to disk): this is the data write strobe for writes to disk. when writing to disk, the intel ? 6300ESB ich drives valid data on rising and falling edges of pdwstb or sdwstb. primary and secondary disk dma ready (ultra dma reads from disk): this is the dma ready for reads from disk. when reading from disk, the intel ? 6300ESB ich deasserts prdmardy# or srdmardy# to pause burst data transfers. pdiow# / (pdstop) sdiow# / (sdstop) o primary and secondary disk i/o write (pio and non-ultra dma): this is the command to the ide device that it may latch data from the pdd or sdd lines. data is latched by the ide device on the deassertion edge of pdiow# or sdiow#. the ide device is selected either by the ata register file chip selects (pdcs1# or sdcs1#, pdcs3# or sdcs3#) and the pda or sda lines, or the ide dma acknowledge (pddak# or sddak#). primary and secondary disk stop (ultra dma): the intel ? 6300ESB ich asserts this signal to terminate a burst. piordy / (pdrstb / pwdmardy#) siordy / (sdrstb / swdmardy#) i primary and secondary i/o channel ready (pio): this signal will keep the strobe active (pdior# or sdior# on reads, pdiow# or sdiow# on writes) longer than the minimum width. it adds wait states to pio transfers. primary and secondary disk read strobe (ultra dma reads from disk): when reading from disk, the intel ? 6300ESB ich latches data on rising and falling edges of this signal from the disk. primary and secondary disk dma ready (ultra dma writes to disk): when writing to disk, this is deasserted by the disk to pause burst data transfers. table 8. ide interface signals (sheet 2 of 2) name type description notes: 1. the ide signals are 5v tolerant. 2. the ide signals have integrated series terminating resistors. 3. all signals may be tri-stated or driven low for mobile swap bays.
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 66 order number: 300641-004us 3.7 lpc i/f 3.8 interrupt interface table 9. lpc interface signals name typ e description lad[3:0] / fwh[3:0] i/o lpc multiplexed command, address, data: internal pull-ups are provided. lframe# / fwh[4] i/o lpc frame: indicates the start of an lpc cycle, or an abort. ldrq[1:0 ]# i lpc serial dma/master request inputs: used by lpc devices, such as super i/o chips, to request dma or bus master access. note: all lpc/fwh signals are in the core well table 10. interrupt signals (sheet 1 of 2) name type description serirq i/o serial interrupt request: this pin implements the serial interrupt protocol. pirq[d:a]# i pci interrupt requests: in non-apic mode the pirqx# signals may be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the interrupt steering section. each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirq[a]# irq16 pirq[b]# irq17 pirq[c]# irq18 pirq[d]# irq19 this frees the legacy interrupts. these signals are 5v tolerant. note: the interrupt signals are 5v tolerant except for pxirq [3:0]# / gpio[36:33]
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 67 3?intel ? 6300ESB ich 3.9 usb interface pirq[h:e]# / gpio[5:2] i pci interrupt requests: in non-apic mode the pirqx# signals may be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the interrupt steering section. each pirqx# line has a separate route control register. these signals are 5 v tolerant. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirq[e] irq[20] pirq[f] irq[21] pirq[g] irq[22] pirq[h] irq[23] note: when not connected as interrupts on the board, these pins must be programmed as gpi. this ensures proper interrupt delivery from internal sources regardless of the board termination on these pins. irq[14-15] i interrupt request 14?15: these interrupt inputs are connected to the ide drives. irq14 is used by the drives connected to the primary controller and irq15 is used by the drives connected to the secondary controller. these signals are 5 v tolerant. pxirq[3:0]# / gpio[36:33] i pci-x bus interrupt request: the pirq# lines from pci-x interrupts, inta, intb, intc, intd], may be routed to these interrupt lines. pxirq[3:0]# are connected to an i/oxapic that resides on the pci-x bus. table 11. usb interface signals name type description usbp0p, usbp0n, usbp1p, usbp1n, usbp2p, usbp2n, usbp3p, usbp3n i/o universal serial bus port 3:0 differentials: bus data/ address/command bus. note: no external resistors are required on these signals. the intel ? 6300ESB ich integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor oc[3:0]# i overcurrent indicators: these signals set corresponding bits in the usb controllers to indicate that an overcurrent condition has occurred. usbrbias o usb resistor bias: analog connection point for an external resistor to ground. usbrbias should be connected to usbrbias# as close to the resistor as possible. usbrbias# i usb resistor bias complement: analog connection point for an external resistor to ground. usbrbias# should be connected to usbrbias as close to the resistor as possible. notes: 1. the usb signals are all in the resume well. 2. since oc[3:0]# are in the 5 v tolerant resume well, the external biasing resistors are not required. 3. all 4 ports support both usb1.0 and usb2.0 signaling. table 10. interrupt signals (sheet 2 of 2) name type description note: the interrupt signals are 5v tolerant except for pxirq [3:0]# / gpio[36:33]
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 68 order number: 300641-004us 3.10 power management interface table 12. power management interface signals (sheet 1 of 2) name type description thrm# i thermal alarm: active low signal generated by external hardware to start the hardware clock throttling mode. may also generate an smi# or sci. thrmtrip # i thermal trip: when low, indicates that a thermal trip from the processor occurred, and corrective action will be taken. this input buffer has the same characteristics as the ferr# input buffer. slp_s3# o s3 sleep control: power plane control. shuts off power to all non- critical systems when in the s3 (suspend to ram) state. slp_s4# o s4 sleep control: power plane control. shuts power to non-critical systems when in the s4 (suspend to disk) or s5 (soft off) state. slp_s5# o s5 sleep control: power plane control. the signal is used to shut power off to all non-critical systems when in the s5 (soft off) state. pwrok i power ok: when asserted, pwrok is an indication to the intel ? 6300ESB ich that core power and pciclk have been stable for at least 1 ms. pwrok may be driven asynchronously. when pwrok is low, the intel ? 6300ESB ich asserts pxpcirst#. traditional designs have a reset button logically ored with the pwrok signal from the power supply and the processor?s voltage regulator module. when this is done with the intel ? 6300ESB ich, the pwrok_flr bit will be set. the intel ? 6300ESB ich treats this internally as though the rsmrst# signal had gone active. however, it is not treated as a full power failure. when pwrok goes inactive and then active (but rsmrst# stays high), the intel ? 6300ESB ich will reboot (regardless of the state of the afterg3 bit). when rsmrst# also goes low before pwrok goes high, then this is a full power failure and the reboot policy is controlled by the afterg3 bit. pwrok must deassert for a minimum of 100 seconds (simulation and analysis shows 3 rtc clock periods are required) in order to fully reset the core power well and properly generate the pxpcirst# output. pwrbtn# i power button: the power button will cause smi# or sci to indicate a system request to go to a sleep state. when the system is already in a sleep state, this signal will cause a wake event. when pwrbtn# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the s5 state with only the pwrbtn# available as a wake event. override will occur even when the system is in the s1-s4 states. this signal has an internal pull-up resistor. ri# i ring indicate: from the modem interface. may be enabled as a wake event, and this is preserved across power failures. sys_reset # i system reset : this pin forces an internal reset after being debounced. rsmrst# i resume well reset: used for resetting the resume power plane logic. an external rc circuit is required to ensure that the resume well power is valid prior to rsmrst# going high. note: these signals are all in the resume well, except thrm# which is in the core well; pwrok and rsmrst# which are in the rtc well.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 69 3?intel ? 6300ESB ich 3.11 cpu interface sus_stat# / lpcpd# o suspend status: this signal is asserted by the intel ? 6300ESB ich to indicate that the system will be entering a low power state soon. this may be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. it may also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. this signal is called lpcpd# on the lpc i/f. susclk o suspend clock: output of the rtc generator circuit (32.768 khz). susclk will have a duty cycle that may be as low as 30% or as high as 70%. vrmpwrg d i voltage regulator power good: not implemented in the intel ? 6300ESB ich. pull this input high to vcc. table 13. cpu interface signals (sheet 1 of 2) name type description a20m# o mask a20: a20m# will go active based on either setting the appropriate bit in the port 92h register, or based on the a20gate input being active. speed strap: during the reset sequence, the intel ? 6300ESB ich drives a20m# high when the corresponding bit is set in the freq_strp register. cpuslp# o cpu sleep: this signal puts the processor into a state that saves substantial power compared to stop-grant state. however, during that time, no snoops occur. the intel ? 6300ESB ich may optionally assert the cpuslp# signal when going to the s1 state. it will go active for all other sleep states. ferr# i numeric coprocessor error: this signal is tied to the coprocessor error signal on the processor. ferr# is only used when the intel ? 6300ESB ich coprocessor error reporting function is enabled in the general control register (d31:f0:offset d0.bit 5). when ferr# is asserted, the intel ? 6300ESB ich generates an internal irq13 to its interrupt controller unit. it is also used to gate the ignne# signal to ensure that ignne# is not asserted to the processor unless ferr# is active. ferr# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. ferr# may optionally be used in some states for notification by the processor of pending interrupt events. notes: 1. the cpu i/f signals (except rcin#, a20gate, and ferr#) are on a separate power well. this saves the external pull-up resistors that were needed on previous chipsets. 2. rcin# and a20gate, and ferr# are on in the core power well. table 12. power management interface signals (sheet 2 of 2) name type description note: these signals are all in the resume well, except thrm# which is in the core well; pwrok and rsmrst# which are in the rtc well.
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 70 order number: 300641-004us ignne# o ignore numeric error: this signal is connected to the ignore error pin on the cpu. ignne# is only used when the intel ? 6300ESB ich coprocessor error reporting function is enabled in the general control register (d31:f0:offset d0.bit 5). when ferr# is active, indicating a coprocessor error, a write to the coprocessor error register (f0h) causes the ignne# to be asserted. ignne# remains asserted until ferr# is negated. if ferr# is not asserted when the coprocessor error register is written, the ignne# signal is not asserted. init# o initialization: init# is asserted by the intel ? 6300ESB ich for 16 pci clocks to reset the processor. the intel ? 6300ESB ich may be configured to support cpu bist. in that case, init# will be active when pxpcirst# is active. intr o cpu interrupt: intr is asserted by the intel ? 6300ESB ich to signal the processor that an interrupt request is pending and needs to be serviced. it is an asynchronous output and normally driven low. nmi o non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor. the intel ? 6300ESB ich may generate an nmi when either serr# or iochk# is asserted. the processor detects an nmi when it detects a rising edge on nmi. nmi is reset by setting the corresponding nmi source enable/disable bit in the nmi status and control register. smi# o system management interrupt: smi# is an active low output synchronous to pciclk. it is asserted by the intel ? 6300ESB ich in response to one of many enabled hardware or software events. stpclk# o stop clock request: stpclk# is an active low output synchronous to pciclk. it is asserted by the intel ? 6300ESB ich in response to one of many hardware or software events. when the processor samples stpclk# asserted, it responds by stopping its internal clock. this signal will not be connected to the processor in ia64 systems, since the processor has no corresponding input signal. rcin# i keyboard controller reset cpu: the keyboard controller may generate init# to the processor. this saves the external or gate with the intel ? 6300ESB ich?s other sources of init#. when the intel ? 6300ESB ich detects the assertion of this signal, init# is generated for 16 pci clocks. note that the intel ? 6300ESB ich will ignore rcin# assertion during transitions to the s1, s3, s4 and s5 states. a20gate i a20 gate: from the keyboard controller. acts as an alternative method to force the a20m# signal active. saves the external or gate needed with various other chipsets. table 13. cpu interface signals (sheet 2 of 2) name type description notes: 1. the cpu i/f signals (except rcin#, a20gate, and ferr#) are on a separate power well. this saves the external pull-up resistors that were needed on previous chipsets. 2. rcin# and a20gate, and ferr# are on in the core power well.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 71 3?intel ? 6300ESB ich 3.12 smbus interface 3.13 system management interface 3.14 real time clock interface table 14. sm bus interface signals name type description smbdata i/od smbus data: external pull-up is required. smbclk i/od smbus clock: external pull-up is required. smbalert # / gpio[11] i smbus alert : this signal is used to wake the system or generate smi#. when not used for smbalert#, it may be used as a gpio (gpio[11]). note: the smbus i/f signals are all in the resume well. table 15. system management interface signals name type description intruder # i intruder detect: detects if the system case has been opened. may be set to disable the system when box is detected open. this signal?s status is readable, so it may be used like a gpi when the intruder switch is not needed. smlink[1: 0] i/od system management link: smbus link to optional external system management asic or lan controller. external pull-ups are required. note that smlink[0] corresponds to a smbus clock signal, and smlink[1] corresponds to a smbus data signal. note: intruder# is in the rtc well. the smlink signal is in the resume well. table 16. real time clock interface name type description rtcx1 special crystal input 1: connected to the 32.768 khz crystal. when no external crystal is used, then rtcx1 may be driven with the desired clock rate. rtcx2 special crystal input 2: connected to the 32.768 khz crystal. when no external crystal is used, then rtcx2 should be left floating. vbias i bias voltage for oscillator: sets the proper biasing for the oscillator. expected voltage 200 mv. note: an external crystal/resistor/capacitor circuit is required for proper operation of the oscillator.
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 72 order number: 300641-004us 3.15 other clocks 3.16 miscellaneous signals table 17. other clocks name type description clk14 i oscillator clock: used for 8254 timers. runs at 14.31818 mhz. this clock is permitted to stop during s3 (or lower) states in desktop configurations or s1 (or lower) states in mobile configurations. clk48 i 48 mhz clock: used to run the usb controllers. runs at 48 mhz. this clock is permitted to stop during s3 (or lower) states in desktop configurations or s1 (or lower) states in mobile configurations. hiclk i 66 mhz clock: used to run the hub interface. runs at 66 mhz. this clock is permitted to stop during s3 (or lower) states in desktop configurations or s1 (or lower) states in mobile configurations. table 18. miscellaneous signals name typ e description spkr o speaker: the spkr signal is the output of counter 2 and is internally ?anded? with port 61h bit 1 to provide speaker data enable. this signal drives an external speaker driver device, which in turn drives the system speaker. upon pxpcirst#, its output state is 0. note: spkr is sampled at the rising edge of pwrok as a functional strap. see section 3.21.1, ?functional straps? for more details. there is a weak integrated pull-down resistor on spkr pin. rtcrst# i rtc reset: when asserted, this signal resets register bits in the rtc well and sets the rtc_pwr_sts bit (bit 2 in gen_pmcon3 register). notes: 1. clearing cmos in an intel ? 6300ESB ich-based platform may be done by using a jumper on rtcrst# or gpi, or using safemode strap. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. 2. unless entering the xor chain test mode, the rtcrst# input must always be high when all other rtc power planes are on wdt_tout# / gpio[32] o watchdog timer timeout: driven active to indicate the second stage of the wdt has overflowed. this signal will toggle states for each overflow in periodic mode. in non-periodic mode, this signal will go active low and remain in this state until a system reset or power cycle. this signal is muxed with gpio[32].
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 73 3?intel ? 6300ESB ich 3.17 ac?97 link 3.18 universal asynchronous receive and transmit (uart0,1) table 19. ac?97 link signals name type description ac_rst# o ac?97 reset: master h/w reset to external codec(s). ac_sync o ac?97 sync: 48 khz fixed rate sample sync to the codec(s). ac_bit_clk i ac?97 bit clock: 12.288 mhz serial data clock generated by the external codec(s). this signal has an integrated pull-down resistor 3 . ac_sdout o ac?97 serial data out: serial tdm data output to the codec(s). ac_sdin[2:0] i ac?97 serial data in 2:0: serial tdm data input from the three codec(s). integrated pull-down resistors, which are always enabled. notes: 1. these signals are in the resume well, except ac_sync, ac_bit_clk, and ac_sdata_out, which are in the core well. 2. see section 4.2, ?integrated pull-ups and pull-downs? for details about when the integrated pull-down resistors are enabled on ac_sync, ac_bit_clk, and ac_sdata_out. 3. an integrated pull-down resistor on ac_bit_clk is enabled when either: - the aclink shutoff bit in the ac?97 global control register (see section 13.2.8, ?glob_cnt?global control register? ) is set to ?1?, or - both function 5 and function 6 of device 31 are disabled. otherwise, the integrated pull- down resistor is disabled. table 20. universal asynchronous receive and transmit (uart0, 1) (sheet 1 of 2) signal name type description uart_clk i input clock to the siu. this clock is passed to the baud clock generation logic of each uart in the siu. siu0_rxd siu1_rxd i serial inputs for uart0 and uart1: serial data input from device pin to the receive port. siu0_txd siu1_txd o serial output for uart0, 1: serial data output to the communication peripheral/modem or data set. upon reset, the txd pins will be set to marking condition (logic ?1? state). siu0_cts siu1_cts i clear to send: active low, this pin indicates that data may be exchanged between the intel ? 6300ESB ich and external interface. these pins have no effect on the transmitter. note: these pins could be used as modem status input whose condition may be tested by the processor by reading bit 4 (cts) of the modem status register (msr). bit 4 is the complement of the cts# signal. bit 0 (dcts) of the msr indicates whether the cts# input has changed state since the previous reading of the msr. when the cts bit of the msr changes state, an interrupt is generated when the modem status interrupt is enabled.
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 74 order number: 300641-004us 3.19 general purpose i/o note: alternative signal definition is for pin strap selected feature muxing. gpios muxing is based on gpio configurations. siu0_dsr siu1_dsr i data set ready for uart 0, 1: active low, this pin indicates that the external agent is ready to communicate with the intel ? 6300ESB ich uarts. these pins have no effect on the transmitter. note: these pins could be used as modem status input whose condition may be tested by the processor by reading bit 5 (dsr) of the modem status register. bit 5 is the complement of the dsr# signal. bit 1 (ddsr) of the modem status register (msr) indicates whether the dsr# input has changed state since the previous reading of the msr. when the dsr bit of the msr changes state, an interrupt is generated when the modem status interrupt is enabled. siu0_dcd siu1_dcd i data carrier detect for uart 0, 1: active low, this pin indicates that data carrier has been detected by the external agent. note: these pins are modem status input whose condition may be tested by the processor by reading bit 7 (dcd) of the modem status register (msr). bit 7 is the complement of the dcd# signal. bit 3 (ddcd) of the msr indicates whether the dcd# input has changed state since the previous reading of the msr. when the dcd bit of the msr changes state, an interrupt is generated when the modem status interrupt is enabled. siu0_ri# siu1_ri# i ring indicator for uart 0, 1: active low, this pin indicates that a telephone ringing signal has been received by the external agent. note: these pins are modem status input whose condition may be tested by the processor by reading bit 6 (ri) of the modem status register (msr). bit 6 is the complement of the ri# signal. bit 2 (teri) of the msr indicates whether the ri# input has transitioned back to an inactive state. when the ri bit of the msr changes from a 1 to 0, an interrupt is generated when the modem status interrupt is enabled. siu0_dtr# siu1_dtr# o data terminal ready for uart 0, 1: when low these pins informs the modem or data set that the intel ? 6300ESB ich uart 0, 1 are ready to establish a communication link. the dtr#x(x=0,1) output signals may be set to an active low by programming the dtrx (x-0,1) (bit0) of the modem control register to a logic ?1?. a reset operation sets this signal to its inactive state (logic ?1?). loop mode operation holds this signal in its inactive state. siu0_rts# siu1_rts# o request to send for uart 0, 1: when low these pins informs the modem or data set that the intel ? 6300ESB ich uart 0, 1are ready to establish a communication link. the rts#x, where x = 0,1, output signals may be set to an active low by programming the rts#x (bit1) of the modem control register to a logic ?1?. a reset operation sets this signal to its inactive state (logic ?1?). loop mode operation holds this signal in its inactive state. table 20. universal asynchronous receive and transmit (uart0, 1) (sheet 2 of 2) signal name type description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 75 3?intel ? 6300ESB ich table 21. general purpose i/o signals (sheet 1 of 2) signal name type description gpio[0]/ pxreq[2]# i fixed as input only. main power well. may instead be used as pxreq[2]#. gpio[1]/ pxreq[3]# i fixed as input only. main power well. may instead be used as pxreq[3]#. gpio[5:2]/ pirq[h:e]# i fixed as input only. main power well. may instead be used as pirq[h:e]#. gpio[6] i fixed as input only. main power well. (3.3 v tolerant, not 5 v tolerant) gpio[7] i fixed as input only. main power well. (3.3 v tolerant, not 5 v tolerant) gpio[8] i fixed as input only. resume power well. unmuxed. the gpi_inv bit corresponding to gpio[8] must be set in order to achieve the correct polarity in the general purpose event 0 status register. gpio[9:10] i reserved. these gpio are not implemented. gpio[11] i fixed as input only. resume power well. may instead be used for smbalert#. gpio[12:13] i fixed as input only. resume power well. gpio[14:15] i reserved. these gpio are not implemented. gpio[16] o fixed as output only. main power well. may instead be used as pxgnt[2]#. gpio[17] o fixed as output only. main power well. may instead be used as pxgnt[3]#. gpio[18] o fixed as output only. main power well. gpio[19] o fixed as output only. main power well. gpio[20] o fixed as output only. main power well. gpio[21] o fixed as output only. main power well. gpio[23] o fixed as output only. main power well. gpio[24] i/o may be input or output. resume power well. unmuxed. gpio[25] i/o may be input or output. resume power well. unmuxed. gpio[26] i/o reserved. this gpio is not implemented. gpio[27:28] i/o may be input or output. resume power well. unmuxed. gpio[29:31] o reserved. these gpio are not implemented. gpio[32] o fixed as output only. core power well. may instead be used for wdt_tout#. gpio[33:36] i/o may be input or output. core power well. may instead be used for pxirq[0:3]#. gpio[37:39] i/o may be input or output. core power well. gpio[37,39] are unmuxed. notes: 1. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 2. gpio[8:15] and gpio[24:31] are in the suspend well. 3. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 4. resume-well gpio are not 5 v tolerant. 5. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well.
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 76 order number: 300641-004us 3.20 power and ground gpio[40:43] i/o may be input or output. core power well. note: these gpios have high strength output capability (for driving leds). gpio[44:55] i/o reserved. these gpio are not implemented. gpio[56:57] od output only. resume and rtc power wells. unmuxed. gpio[58:63] i/o reserved. these gpio are not implemented. table 22. power and ground signals (sheet 1 of 2) name description vcc3_3 3.3 v supply for core well i/o buffers. this power may be shut off in s3, s4, or s5 states. vcc1_5 1.5 v supply for core well logic. this power may be shut off in s3, s4, s5 or s5 states. vcchi 1.5 v supply for hub interface 1.5 logic. this power may be shut off in s3, s4, and s5 states. v5ref reference for 5 v tolerance on core well inputs. this power may be shut off in s3, s4, s5 or g3 states. vccref 3.3v reference voltage for pci-x inputs vcca 1.5v supply for hub interface pll. this power may be shut off in s3, s4, and s5 states. hiref analog input. expected voltages are 350 mv for the hub interface 1.5 (enhanced hub interface) parallel termination. this power is shut off in s3, s4, s5 and g3 states. vccsus3_3 3.3 v supply for resume well i/o buffers. this power is not expected to be shut off unless the system is unplugged in desktop configurations. vccsus1_5 1.5 v supply for resume well logic. this power is not expected to be shut off unless the system is unplugged in desktop configurations. v5ref_sus reference for 5 v tolerance on resume well inputs. this power is not expected to be shut off unless the system is unplugged in desktop configurations. vccrtc 3.3 v (may drop to 2.0 v min. in g3 state) supply for the rtc well. this power is not expected to be shut off unless the rtc battery is removed or completely drained. note: implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. clearing cmos in an intel ? 6300ESB ich-based platform may be done by using a jumper on rtcrst# or gpi, or using safemode strap. table 21. general purpose i/o signals (sheet 2 of 2) signal name type description notes: 1. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 2. gpio[8:15] and gpio[24:31] are in the suspend well. 3. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 4. resume-well gpio are not 5 v tolerant. 5. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 77 3?intel ? 6300ESB ich 3.21 pin straps 3.21.1 functional straps the following signals are used for static configuration. they are sampled at various reset points to select configurations, and then revert later to their standard usage. to invoke the associated mode, the signal should be driven at least four pci clocks prior to the time it is sampled. note: the intel ? 6300ESB ich changes the polarity of the ?no reboot? strap in order to avoid an audible click due to the pull-up on the spkr output. vccpll 1.5 v supply for core well logic. this power may be shut off in s3, s4, s5 or g3 states. v_cpu_io powered by the same supply as the cpu i/o voltage. this supply is used to drive the cpu i/f outputs. 0.8 to 1.75 v. the power will be shut in s3, s4, and s5 states. vss shared grounds. table 22. power and ground signals (sheet 2 of 2) name description table 23. functional strap definitions signal usage when sampled comment ac_sdou t safe mode rising edge of pwrok the signal has a weak internal pull-down. when the signal is sampled high, the intel ? 6300ESB ich will set the processor speed strap pins for safe mode. refer to processor specification for speed strapping definition. the status of this strap is readable via the safe_mode bit (bit 2, d31: f0, offset d4h). siu0_dtr # a16 swap override rising edge of pwrok this signal has a weak internal pull-up. the intel ? 6300ESB ich starts driving it when pxpcirst# goes high. the status of this strap is readable via d31: f0, offset d5h, bit 5). spkr no reboot rising edge of pwrok the signal has a weak internal pull-down. when the signal is sampled high, this indicates that the system is strapped to the ?no reboot? mode (the intel ? 6300ESB ich will disable the tco timer system reboot feature). the status of this strap is readable via the no_reboot bit (bit 1, d31: f0, offset d4h).
intel ? 6300ESB ich?3 intel ? 6300ESB i/o controller hub ds november 2007 78 order number: 300641-004us 3.22 revision and device id table table 24. revision and device id table device function description device id a0 rev id a1/a2 rev id a3 rev id comments d30,f0 hub to pci bridge 244eh 08h 09h 0ah d31,f0 lpc bridge 25a1h 00h 01h 02h d31,f1 ide 25a2h 00h 01h 02h d31,f2 sata controller 25a3h 00h 01h 02h sata and raid are mutually exclusive. d31, f3 smbus controller 25a4h 00h 01h 02h d31, f5 ac?97 audio 25a6h 00h 01h 02h d31, f6 ac?97 modem 25a7h 00h 01h 02h d29, f0 usb uhci #1 25a9h 00h 01h 02h d29, f1 usb uhci #2 25aah 00h 01h 02h d29,f4 wdt 25abh 00h 01h 02h d29:f5 ioxapic 25ach 00h 01h 02h d29, f7 usb ehci 25adh 00h 01h 02h d28:f0 hub interface to pci-x bridge 25aeh 00h 01h 02h d31:f2 raid controller 25b0h 00h 01h sata and raid are mutually exclusive. note: refer to the latest intel? 6300ESB i/o controller hub specification update for the value of the revision identification registers.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 79 4?intel ? 6300ESB ich intel ? 6300ESB ich power planes and pin states 4 4.1 power planes usage model assumption: the power planes and control are shown in figure 5 . table 25. intel ? 6300ESB i/o controller hub power planes plane description main i/o (3.3 v) vcc3_3: powered by the main power supply. when the system is in the s3, s4, s5, or g3 state, this plane is assumed to be shut off. main logic (1.5 v) vcc1_5: powered by the main power supply. when the system is in the s3, s4, s5, or g3 state, this plane is assumed to be shut off. resume i/o (3.3 v standby) vccsus3_3: powered by the main power supply in s0 - s1 states. powered by the trickle power supply when the system is in the s3, s4, s5, state. assumed to be shut off only when in the g3 state (system is unplugged and ac power is not present). resume logic (1.5 v standby) vccsus1_5: powered by the main power supply in s0 - s1 states. powered by the trickle power supply when the system is in the s3, s4, s5, state. assumed to be shut off only when in the g3 state (system is unplugged and ac power is not present). cpu i/f (0.8 ~ 1.75 v) v_cpu_io: powered by the main power supply through the processor voltage regulator. when the system is in the s3, s4, s5, or g3 state, this plane is assumed to be shut off. hub interface logic (1.5 v) vcchi: powered by the main power supply. assumed to be 1.5 v. when the system is in the s3, s4, s5, or g3 state, this plane is assumed to be shut off. rtc vccrtc: when other power is available (from the main supply), external diode coupling will provide power to reduce the drain on the rtc battery. assumed to operate from 3.3 v down to 2.0 v.
intel ? 6300ESB ich?4 intel ? 6300ESB i/o controller hub ds november 2007 80 order number: 300641-004us 4.2 integrated pull-ups and pull-downs figure 5. power plane usage model table 26. integrated pull-up and pull-down resistors signal resistor type nominal value notes ac_bitclk pull-down 20k 1 ac_rst# pull-down 20k 2 ac_sdin[2:0] pull-down 20k 3 ac_sdout pull-down 20k 2 , 8 ac_sync pull-down 20k 2 , 8 dprslpvr pull-down 20k 2 ee_din pull-up 20k 3 ee_dout pull-up 20k 3 gnt[b:a]# / gnt[5]# / gpio[17:16] pull-up 20k 3 lad[3:0]# / fwh[3:0]# pull-up 20k 3 ldrq[1:0] pull-up 20k 3 pme# pull-up 20k 3 pwrbtn# pull-up 20k 3 pdd[7] / sdd[7] pull-down 11.5k 6 notes: 1. simulation data shows that these resistor values may range from 10 k to 40 k . 2. simulation data shows that these resistor values may range from 9 k to 50 k . 3. simulation data shows that these resistor values may range from 15 k to 35 k 4. simulation data shows that these resistor values may range from 7.5 k to 16 k . 5. simulation data shows that these resistor values may range from 45 k to 170 k 6. simulation data shows that these resistor values may range from 5.7 k to 28.3 k . 7. simulation data shows that these resistor values may range from 14.25 k to 24.8 k 8. the pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. atx power supply dc-dc fet switch dc-dc dc-dc core well suspend well rtc well vcc 3.3 v vaux 5 v 3.3 v 1.5 v 1.5 v 3.3 v vccrtc lithium coin cell 2.0 ? 3.0v
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 81 4?intel ? 6300ESB ich 4.3 ide integrated series termination resistors tab l e 2 7 shows the intel ? 6300ESB ich ide signals that have integrated series termination resistors. 4.4 output and i/o signals planes and states tab le 2 8 and tab l e 2 9 shows the power plane associated with the output and i/o signals, as well as the state at various times. within the table, the following terms are used: ?high-z? tri-state. the intel ? 6300ESB ich is not driving the signal high or low. ?high? the intel ? 6300ESB ich is driving the signal to a logic ?1?. ?low? the intel ? 6300ESB ich is driving the signal to a logic ?0?. ?defined? driven to a level that is defined by the function (will be high or low). ?undefined? the intel ? 6300ESB ich is driving the signal, but the value is indeterminate. ?running? clock is toggling or signal is transitioning because the function is not stopping. pddreq / sddreq pull-down 11.5k 6 spkr pull-down 20k 2 , 8 usb[3:0] [p,n] pull-down 15k 7 table 26. integrated pull-up and pull-down resistors signal resistor type nominal value notes notes: 1. simulation data shows that these resistor values may range from 10 k to 40 k . 2. simulation data shows that these resistor values may range from 9 k to 50 k . 3. simulation data shows that these resistor values may range from 15 k to 35 k 4. simulation data shows that these resistor values may range from 7.5 k to 16 k . 5. simulation data shows that these resistor values may range from 45 k to 170 k 6. simulation data shows that these resistor values may range from 5.7 k to 28.3 k . 7. simulation data shows that these resistor values may range from 14.25 k to 24.8 k 8. the pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. table 27. ide series termination resistors signal integrated series termination resistor value pdd[15:0], sdd[15:0], pdiow#, sdiow#, pdior#, pdiow#, pdreq, sdreq, pddack#, sddack#, piordy, siordy, pda[2:0], sda[2:0], pdcs1#, sdcs1#, pdcs3#, sdcs3#, irq14, irq15] approximately 33 (see note) note: simulation data indicates that the integrated series termination resistors are a nominal 33 but may range from 31 to 43 .
intel ? 6300ESB ich?4 intel ? 6300ESB i/o controller hub ds november 2007 82 order number: 300641-004us ?off? the power plane is off, so the intel ? 6300ESB ich is not driving. note: the signal levels are the same in s4 and s5.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 83 4?intel ? 6300ESB ich 4.5 power planes for input signals table 28. power plane and states for output and i/o signal for desktop configurations (sheet 1 of 7) signal name type power well resistors during reset (note 2) after reset (note 2) hub interface h1pd[7:0] i/o core internal termination see table below see table below h1pstrbs i/o core internal termination see table below see table below h1pstrbf i/o core internal termination see table below see table below h1reqm i core internal termination see table below see table below h1reqi o core internal termination see table below see table below h1stop i/o core internal termination see table below see table below h1rcomp i/o core strap pin external resistor 1 see table below see table below hlclk i core none see table below see table below h1par i/o core internal termination see table below see table below vswing i core external resistor 1 input only input only hlvref i core external resistor 1 input only input only pci-x interface pxad[63:32] i/o core external pull-up z z pxad[31:0] i/o core none z driven (0 or 1) pxc/be[7:4]# i/o core external pull-up z z pxc/be[3:0]# i/o core none z driven (0 or 1) pxdevsel# i/o core external pull-up z z pxframe# i/o core external pull-up z z pxirdy# i/o core external pull-up z z pxirq[3:0]#/ gpio[36:33] i / i/o note: 9 core external pull-up z z pxtrdy# i/o core external pull-up z z pxstop# i/o core external pull-up z z notes: 1. the intel ? 6300ESB ich sets these signals at reset for cpu frequency strap. 2. the states of main i/o signals are taken at the times during pxpcirst# and immediately after pxpcirst#. 3. the states of resume i/o signals are taken at the times during rsmrst# and immediately after rsmrst# 4. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 5. gpio[8:15] and gpio[24:31] are in the suspend well. 6. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 7. resume-well gpio are not 5 v tolerant. 8. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well. 9. pxirq[3:0] are input only, gpio[36:33] are i/o in gpio mode 10.pirq[h:e] are i/od, gpio[5:2] are input only.
intel ? 6300ESB ich?4 intel ? 6300ESB i/o controller hub ds november 2007 84 order number: 300641-004us pxpar64 i/o core external pull-up z z pxpar i/o core none z driven (0 or 1) pxperr# i/o core external pull-up z z pxreq[0]# i core external pull-up input only input only pxreq[3:2]#/ gpio[1:0] i core external pull-up input only input only pxgnt[0:1]# o core none 1 1 pxgnt[3]#/gpio[17] o core none 1 1 pxgnt[2]#/gpio[16] o core none h 1 pciclk i core none input only input only raserr# od core external pull-up 1 1 pxpcirst# o suspend none 0 1 pxplock# i/o core external pull-up z z pxserr# i/od core external pull-up z z pxreq64# i/o core external pull-up h h pxack64# i/o core external pull-up h h pxm66en i core external 10k pull up input only input only pxpcixcap i core external 10k pull up input only input only pci interface ad[31:0] i/o core none z driven (0 or 1) c/be[3:0]# i/o core none z driven (0 or 1) devsel# i/o core external pull-up z z frame# i/o core external pull-up z z irdy# i/o core external pull-up z z trdy# i/o core external pull-up z z stop# i/o core external pull-up z z par i/o core none z driven (0 or 1) perr# i/o core external pull-up z z req[3:0]# i core external pull-up input only input only gnt[3:0]# o core none i i pciclk i/o core none input only input only plock# i/o core external pull-up z z serr# i/od core external pull-up z z table 28. power plane and states for output and i/o signal for desktop configurations (sheet 2 of 7) signal name type power well resistors during reset (note 2) after reset (note 2) notes: 1. the intel ? 6300ESB ich sets these signals at reset for cpu frequency strap. 2. the states of main i/o signals are taken at the times during pxpcirst# and immediately after pxpcirst#. 3. the states of resume i/o signals are taken at the times during rsmrst# and immediately after rsmrst# 4. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 5. gpio[8:15] and gpio[24:31] are in the suspend well. 6. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 7. resume-well gpio are not 5 v tolerant. 8. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well. 9. pxirq[3:0] are input only, gpio[36:33] are i/o in gpio mode 10.pirq[h:e] are i/od, gpio[5:2] are input only.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 85 4?intel ? 6300ESB ich pme# i/od suspend internal pull-ups (15k - 35k) hh lpc interface lad[3:0] i/o core internal pull-ups (15k - 35k) hh lframe# i core internal pull-ups (15k - 35k) 11 ldrq[0]#, ldrq[1]# i/o core internal pull-ups (15k - 35k) hh usb interface usbp[3:0]p/n, i/o suspend internal pull-down and series resistors ll oc[3:0]# i suspend none input only input only usbrbiasp o suspend external pull-down (22.6 ohm +/- 1%) z 1 during periodic auto current cal usbrbiasn i suspend analog connection point for sensing the voltage across the external usbrbiasp resistor. input only input only sata interface sataclkp, sataclkn i core input only input only sata0txp, sata0txn o core h sata0rxp, sata0rxn i core input only input only sata1txp, sata1txn o core sata1rxp, sata1rxn i core input only input only sataled# od core external pull-up z z satarbiasp i core satarbiasn i core ide interface pdcs1#, sdcs1# ocore internal series resistors (21 ohms - 75 ohms) 11 pdcs3#, sdcs3# ocore internal series resistors (21 ohms - 75 ohms) 11 pda[2:0], sda[2:0] ocore internal series resistors (21 ohms - 75 ohms) driven (0 or 1) driven (0 or 1) table 28. power plane and states for output and i/o signal for desktop configurations (sheet 3 of 7) signal name type power well resistors during reset (note 2) after reset (note 2) notes: 1. the intel ? 6300ESB ich sets these signals at reset for cpu frequency strap. 2. the states of main i/o signals are taken at the times during pxpcirst# and immediately after pxpcirst#. 3. the states of resume i/o signals are taken at the times during rsmrst# and immediately after rsmrst# 4. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 5. gpio[8:15] and gpio[24:31] are in the suspend well. 6. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 7. resume-well gpio are not 5 v tolerant. 8. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well. 9. pxirq[3:0] are input only, gpio[36:33] are i/o in gpio mode 10.pirq[h:e] are i/od, gpio[5:2] are input only.
intel ? 6300ESB ich?4 intel ? 6300ESB i/o controller hub ds november 2007 86 order number: 300641-004us pdd[15:0], sdd[15:0] i/o core internal pull-downs on pdd[7] and sdd[7] (5.7k - 28.3k), internal series resistors (21 ohms - 75 ohms) l on bit 7, z on others l on bit 7, z on others pddreq, sddreq icore internal pull-downs (5.7k - 28.3k), internal series resistors (21ohms - 75 ohms) input only input only pddack#, sddack# ocore internal series resistors (21 ohms - 75 ohms) 11 pdior# / (pdwstb / prdmardy#) sdior# / (sdwstb / srdmardy#) ocore internal series resistors (21 ohms - 75 ohms) 11 pdiow# / (pdstop) sdiow# / (sdstop) ocore internal series resistors (21 ohms - 75 ohms) 11 piordy / (pdrstb / pwdmardy#) siordy / (sdrstb / swdmardy#) icore internal series resistors (21 ohms - 75 ohms) external pull-ups input only input only irq[14-15] i core internal series resistors (21 ohms - 75 ohms) external pull-ups input only input only interrupt pins serirq i/o core external pull-up z z pirq[a:d]# i core external pull-up z z pirq[e:h]# / gpio[2:5] i/od / i note: 10 core external pull-up when used as pirq zz pxirq[3:0]#/ gpio[36:33] i / i/o note: 9 core external pull-up z z ac?97 interface ac_rst# o suspend internal pull-down (9k - 50k) when aclink is shut 00 ac_sync o core strap pin internal pull-down 2 during reset (9k - 50k) l0 ac_bit_clk i core internal pull-down 2 (10k - 40k) input only input only table 28. power plane and states for output and i/o signal for desktop configurations (sheet 4 of 7) signal name type power well resistors during reset (note 2) after reset (note 2) notes: 1. the intel ? 6300ESB ich sets these signals at reset for cpu frequency strap. 2. the states of main i/o signals are taken at the times during pxpcirst# and immediately after pxpcirst#. 3. the states of resume i/o signals are taken at the times during rsmrst# and immediately after rsmrst# 4. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 5. gpio[8:15] and gpio[24:31] are in the suspend well. 6. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 7. resume-well gpio are not 5 v tolerant. 8. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well. 9. pxirq[3:0] are input only, gpio[36:33] are i/o in gpio mode 10.pirq[h:e] are i/od, gpio[5:2] are input only.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 87 4?intel ? 6300ESB ich ac_sdata_out o core strap pin internal pull-down 2 (9k - 50k) l0 ac_sdata_in[2:0] i/o suspend internal pull-down (9k - 50k) l power management pins thrm# i core none input only input only thrmtrip# i cpu i/o none input only input only slp_s3# o suspend none 0 1 slp_s4# o suspend none 0 1 slp_s5# o suspend none 0 1 sys_reset# i suspend none input only input only pwrok i rtc none input only input only pwrbtn# i suspend internal pull-up (15k - 35k) h h ri# i suspend none input only input only rsmrst# i rtc none input only input only sus_stat# o suspend none 0 1 after pwrok rises susclk o suspend none 0 toggling vrmpwrgd i core none input only input only cpu interface pins a20m# o cpu i/o none 0 (before pwrok rising) 1 cpuslp# o cpu i/o none 1 1 ferr# i cpu i/o external pull-up input only input only ignne# o cpu i/o none 0 (before pwrok rising) 1 init# o cpu i/o none 1 1 intr o cpu i/o none 0 (before pwrok rising) 0 nmi o cpu i/o none 0 (before pwrok rising) 0 smi# o cpu i/o none 1 1 stpclk# o cpu i/o none 1 1 table 28. power plane and states for output and i/o signal for desktop configurations (sheet 5 of 7) signal name type power well resistors during reset (note 2) after reset (note 2) notes: 1. the intel ? 6300ESB ich sets these signals at reset for cpu frequency strap. 2. the states of main i/o signals are taken at the times during pxpcirst# and immediately after pxpcirst#. 3. the states of resume i/o signals are taken at the times during rsmrst# and immediately after rsmrst# 4. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 5. gpio[8:15] and gpio[24:31] are in the suspend well. 6. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 7. resume-well gpio are not 5 v tolerant. 8. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well. 9. pxirq[3:0] are input only, gpio[36:33] are i/o in gpio mode 10.pirq[h:e] are i/od, gpio[5:2] are input only.
intel ? 6300ESB ich?4 intel ? 6300ESB i/o controller hub ds november 2007 88 order number: 300641-004us rcin# i core dependent upon the driving agent. external pull-up when open-drain. input only input only a20gate i core dependent upon the driving agent. external pull-up when open-drain. input only input only smbus and system management pins smbdata i/od suspend external pull-up z z smbclk i/od suspend external pull-up z z smbalert#/ gpio[11] i suspend external pull-up (for smbalert#) input only input only intruder# i rtc none input only input only smlink[1:0] i/od suspend external pull-ups z z real time clock pins rtcx1 special rtc none analog input analog input rtcx2 special rtc none analog input analog input vbias i rtc none analog input analog input miscellaneous pins and gpio clk14 i core none input only input only clk48 i core none input only input only spkr o core strap pin internal pull-down (9k - 50k) l0 rtcrst# i rtc external rc circuit input only input only wdt_tout#/ gpio[32] o / i/o core none 1 1 gpio[13:12],[8] i suspend none input only input only gpio[7:6] i core internal pull-up 1 input only gpio[20:18] o core none 1 1 until driven gpio[21] o core none 0 1 gpio[23] o core none 0 0 until driven gpio[25:24] i/o suspend none 1 1 gpio[27:28] i/o suspend none 1 1 table 28. power plane and states for output and i/o signal for desktop configurations (sheet 6 of 7) signal name type power well resistors during reset (note 2) after reset (note 2) notes: 1. the intel ? 6300ESB ich sets these signals at reset for cpu frequency strap. 2. the states of main i/o signals are taken at the times during pxpcirst# and immediately after pxpcirst#. 3. the states of resume i/o signals are taken at the times during rsmrst# and immediately after rsmrst# 4. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 5. gpio[8:15] and gpio[24:31] are in the suspend well. 6. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 7. resume-well gpio are not 5 v tolerant. 8. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well. 9. pxirq[3:0] are input only, gpio[36:33] are i/o in gpio mode 10.pirq[h:e] are i/od, gpio[5:2] are input only.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 89 4?intel ? 6300ESB ich tab l e 2 9 shows the power plane associated with each input signal, as well as what device drives the signal at various times. valid states include: ? high ? low ? static: will be high or low, but will not change ? driven: will be high or low, and is allowed to change ? running: for input clocks gpio[43:37] i/o core none 0 0 until driven gpio[57:56] od rtc/ suspend external pull up driven (0 or 1) driven (0 or 1) siu interface uart_clk i core none input only input only siu0_rxd i core none input only input only siu1_rxd i/o core internal pull-up (15k - 35k) h h siu0_txd i/o core none 1 1 siu1_txd i/o core internal pull-up (15k - 35k) h 1 siu0_cts# i core none input only input only siu1_cts# i/o core internal pull-up (15k - 35k) h h siu0_dsr# i core none input only input only siu1_dsr# i/o core internal pull-up (15k - 35k) h h siu0_dcd# i core none input only input only siu1_dcd# i/o core internal pull-up (15k - 35k) h h siu0_ri# i core none input only input only siu1_ri# i/o core internal pull-up (15k - 35k) h h siu0_dtr# o core internal pull-up (15k - 35k) 1 1 siu1_dtr# i/o core internal pull-up (15k - 35k) h 1 siu0_rts# o core none 1 1 siu1_rts# i/o core internal pull-up (15k - 35k) h 1 table 28. power plane and states for output and i/o signal for desktop configurations (sheet 7 of 7) signal name type power well resistors during reset (note 2) after reset (note 2) notes: 1. the intel ? 6300ESB ich sets these signals at reset for cpu frequency strap. 2. the states of main i/o signals are taken at the times during pxpcirst# and immediately after pxpcirst#. 3. the states of resume i/o signals are taken at the times during rsmrst# and immediately after rsmrst# 4. gpio[0:7], gpio[16:21, 23], and gpio[32:55] are in the core well. 5. gpio[8:15] and gpio[24:31] are in the suspend well. 6. core-well gpio are 5 v tolerant, except for gpio[7:6] and [32:43]. 7. resume-well gpio are not 5 v tolerant. 8. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well. 9. pxirq[3:0] are input only, gpio[36:33] are i/o in gpio mode 10.pirq[h:e] are i/od, gpio[5:2] are input only.
intel ? 6300ESB ich?4 intel ? 6300ESB i/o controller hub ds november 2007 90 order number: 300641-004us table 29. power plane for input signals for desktop configurations signal name power well driver during reset s1 s3 s5 a20gate main i/o external microcontroller static low low ac_bit_clk main i/o ac?97 codec low low low ac_sdin[2:0] resume i/o ac?97 codec low low low apicclk main i/o clock generator running low low clk14 main i/o clock generator running low low clk48 main i/o clock generator running low low clk66 main logic clock generator running low low ferr# cpu i/o cpu static low low intruder# rtc external switch driven driven driven irq[15:14] main i/o ide static low low ldrq[0]# main i/o lpc devices high low low ldrq[1]# main i/o lpc devices high low low oc[5:0]# resume i/o external pull-ups driven driven driven pciclk main i/o clock generator running low low pddreq main i/o ide device static low low piordy main i/o ide device static low low pme# resume i/o internal pull-up driven driven driven pwrbtn# resume i/o internal pull-up driven driven driven pwrok rtc system power supply driven low low rcin# main i/o external microcontroller high low low req[0:5]# main i/o pci master driven low low req[b:a]# main i/o pc/pci devices driven low low ri# resume i/o serial port buffer driven driven driven rsmrst# rtc external rc circuit high high high rtcrst# rtc external rc circuit high high high sddreq main i/o ide drive static low low serr# main i/o pci bus peripherals high low low siordy main i/o ide drive static low low smbalert# resume i/o external pull-up driven driven driven sys_reset# resume i/o external circuit driven driven driven thrm# main i/o thermal sensor driven low low thrmtrip# cpu i/o thermal sensor driven low low usbrbias# resume i/o external pull-down driven driven driven
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 91 5?intel ? 6300ESB ich functional description 5 5.1 hub interface to pci bridge (d30:f0) the hub interface to pci bridge resides in pci device 30, function 0 on bus #0. this portion of the intel ? 6300ESB ich implements the buffering and control logic between pci and the hub interface. the arbitration for the pci bus is handled by this pci device. the pci decoder in this device must decode the ranges for the hub interface. all register contents will be lost when core well power is removed. 5.1.1 pci bus interface the intel ? 6300ESB ich pci interface provides a 33 mhz, pci local bus specification, rev. 2.2-compliant implementation. all pci signals are 5 v tolerant. the intel ? 6300ESB ich integrates a pci arbiter that supports up to four external pci bus masters in addition to the internal intel ? 6300ESB ich requests. most transactions targeted to the intel ? 6300ESB ich will first appear on the external pci bus before being claimed back by the intel ? 6300ESB ich. the exceptions are i/o cycles involving usb, ide, and ac?97. these transactions will complete over the hub interface without appearing on the external pci bus. configuration cycles targeting usb, ide or ac?97 will appear on the pci bus. when the intel ? 6300ESB ich is programmed for positive decode, the intel ? 6300ESB ich w ill claim the cycles appearing on the external pci bus in medium decode time. when the intel ? 6300ESB ich is programmed for subtractive decode, the intel ? 6300ESB ich w ill claim these cycles in subtractive time. when the intel ? 6300ESB ich is programmed for subtractive decode, these cycles may be claimed by another positive decode agent out on pci. this architecture enables the ability to boot off of a pci card that positively decodes the boot cycles. in order to boot off a pci card it is necessary to keep the intel ? 6300ESB ich in subtractive decode mode. when booting off a pci card, the boot_sts bit (bit 2, tco2 status register) will be set. when the processor issues a locked cycle to a resource that is too slow (e.g., pci), the intel ? 6300ESB ich will not allow upstream requests to be performed until the cycle completion. this may be critical for isochronous buses which assume certain timing for their data flow, such as ac?97 or usb. devices on these buses may suffer from underrun when the asynchronous traffic is too heavy. underrun means that the same data is sent over the bus while the intel ? 6300ESB ich is not able to issue a request for the next data. snoop cycles are not permitted while the processor side bus is locked. locked cycles are assumed to be rare. locks by pci targets are assumed to exist for a short duration (a few microseconds at most). when a system has a very large number of locked cycles and some that are very long, then the system will definitely experience underruns and overruns. the units most likely to have problems are the ac?97 controller and the usb controllers. other units could get underruns/overruns, but are much less likely. the ide controller (due to its stalling capability on the cable) should not get any underruns or overruns. note: the intel ? 6300ESB ich?s ac?97, ide and usb controllers cannot perform peer-to-peer traffic. note: poor performing pci devices that cause long latencies (numerous retries) to processor- to-pci locked cycles may starve isochronous transfers between usb or ac?97 devices
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 92 order number: 300641-004us and memory. this will result in overrun or underrun, causing reduced quality of the isochronous data, such as audio. note: pci configuration write cycles, initiated by the processor, with the following characteristics will be converted to a special cycle with the shutdown message type. ? device number (ad[15:11]) = ?11111 ? function number (ad[10:8]) = ?111? ? register number (ad[7:2]) = ?000000? ? data = 00h ? bus number matches secondary bus number 5.1.2 pci-to-pci bridge model from a software perspective, the intel ? 6300ESB ich contains a pci-to-pci bridge. this bridge connects the hub interface to the pci bus. by using the pci-to-pci bridge software model, the intel ? 6300ESB ich may have its decode ranges programmed by existing plug-and-play software such that pci ranges do not conflict with agp and graphics aperture ranges in the host controller. 5.1.3 idsel to device number mapping when addressing devices on the external pci bus (with the pci slots) the intel ? 6300ESB ich will assert one address signal as an idsel. when accessing device 0, the intel ? 6300ESB ich will assert ad16. when accessing device 1, the intel ? 6300ESB ich will assert ad17. this mapping continues all the way up to device 15 where the intel ? 6300ESB ich asserts ad31. note that the intel ? 6300ESB ich?s internal functions (ac?97, ide, usb, and pci bridge) are enumerated like they are on a separate pci bus (the hub interface) from the external pci bus. 5.1.4 serr# functionality there are several internal and external sources that may cause serr#. the intel ? 6300ESB ich may be programmed to cause an nmi based on detecting that an serr# condition has occurred. the nmi may also be routed to instead cause an smi#. note: note that the intel ? 6300ESB ich does not drive the external pci bus serr# signal active onto the pci bus. the external serr# signal is an input into the intel ? 6300ESB ich driven only by external pci devices. the conceptual logic diagrams in figure 6 and figure 7 illustrate all sources of serr#, along with their respective enable and status bits. figure 8 shows how the intel ? 6300ESB ich error reporting logic is configured for nmi# generation.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 93 5?intel ? 6300ESB ich figure 6. primary device status register error reporting logic and and and or or and and and and and and and or and d28: 04h.6 hl parity error d28: 3eh.0 px parity error d28: (3eh.11) dtse dtt_en d28: 3eh.1 pci-x serr pin (d28:04h.8) px_serr#_enable rx target abort serr_rta_en (d30:90h.2) serr_rta (d30:92h.2) serr# enable (d30:3eh.1) legacy pci serr signal delayed transaction timeout p_serr_en (d30:04h.8) serr_en (d30:04h.8) pci address parity error pre-latch p_sse (to t-unit) master abort mode (d30:3eh.5) hl-to-pci posted write master aborts serr_en (d30:04h.8) d30:3eh.0 d30:3eh.1 p_sse (d30:06h.14) and serr_dtt_en (d30.3eh.1) hl-to-pci-x posted write master aborts master abort mode (d28.3eh.5) and sse for pci-x (d28:06h.14)
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 94 order number: 300641-004us figure 7. secondary status register error reporting logic s_sse (d31:f0.06h.14) pre-latch s_sse (to t-unit) or and serr_dtt_en (d31:88h.1) and serr_rta_en (d31:88h.2) received target abort serr# enable (d31:f0.04h.8) south pci delayed transaction timeout and iochk# v ia serirq receive do_serr message from hl mchserr_ sts (tcobase+04h .b it 12) error fro m xl-unit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 95 5?intel ? 6300ESB ich 5.1.5 parity error detection the intel ? 6300ESB ich may detect and report different parity errors in the system. the intel ? 6300ESB ich may be programmed to cause an nmi (or smi# when nmi is routed to smi#) based on detecting a parity error. the conceptual logic diagram in figure 8 details all the parity errors that the intel ? 6300ESB ich may detect, along with their respective enable bits, status bits, and the results. note: the intel ? 6300ESB ich does not escalate a data parity mismatch reported by a pci device (perr#) across the p2p bridge. note: when nmis are enabled, and parity error checking on pci is also enabled, then parity errors will cause an nmi. some operating systems will not attempt to recover from this nmi, since it considers the detection of a pci error to be a catastrophic event. figure 8. nmi# generation logic a9644-01 and and or or and and to nmi# output and gating logic iochk from serirq logic port 61.3 s_sse for pci-x pre-latch s_sse pre-latch p_sse hublink parity error detected d30_p_per (d30:04h.6) pci parity error detected d30_s_per (d30:3eh.0) south pci parity error detected d31_s_per (d31:04h.6) pre-latch usbe_sse tconmi_sts port 70:7 iochk_nmi_sts (port 61.6) serr_nmi_sts (port 61.7) d30_pdpd (d30:06h:8) d30_sdpd (d30:1eh:8) pci_serr_sts (port 61.2) and pci-x perr_pin (d28:3e.0) and d29:f7:06h.14 d31_dpt (d31:06h.8) puserr_nmi and or
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 96 order number: 300641-004us 5.1.6 standard pci bus configuration mechanism the pci bus defines a slot based ?configuration space? that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechanism implemented within the intel ? 6300ESB ich. the intel ? 6300ESB ich only supports mechanism #1 as defined in the pci specification. configuration cycles for pci bus #0 devices #2 through #31, and for pci bus numbers greater than 0 will be sent towards the intel ? 6300ESB ich from the host controller. the intel ? 6300ESB ich compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its p2p bridge to determine when the configuration cycle is meant for primary pci or a downstream pci bus. 5.1.6.1 type 0 to type 0 forwarding when a type 0 configuration cycle is received on hub interface to any function other than usb ehci or ac?97, the intel ? 6300ESB ich forwards these cycles to pci and then reclaims them. the intel ? 6300ESB ich uses address bits ad[15:13] to communicate the intel ? 6300ESB ich device numbers in type 0 configuration cycles. when the type 0 cycle on hub interface specifies any device number other than 29, 30 or 31, the intel ? 6300ESB ich will not set any address bits in the range ad[31:11] during the corresponding transaction on pci. tab le 3 0 shows the device number translation. the intel ? 6300ESB ich logic will generate single d-word configuration read and write cycles on the pci bus. the intel ? 6300ESB ich will generate a type 0 configuration cycle for configurations to the bus number matching the pci bus. when the cycle is targeting a device behind an external bridge, the intel ? 6300ESB ich will run a type 1 cycle on the pci bus. 5.1.6.2 type 1 to type 0 conversion when the bus number for the type 1 configuration cycle matches the pci (secondary) bus number, the intel ? 6300ESB ich will convert the address as follows: 1. for device numbers 0 through 15, only one bit of the pci address [31:16] will be set. when the device number is 0, ad[16] is set; when the device number is 1, ad[17] is set; etc. 2. the intel ? 6300ESB ich will always drive 0s on bits ad[15:11] when converting type 1 configurations cycles to type 0 configuration cycles on pci. 3. address bits [10:1] will also be passed unchanged to pci. 4. address bit [0] will be changed to ?0?. table 30. type 0 configuration cycle device number translation device # in hub interface type 0 cycle ad[31:11] during address phase of type 0 cycle on pci 0 through 28 0000000000000000_00000b 29 0000000000000000_00100b 30 0000000000000000_01000b 31 0000000000000000_10000b
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 97 5?intel ? 6300ESB ich 5.1.7 pci dual address cycle (dac) support the intel ? 6300ESB ich supports dac format on pci for cycles from pci initiators to main memory. this allows pci masters to generate an address up to 44 bits. the size of the actual supported memory space will be determined by the memory controller and the processor. the dac mode is only supported for pci adapters and usb ehci, and is not supported for any of the internal pci masters (ide, usb uhci, ac?97, 8237 dma, etc.). when a pci master wants to initiate a cycle with an address above 4g, it follows the following behavioral rules (see pci local bus specification, revision 2.2, section 3.9 for more details): 1. on the first clock of the cycle (when frame# is first active), the peripheral uses the dac encoding on the c/be# signals. this unique encoding is: 1101. 2. also during the first clock, the peripheral drives the ad[31:0] signals with the low address. 3. on the second clock, the peripheral drives ad[31:0] with the high address. the address is right justified: a[43:32] appear on ad[12:0]. the value of ad[31:13] is expected to be 0, however the intel ? 6300ESB ich will ignore these bits. c/be# indicate the bus command type (memory read, memory write, etc.) 4. the rest of the cycle proceeds normally. 5.2 lpc bridge (with system and management functions) (d31:f0) the lpc bridge function of the intel ? 6300ESB ich resides in pci device 31:function 0. in addition to the lpc bridge function, d31:f0 contains other functional units including dma, interrupt controllers, timers, power management, system management, gpio, and rtc.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 98 order number: 300641-004us 5.2.1 lpc cycle types the intel ? 6300ESB ich implements all of the cycle types described in the low pin count interface specification, revision 1.0. tab le 3 1 shows the cycle types supported by the intel ? 6300ESB ich. 5.2.1.1 start field definition table 31. lpc cycle types supported cycle type comment memory read single: 1 byte only 1 memory write single: 1 byte only 1 i/o read 1 byte only. the intel ? 6300ESB ich breaks up 16 and 32-bit processor cycles into multiple 8-bit transfers. i/o write 1 byte only. the intel ? 6300ESB ich breaks up 16 and 32-bit processor cycles into multiple 8-bit transfers. dma read may be 1, or 2 bytes dma write may be 1, or 2 bytes bus master read may be 1, 2, or 4 bytes. 2 bus master write may be 1, 2, or 4 bytes. 2 notes: 1. for memory cycles below 16m which do not target enabled fwh ranges, the intel ? 6300ESB ich will perform standard lpc memory cycles. it will only attempt 8-bit transfers. when the cycle appears on pci as a 16-bit transfer, it will appear as two consecutive 8-bit transfers on lpc. likewise, when the cycle appears as a 32-bit transfer on pci, it will appear as four consecutive 8-bit transfers on lpc. when the cycle is not claimed by any peripheral, it will be subsequently aborted, and the intel ? 6300ESB ich will return a value of all 1s to the processor. this is done to maintain compatibility with isa memory cycles where pull-up resistors would keep the bus high when no device responds. 2. bus master read or write cycles must be naturally aligned. for example, a 1-byte transfer may be to any address. however, the 2-byte transfer must be word aligned (i.e.,with an address where a0=0). a dword transfer must be dword aligned (i.e., with an address where a1and a0 are both 0). table 32. start field bit definitions bits[3:0] encoding definition 0000 start of cycle for a generic target. 0010 grant for bus master 0. 0011 grant for bus master 1. 1101 start of cycle for firmware memory read cycle 1110 start of cycle for firmware memory write cycle 1111 stop/abort: end of a cycle for a target. note: all other encodings are reserved.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 99 5?intel ? 6300ESB ich 5.2.1.2 cycle type/direction (cyctype + dir) the intel ? 6300ESB ich will always drive bit 0 of this field to zero. peripherals running bus master cycles must also drive bit 0 to 0. the following table shows the valid bit encodings: 5.2.1.3 size bits[3:2] are reserved. the intel ? 6300ESB ich will always drive them to 00. peripherals running bus master cycles are also supposed to drive 00 for bits 3:2, however, the intel ? 6300ESB ich will ignore those bits. bits[1:0] are encoded as follows: 5.2.1.4 sync valid values for the sync field are: table 33. cycle type bit definitions bits[3:2 ] bit[1] definition 00 0 i/o read 00 1 i/o write 01 0 memory read 01 1 memory write 10 0 dma read 10 1 dma write 11 x reserved. when a peripheral performing a bus master cycle generates this value, the intel ? 6300ESB ich will abort the cycle. table 34. transfer size bit definition bits[1:0] size 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) 10 reserved. the intel ? 6300ESB ich will never drive this combination. when a peripheral running a bus master cycle drives this combination, the intel ? 6300ESB ich may abort the transfer. 11 32-bit transfer (4 bytes) table 35. sync bit definition (sheet 1 of 2) bits[3:0] indication 0000 ready: sync achieved with no error. for dma transfers, this also indicates dma request deassertion and no more transfers desired for that channel. 0101 short wait: part indicating wait-states. for bus master cycles, the intel ? 6300ESB ich will not use this encoding. it will instead use the long wait encoding (see next encoding below). note: all other combinations are reserved.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 100 order number: 300641-004us 5.2.1.5 sync time-out there are several error cases that may occur on the lpc i/f. the following table indicates the failing case and the intel ? 6300ESB ich response: there may be other peripheral failure conditions, however these are not handled by the intel ? 6300ESB ich. 5.2.1.6 sync error indication the sync protocol allows the peripheral to report an error through the lad[3:0] = ?1010b? encoding. the intent of this encoding is to give peripherals a method of communicating errors to aid higher layers with more robust error recovery. when the intel ? 6300ESB ich is reading data from a peripheral, data will still be transferred in the next two nibbles. this data may be invalid, but it must be transferred by the peripheral. when the intel ? 6300ESB ich is writing data to the peripheral, the data had already been transferred. in the case of multiple byte cycles, such as for memory and dma cycles, an error sync terminates the cycle. therefore, when the intel ? 6300ESB ich is transferring four bytes from a device, and if the device returns the error sync in the first byte, the other three bytes will not be transferred. 0110 long wait: part indicating wait-states, and many wait-states will be added. this encoding driven by the intel ? 6300ESB ich for bus master cycles, rather than the short wait (0101). 1001 ready more (used only by peripheral for dma cycle): sync achieved with no error and more dma transfers desired to continue after this transfer. this value is valid only on dma transfers and is not allowed for any other type of cycle. 1010 error: sync achieved with error. this is generally used to replace the serr# or iochk# signal on the pci/isa bus. it indicates that the data is to be transferred, but there is a serious error in this transfer. for dma transfers, this not only indicates an error, but also indicates dma request deassertion and no more transfers desired for that channel. table 35. sync bit definition (sheet 2 of 2) bits[3:0] indication note: all other combinations are reserved. table 36. response to sync failures possible sync failure intel ? 6300ESB ich response intel ? 6300ESB ich starts a memory, i/o, or dma cycle, but no device drives a valid sync after 4 consecutive clocks. this could occur when the processor tries to access an i/o location to which no device is mapped. intel ? 6300ESB ich aborts the cycle after the fourth clock. intel ? 6300ESB ich drives a memory, i/o, or dma cycle, and a peripheral drives more than 8 consecutive valid sync to insert wait- states using the short (?0101b?) encoding for sync. this could occur when the peripheral is not operating properly. continues waiting intel ? 6300ESB ich starts a memory, i/o, or dma cycle, and a peripheral drives an invalid sync pattern. this could occur when the peripheral is not operating properly or when there is excessive noise on the lpc i/f. intel ? 6300ESB ich aborts the cycle when the invalid sync is recognized.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 101 5?intel ? 6300ESB ich upon recognizing the sync field indicating an error, the intel ? 6300ESB ich w ill treat this the same as iochk# going active on the isa bus. 5.2.1.7 lframe# usage start of cycle for memory, i/o, and dma cycles, the intel ? 6300ESB ich will assert lframe# for one clock at the beginning of the cycle ( figure 9 ) during that clock, the intel ? 6300ESB ich will drive lad[3:0] with the proper start field. abort mechanism when performing an abort, the intel ? 6300ESB ich will drive lframe# active for four consecutive clocks. on the fourth clock, it will drive lad[3:0] to ?1111b?. the intel ? 6300ESB ich will perform an abort for the following cases (possible failure cases): ? intel ? 6300ESB ich starts a memory, i/o, or dma cycle, but no device drives a valid sync after four consecutive clocks. ? intel ? 6300ESB ich starts a memory, i/o, or dma cycle, and the peripheral drives an invalid sync pattern. ? a peripheral drives an illegal address when performing bus master cycles. ? a peripheral drives an invalid value. figure 9. typical timing for lframe# lframe# start lclk lad[3:0] cyctype addr start dir & size tar sync data tar 1 - 8 clocks 2 clocks 1 - n clocks 2 clocks 2 clocks 1 clock 1 clock figure 10. abort mechanism lframe# start lclk lad[3:0] cyctype addr dir & size tar sync peripheral must stop driving too many syncs causes timeout chipset will drive high
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 102 order number: 300641-004us 5.2.1.8 i/o cycles for i/o cycles targeting registers specified in the intel ? 6300ESB ich?s decode ranges, the intel ? 6300ESB ich performs i/o cycles as defined in the lpc spec. these will be 8-bit transfers. when the processor attempts a 16-bit or 32-bit transfer, the intel ? 6300ESB ich will break the cycle up into multiple 8-bit transfers to consecutive i/o addresses. note: when the cycle is not claimed by any peripheral (and subsequently aborted), the intel ? 6300ESB ich will return a value of all ones (ffh) to the processor. this is to maintain compatibility with isa i/o cycles where pull-up resistors would keep the bus high when no device responds. 5.2.1.9 bus master cycles the intel ? 6300ESB ich supports bus master cycles and requests (using ldrq#) as defined in the lpc specification. the intel ? 6300ESB ich has two ldrq# inputs, and thus supports two separate bus master devices. it uses the associated start fields for bus master 0 (?0010b?) or bus master 1 (?0011b?). note: the intel ? 6300ESB ich does not support lpc bus masters performing i/o cycles. lpc bus masters should only perform memory read or memory write cycles. 5.2.1.10 lpc power management lpcpd# protocol same timings as for sus_stat#. upon driving sus_stat# low, lpc peripherals will drive ldrq# low or tri-state it. the intel ? 6300ESB ich w ill shut off the ldrq# input buffers. after driving sus_stat# active, the intel ? 6300ESB ich drives lframe# low, and tri-states (or drive low) lad[3:0]. the intel ? 6300ESB ich does not follow one part of the lpc spec that says ?lreset# is always asserted after lpcpd#?. the exception is the s1-m state. in that case, lpcpd# (susstat#) will go active, but lreset# (pxpcirst#) will not go active. 5.2.1.11 configuration and intel ? 6300ESB ich implications lpc i/f decoders in order to allow the i/o cycles and memory mapped cycles to go to the lpc i/f, the intel ? 6300ESB ich includes several decoders. during configuration, the intel ? 6300ESB ich must be programmed with the same decode ranges as the peripheral. the decoders are programmed through the device 31:function 0 configuration space. note: the intel ? 6300ESB ich cannot accept pci write cycles from pci-to-pci bridges or devices with similar characteristics (specifically those with a ?retry read? feature which is enabled) to an lpc device when there is an outstanding lpc read cycle towards the same pci device or bridge. these cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 103 5?intel ? 6300ESB ich bus master device mapping and start fields bus masters must have a unique start field. in the case of the intel ? 6300ESB ich, which supports two lpc bus masters, it will drive 0010 for the start field for grants to bus master #0 (requested through ldrq[0]#) and 0011 for grants to bus master #1 (requested through ldrq[1]#.). thus no registers are needed to config the start fields for a particular bus master. bios mapping and start fields to reduce decoding logic in the fwh, the intel ? 6300ESB ich will use a unique idsel field for each eprom. to do this, the intel ? 6300ESB ich has configuration registers to assign a particular bios range to a particular idsel field. 5.3 dma operation (d31:f0) 5.3.1 dma overview the intel ? 6300ESB ich supports lpc dma through lpc, similar to isa dma. the dma controller has registers that are fixed in the lower 64 kbyte of i/o space. the dma controller is configured using registers in the pci config space. these registers allow configuration of individual channels for use by lpc dma. the dma circuitry incorporates the functionality of two 8237 dma controllers with seven independently programmable channels ( figure 11 ). dma controller 1 (dma-1) corresponds to dma channels 0-3 and dma controller 2 (dma-2) corresponds to channels 5-7. dma channel 4 is used to cascade the two controllers and will default to cascade mode in the dma channel mode (dcm) register. channel 4 is not available for any other purpose. in addition to accepting requests from dma slaves, the dma controller also responds to requests that software initiates. software may initiate a dma service request by setting any bit in the dma channel request register to 1. each dma channel is hardwired to the compatible settings for dma device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. the intel ? 6300ESB ich provides 24-bit addressing in compliance with the isa- compatible specification. each channel includes a 16-bit isa-compatible current register which holds the 16 least-significant bits of the 24-bit address, an isa- compatible page register which contains the eight next most significant bits of address. the dma controller also features refresh address generation, and autoinitialization following a dma termination. figure 11. intel ? 6300ESB ich dma controller channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 dma-1 dma-2
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 104 order number: 300641-004us 5.3.2 channel priority for priority resolution, the dma consists of two logical channel groups: channels 0?3 and channels 4?7. each group may be in either fixed or rotate mode, as determined by the dma command register. see section 8.2, ?dma i/o registers? for more information. dma i/o slaves normally assert their dreq line to arbitrate for dma service. however, a software request for dma service may be presented through each channel's dma request register. a software request is subject to the same prioritization as any hardware request. please see section 8.4.9, ?ocw3?operational control word 3 register? for detailed register description for request register programming information in the dma i/o register ( section 8.2, ?dma i/o registers? ). 5.3.2.1 fixed priority the initial fixed priority structure is as described in ta b le 37 . the fixed priority ordering is zero through seven. in this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. channels [3:0] of dma-1 assume the priority position of channel 4 in dma-2, thus taking priority over channels 5, 6, and 7. 5.3.2.2 rotating priority rotation allows for ?fairness? in priority resolution. the priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0?3, 5?7). channels 0?3 rotate as a group of four. they are always placed between channel 5 and channel 7 in the priority list. channel 5?7 rotate as part of a group of four. that is, channels (5?7) form the first three positions in the rotation, while channel group (0?3) comprises the fourth position in the arbitration. 5.3.3 address compatibility mode whenever the dma is operating, the addresses do not increment or decrement through the high and low page registers. therefore, when a 24-bit address is 01ffffh and increments, the next address will be 010000h, not 020000h. similarly, when a 24-bit address is 020000h and decrements, the next address will be 02ffffh, not 01ffffh. however, when the dma is operating in 16 bit mode, the addresses still do not increment or decrement through the high and low page registers but the page boundary is now 128k. therefore, if a 24 bit address is 01fffeh and increments, the next address will be 000000h, not 010000h. similarly, if a 24 bit address is 020000h and decrements, the next address will be 03fffeh, not 02fffeh. this is compatible with the 8237 and page register implementation used in the pc-at. this mode is set after cpurst is valid. table 37. fixed priority high priority.....low priority (0, 1, 2, 3) (5, 6, 7)
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 105 5?intel ? 6300ESB ich 5.3.4 summary of dma transfer sizes tab l e 3 9 lists each of the dma device transfer sizes. the column labeled ?current byte/ word count register? indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. the column labeled ?current address increment/decrement? indicates the number added to or taken from the current address register after each dma transfer cycle. the dma channel mode register determines when the current address register will be incremented or decremented. 5.3.4.1 address shifting when programmed for 16-bit i/o count by words the intel ? 6300ESB ich maintains compatibility with the implementation of the dma in the pc-at which used the 8237. the dma shifts the addresses for transfers to/from a 16-bit device count-by-words. note that the least significant bit of the low page register is dropped in 16-bit shifted mode. when programming the current address register (when the dma channel is in this mode), the current address must be programmed to an even address with the address value shifted right by one bit. the address shifting is described in ta b l e 3 9 . 5.3.5 autoinitialize by programming a bit in the dma channel mode register, a channel may be set up as an autoinitialize channel. when a channel undergoes autoinitialization, the original values of the current page, current address and current byte/word count registers are automatically restored from the base page, address, and byte/word count registers of that channel following tc. the base registers are loaded simultaneously with the current registers by the microprocessor when the dma channel is programmed and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize. following autoinitialize, the channel is ready to perform another dma service, without processor intervention, as soon as a valid dreq is detected. table 38. dma transfer size dma device date size and word count current byte/word count register current address increment/ decrement 8-bit i/o, count by bytes bytes 1 16-bit i/o, count by words (address shifted) words 1 table 39. address shifting in 16-bit i/o dma transfers output address 8-bit i/o programmed address (ch 0?3) 16-bit i/o programmed address (ch 5?7) (shifted) a0 a[16:1] a[23:17] a0 a[16:1] a[23:17] 0 a[15:0] a[23:17] note: the least significant bit of the page register is dropped in 16-bit shifted mode.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 106 order number: 300641-004us 5.3.6 software commands there are three additional special software commands that the dma controller may execute. the three software commands are: 1. clear byte pointer flip-flop 2. master clear 3. clear mask register they do not depend on any specific bit pattern on the data bus. 5.3.6.1 clear byte pointer flip-flop this command is executed prior to writing or reading new address or word count information to/from the dma controller. this initializes the flip-flop to a known state so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence. when the host processor is reading or writing dma registers, two byte pointer flip-flops are used; one for channels 0?3 and one for channels 4?7. both of these act independently. there are separate software commands for clearing each of them (0ch for channels 0?3, 0d8h for channels 4?7). 5.3.6.2 dma master clear this software instruction has the same effect as the hardware reset. the command, status, request, and internal first/last flip-flop registers are cleared and the mask register is set. the dma controller will enter the idle cycle. there are two independent master clear commands; 0dh which acts on channels 0?3, and 0dah which acts on channels 4?7. 5.3.6.3 clear mask register this command clears the mask bits of all four channels, enabling them to accept dma requests. i/o port 00eh is used for channels 0?3 and i/o port 0dch is used for channels 4?7. 5.4 lpc dma dma on lpc is handled through the use of the ldrq# lines from peripherals and special encodings on lad[3:0] from the host. single, demand, verify, and increment modes are supported on the lpc interface. channels 0 ? 3 are 8 bit channels. channels 5 ? 7 are 16-bit channels. channel 4 is reserved as a generic bus master request. 5.4.1 asserting dma requests peripherals that need dma service encode their requested channel number on the ldrq# signal. to simplify the protocol, each peripheral on the lpc i/f has its own dedicated ldrq# signal (they may not be shared between two separate peripherals). the intel ? 6300ESB ich has two ldrq# inputs, allowing at least two devices to support dma or bus mastering.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 107 5?intel ? 6300ESB ich ldrq# is synchronous with lclk (pci clock). as shown in figure 12 the peripheral uses the following serial encoding sequence: ? peripheral starts the sequence by asserting ldrq# low (start bit). ldrq# is high during idle conditions. ? the next 3 bits contain the encoded dma channel number (msb first). ? the next bit (act) indicates whether the request for the indicated dma channel is active or inactive. the act bit will be a 1 (high) to indicate when it is active and 0 (low) when it is inactive. the case where act is low will be rare, and is only used to indicate that a previous request for that channel is being abandoned. ? after the active/inactive indication, the ldrq# signal must go high for at least 1 clock. after that one clock, ldrq# signal may be brought low to the next encoding sequence. when another dma channel also needs to request a transfer, another sequence may be sent on ldrq#. for example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral may send the encoded request for channel 3. this allows multiple dma agents behind an i/o device to request use of the lpc interface, and the i/o device does not need to self-arbitrate before sending the message. 5.4.2 abandoning dma requests dma requests may be deasserted in two fashions: on error conditions by sending an ldrq# message with the ?act? bit set to ?0?, or normally through a sync field during the dma transfer. this section describes boundary conditions where the dma request needs to be removed prior to a data transfer. there may be some special cases where the peripheral desires to abandon a dma transfer. the most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its fifo, or software stopping a device prematurely. in these cases, the peripheral wishes to stop further dma activity. it may do so by sending an ldrq# message with the act bit as ?0?. however, since the dma request was seen by the intel ? 6300ESB ich, there is no ensuring that the cycle has not been granted and will shortly run on lpc. therefore, peripherals must take into account that a dma cycle may still occur. the peripheral may choose not to respond to this cycle, in which case the host will abort it, or it may choose to complete the cycle normally with any random data. this method of dma deassertion should be prevented whenever possible, to limit boundary conditions both on the intel ? 6300ESB ich and the peripheral. figure 12. dma request assertion through ldrq# start msb lsb act start lclk ldrq#
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 108 order number: 300641-004us 5.4.3 general flow of dma transfers arbitration for dma channels is performed through the 8237 within the host. once the host has won arbitration on behalf of a dma channel assigned to lpc, it asserts lframe# on the lpc i/f and begins the dma transfer. the general flow for a basic dma transfer is as follows: 1. the intel ? 6300ESB ich starts transfer by asserting ?0000b? on lad[3:0] with lframe# asserted. 2. the intel ? 6300ESB ich asserts ?cycle type? of dma, direction based on dma transfer direction. 3. the intel ? 6300ESB ich asserts channel number and, when applicable, terminal count. 4. the intel ? 6300ESB ich indicates the size of the transfer: 8 or 16 bits. 5. when a dma read? ?the intel ? 6300ESB ich drives the first 8 bits of data and turns the bus around. ? the peripheral acknowledges the data with a valid sync. ? when a 16 bit transfer, the process is repeated for the next 8 bits. 6. when a dma write? ?the intel ? 6300ESB ich turns the bus around and waits for data. ? the peripheral indicates data ready through sync and transfers the first byte. ? when a 16 bit transfer, the peripheral indicates data ready and transfers the next byte. 7. the peripheral turns around the bus. 5.4.4 terminal count (tc) terminal count is communicated through lad[3] on the same clock that dma channel is communicated on lad[2:0]. this field is the channel field. terminal count indicates the last byte of transfer, based upon the size of the transfer. for example, on an eight bit transfer size (size field is ?00b?), when the tc bit is set, this is the last byte. on a 16 bit transfer (size field is ?01b?), when the tc bit is set, the second byte is the last byte. the peripheral, therefore, must internalize the tc bit when the channel field is communicated, and only signal tc when the last byte of that transfer size has been transferred. 5.4.5 verify mode verify mode is supported on the lpc interface. a verify transfer to the peripheral is similar to a dma write, where the peripheral is transferring data to main memory. the indication from the host is the same as a dma write, so the peripheral will be driving data onto the lpc interface. however, the host will not transfer this data into main memory. 5.4.6 dma request deassertion an end of transfer is communicated to the intel ? 6300ESB ich through a special sync field transmitted by the peripheral. an lpc device must not attempt to signal the end of a transfer by deasserting ldreq#. when a dma transfer is several bytes, such as a transfer from a demand mode device, the intel ? 6300ESB ich needs to know when to deassert the dma request based on the data currently being transferred.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 109 5?intel ? 6300ESB ich the dma agent uses a sync encoding on each byte of data being transferred, which indicates to the intel ? 6300ESB ich whether this is the last byte of transfer or when more bytes are requested. to indicate the last byte of transfer, the peripheral uses a sync value of ?0000b? (ready with no error), or ?1010b? (ready with error). these encodings tell the intel ? 6300ESB ich that this is the last piece of data transferred on a dma read (intel ? 6300ESB ich to peripheral), or the byte which follows is the last piece of data transferred on a dma write (peripheral to the intel ? 6300ESB ich). when the intel ? 6300ESB ich sees one of these two encodings, it ends the dma transfer after this byte and deasserts the dma request to the 8237. therefore, when the intel ? 6300ESB ich indicated a 16 bit transfer, the peripheral may end the transfer after one byte by indicating a sync value of ?0000b? or ?1010b?. the intel ? 6300ESB ich will not attempt to transfer the second byte, and will deassert the dma request internally. this also holds true for any byte in a 32 bit transfer. this allows the peripheral, therefore, to terminate a dma burst. when the peripheral indicates a ?0000b? or ?1010b? sync pattern on the last byte of the indicated size, then the intel ? 6300ESB ich will only deassert the dma request to the 8237 since it does not need to end the transfer. when the peripheral wishes to keep the dma request active, it uses a sync value of ?1001b? (ready plus more data). this tells the 8237 that more data bytes are requested after the current byte has been transferred, so the intel ? 6300ESB ich will keep the dma request active to the 8237. therefore, on an 8-bit transfer size, when the peripheral indicates a sync value of ?1001b? to the intel ? 6300ESB ich, the data will be transferred and the dma request will remain active to the 8237. at a later time, the intel ? 6300ESB ich will then come back with another start ? cyctype ? channel ? size etc. combination to initiate another transfer to the peripheral. the peripheral must not assume that the next start indication from the intel ? 6300ESB ich is another grant to the peripheral when it had indicated a sync value of ?1001b?. on a single mode dma device, the 8237 will rearbitrate after every transfer. only demand mode dma devices may be ensured that they will receive the next start indication from the intel ? 6300ESB ich. note: indicating a ?0000b? or ?1010b? encoding on the sync field of an odd byte of a 16 bit channel (first byte of a 16 bit transfer) is an error condition. note: the host will stop the transfer on the lpc bus as indicated, fill the upper byte with random data on dma writes (peripheral to memory), and indicate to the 8237 that the dma transfer occurred, incrementing the 8237?s address and decrementing its byte count. 5.4.7 sync field/ldrq# rules since dma transfers on lpc are requested through an ldrq# assertion message, and are ended through a sync field during the dma transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a dma channel. the peripheral must not assert another message for eight lclks after a deassertion is indicated through the sync field. this is needed to allow the 8237, which typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it may arbitrate to the next agent. under default operation, the host will only perform 8-bit transfers on 8-bit channels and 16-bit transfers on 16 bit channels. the method by which this communication between host and peripheral through system bios is performed is beyond the scope of this specification. since the lpc host and lpc peripheral are motherboard devices, no ?plug-n-play? registry is required.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 110 order number: 300641-004us the peripheral must not assume that the host will be able to perform transfer sizes that are larger than the size allowed for the dma channel, and be willing to accept a size field that is smaller than what it may currently have buffered. to that end, it is recommended that future devices which may appear on the lpc bus, which require higher bandwidth than 8-bit or 16-bit dma allow, do so with a bus mastering interface and not rely on the 8237. 5.5 8254 timers (d31:f0) the intel ? 6300ESB ich contains three counters which have fixed uses. all registers and functions associated with the 8254 timers are in the core well. the 8254 unit is clocked by a 14.31818 mhz clock. the 14.31818 mhz clock will stop during the s3-s5 and g3 states. 5.5.1 counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value one counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches zero. it then reloads the initial count value and again decrements the initial count value by two each counter period. the counter then asserts irq0 when the count value reaches zero, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0. 5.5.2 counter 1, refresh request signal prior to ich1, typically in isa platforms, this counter provided the refresh request signal. today, it is still typically programmed for mode 2 operation and only impacts the period of the ref_toggle bit in port 61. the initial count value is loaded one counter period after being written to the counter i/o address. the ref_toggle bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. programming the counter to anything other than mode 2 will result in undefined behavior for the ref_toggle bit. see section 8.7.1, ?nmi_sc?nmi status and control register? (d31:f0:61h:bit 4) for ref_toggle bit details. 5.5.3 counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h (see section 8.7.1, ?nmi_sc?nmi status and control register? for more information). 5.5.4 timer programming the counter/timers are programmed in the following fashion:
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 111 5?intel ? 6300ESB ich 1. write a control word to select a counter. 2. write an initial count for that counter. 3. load the least and/or most significant bytes (as required by control word bits 5, 4) of the 16-bit counter. see section 8.3, ?timer i/o registers? for more information. 4. repeat with other counters. only two conventions need to be observed when programming the counters. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). a new initial count may be written to a counter at any time without affecting the counter's programmed mode. counting will be affected as described in the mode definitions. the new count must follow the programmed count format. when a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. the control word register at port 43h controls the operation of all three counters. several commands are available: ? control word command. specifies which counter to read or write, the operating mode, and the count format (binary or bcd). ? counter latch command. latches the current count so that it may be read by the system. the countdown process continues. ? read back command. reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. tab l e 4 0 lists the six operating modes for the interval counters. 5.5.5 reading from the interval timer it is often desirable to read the value of a counter without disturbing the count in progress. there are three methods for reading the counters: a simple read operation, counter latch command, and the read-back command. each is explained below. table 40. counter operating modes mode function description 0 out signal on end of count (=0) output is ?0?. when count goes to 0, output goes to ?1? and stays at ?1? until counter is reprogrammed. 1 hardware retriggerable one-shot output is ?0?. when count goes to 0, output goes to ?1? for one clock period. 2 rate generator (divide by n counter) output is ?1?. output goes to ?0? for one clock time, then back to ?1? and counter is reloaded. 3square wave output output is ?1?. output goes to ?0? when counter rolls over, and counter is reloaded. output goes to ?1? when counter rolls over, and counter is reloaded, etc. 4 software triggered strobe output is ?1?. output goes to ?0? when count expires for one clock period. 5 hardware triggered strobe output is ?1?. output goes to ?0? when count expires for one clock period.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 112 order number: 300641-004us with the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, when the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other. read, write, or programming operations for other counters may be inserted between them. 5.5.5.1 simple read the first method is to perform a simple read operation. the counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). note: performing a direct read from the counter will not return a determinate value, because the counting process is asynchronous to read operations. however, in the case of counter 2, the count may be stopped by writing to the gate bit in port 61h. 5.5.5.2 counter latch command the counter latch command, written to port 43h, latches the count of a specific counter at the time the command is received. this command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. the count value is then read from each counter's count register as was programmed by the control register. the count is held in the latch until it is read or the counter is reprogrammed. the count is then unlatched. this allows reading the contents of the counters on the fly without affecting counting in progress. multiple counter latch commands may be used to latch more than one counter. counter latch commands do not affect the programmed mode of the counter in any way. when a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the first counter latch command was issued.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 113 5?intel ? 6300ESB ich 5.5.5.3 read back command the read back command, written to port 43h, latches the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the value of the counter and its status may then be read by i/o access to the counter address. the read back command may be used to latch multiple counter outputs at one time. this single command is functionally equivalent to several counter latch commands, one for each counter latched. each counter's latched count is held until it is read or reprogrammed. once read, a counter is unlatched. the other counters remain latched until they are read. when multiple count read back commands are issued to the same counter without reading the count, all but the first are ignored. the read back command may additionally be used to latch status information of selected counters. the status of a counter is accessed by a read from that counter's i/ o port address. when multiple counter status latch operations are performed without reading the status, all but the first are ignored. both count and status of the selected counters may be latched simultaneously. this is functionally the same as issuing two consecutive, separate read back commands. when multiple count and/or status read back commands are issued to the same counters without any intervening reads, all but the first are ignored. when both count and status of a counter are latched, the first read operation from that counter will return the latched status, regardless of which was latched first. the next one or two reads, depending on whether the counter is programmed for one or two type counts, return the latched count. subsequent reads return unlatched count. 5.6 8259 interrupt controllers (pic) (d31:f0) the intel ? 6300ESB ich incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the isa compatible interrupts. these interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, ide, mouse, and dma channels. in addition, this interrupt controller may support the pci based interrupts, by mapping the pci interrupt onto the compatible isa interrupt line. each 8259 core supports eight interrupts, numbered zero through seven. ta b le 4 1 shows how the cores are connected. . table 41. interrupt controller core connections (sheet 1 of 2) 8259 8259 input typical interrupt source connected pin / function master 0 internal internal timer / counter 0 output / mmt #0 1 keyboard irq1 via serirq 2 internal slave controller intr output 3 serial port a irq3 via serirq, pirqx 4 serial port b irq4 via serirq, pirqx 5 parallel port / generic irq5 via serirq, pirqx 6 floppy disk irq6 via serirq pirqx, 7 parallel port / generic irq7 via serirq pirqx,
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 114 order number: 300641-004us the intel ? 6300ESB ich cascades the slave controller onto the master controller through master controller interrupt input two. this means there are only 15 possible interrupts for the intel ? 6300ESB ich pic. interrupts may individually be programmed to be edge or level, except for irq0, irq2 and irq8#. note that previous piixn devices internally latched irq12 and irq1 and required a port 60h read to clear the latch. the intel ? 6300ESB ich may be programmed to latch irq12 or irq1 (see bit 11 and bit 12 in general control register, d31:f0, offset d0h). 5.6.1 interrupt handling 5.6.1.1 generating interrupts the pic interrupt sequence involves three bits, from the irr, isr, and imr, for each interrupt level. these bits are used to determine the interrupt vector returned, and status of any other pending interrupts. ta b l e 4 2 defines the irr, isr and imr. slave 0 internal real time clock internal rtc / mmt #1 1 generic irq9 via serirq, sci or tco, pirqx, boot interrupt 2 generic irq10 via serirq, sci, or tco, pirqx 3 generic irq11 via serirq, sci, or tco, pirqx, multimedia timer #2 4 ps/2 mouse irq12 via serir, sci, or tco, pirqx 5 internal state machine output based on processor ferr# assertion. see section 5.8.4, ?specific interrupts not supported via serirq? for more information. 6primary ide cable irq14 from input signal (primary ide in legacy mode only) or via serirq pirqx 7 secondary ide cable irq15 from input signal (secondary ide in legacy mode only) or via serirq, pirqx table 41. interrupt controller core connections (sheet 2 of 2) 8259 8259 input typical interrupt source connected pin / function table 42. interrupt status registers bit description irr interrupt request register. this bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. this bit is set whether or not the interrupt is masked. however, a masked interrupt will not generate intr. isr interrupt service register. this bit is set, and the corresponding irr bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. imr interrupt mask register. this bit determines whether an interrupt is masked. masked interrupts will not generate intr.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 115 5?intel ? 6300ESB ich 5.6.1.2 acknowledging interrupts the processor generates an interrupt acknowledge cycle which is translated by the host bridge into a pci interrupt acknowledge cycle to the intel ? 6300ESB ich. the pic translates this command into two internal inta# pulses expected by the 8259 cores. the pic uses the first internal inta# pulse to freeze the state of the interrupts for priority resolution. on the second inta# pulse, the master or slave will send the interrupt vector to the processor with the acknowledged interrupt code. this code is based upon bits [7:3] of the corresponding icw2 register, combined with three bits representing the interrupt within that controller. 5.6.1.3 hardware/software interrupt sequence 1. one or more of the interrupt request lines (irq) are raised high in edge mode, or seen high in level mode, setting the corresponding irr bit. 2. the pic sends intr active to the processor when an asserted interrupt is not masked. 3. the processor acknowledges the intr and responds with an interrupt acknowledge cycle. the cycle is translated into a pci interrupt acknowledge cycle by the host bridge. this command is broadcast over pci by the intel ? 6300ESB ich. 4. upon observing its own interrupt acknowledge cycle on pci, the intel ? 6300ESB ich converts it into the two cycles that the internal 8259 pair may respond to. each cycle appears as an interrupt acknowledge pulse on the internal inta# pin of the cascaded interrupt controllers. 5. upon receiving the first internally generated inta# pulse, the highest priority isr bit is set and the corresponding irr bit is reset. on the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. the slave controller uses these bits to determine when it must respond with an interrupt vector during the second inta# pulse. 6. upon receiving the second internally generated inta# pulse, the pic returns the interrupt vector. when no interrupt request is present because the request was too short in duration, the pic will return vector 7 from the master controller. 7. this completes the interrupt cycle. in aeoi mode the isr bit is reset at the end of the second inta# pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. 5.6.2 initialization command words (icwx) before operation may begin, each 8259 must be initialized. in the intel ? 6300ESB ich, this is a four byte sequence. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. table 43. content of interrupt vector byte master, slave interrupt bits [7:3] bits [2:0] irq7,15 icw2[7:3] 111 irq6,14 110 irq5,13 101 irq4,12 100 irq3,11 011 irq2,10 010 irq1,9 001 irq0,8 000
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 116 order number: 300641-004us the base address for each 8259 initialization command word is a fixed location in the i/ o memory space: 20h for the master controller, and a0h for the slave controller. 5.6.2.1 icw1 an i/o write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to icw1. upon sensing this write, the intel ? 6300ESB ich pic expects three more byte writes to 21h for the master controller, or a1h for the slave controller, to complete the icw sequence. a write to icw1 starts the initialization sequence during which the following automatically occur: 1. following initialization, an interrupt request (irq) input must make a low-to-high transition to generate an interrupt. 2. the interrupt mask register is cleared. 3. irq7 input is assigned priority 7. 4. the slave mode address is set to 7. 5. special mask mode is cleared and status read is set to irr. 5.6.2.2 icw2 the second write in the sequence, icw2, is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. a different base is selected for each interrupt controller. 5.6.2.3 icw3 the third write in the sequence, icw3, has a different meaning for each controller. ? for the master controller, icw3 is used to indicate which irq input line is used to cascade the slave controller. within the intel ? 6300ESB ich, irq2 is used. therefore, bit 2 of icw3 on the master controller is set to a 1, and the other bits are set to 0s. ? for the slave controller, icw3 is the slave identification code used during an interrupt acknowledge cycle. on interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller when the cascaded interrupt won arbitration on the master controller. the slave controller compares this identification code to the value stored in its icw3, and when it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 5.6.2.4 icw4 the final write in the sequence, icw4, must be programmed both controllers. at the very least, bit 0 must be set to one to indicate that the controllers are operating in an intel ? architecture-based system. 5.6.3 operation command words (ocw) these command words reprogram the interrupt controller to operate in various interrupt modes. ? ocw1 masks and unmasks interrupt lines. ? ocw2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the eoi function.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 117 5?intel ? 6300ESB ich ? ocw3 is sets up isr/irr reads, enables/disables the special mask mode (smm), and enables/disables polled interrupt mode. 5.6.4 modes of operation 5.6.4.1 fully nested mode in this mode, interrupt requests are ordered in priority from zero through seven, with zero being the highest. when an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. additionally, the isr for the interrupt is set. this isr bit remains set until: the processor issues an eoi command immediately before returning from the service routine; or when in aeoi mode, on the trailing edge of the second inta#. while the isr bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels will generate another interrupt. interrupt priorities may be changed in the rotating priority mode. 5.6.4.2 special fully-nested mode this mode will be used in the case of a system where cascading is used, and the priority has to be conserved within each slave. in this case, the special fully-nested mode will be programmed to the master controller. this mode is similar to the fully- nested mode with the following exceptions: ? when an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave will be recognized by the master and will initiate interrupts to the processor. in the normal-nested mode, a slave is masked out when its request is in service. ? when exiting the interrupt service routine, software has to check whether the interrupt serviced was the only one from that slave. this is done by sending a non- specific eoi command to the slave and then reading its isr. when it is zero, a non- specific eoi may also be sent to the master. 5.6.4.3 automatic rotation mode (equal priority devices) in some applications, there are a number of interrupting devices of equal priority. automatic rotation mode provides for a sequential 8-way rotation. in this mode, a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt will have to wait until each of seven other devices are serviced at most once. there are two ways to accomplish automatic rotation using ocw2; the rotation on non-specific eoi command (r=1, sl=0, eoi=1) and the rotate in automatic eoi mode which is set by (r=1, sl=0, eoi=0). 5.6.4.4 specific rotation mode (specific priority) software may change interrupt priorities by programming the bottom priority. for example, when irq5 is programmed as the bottom priority device, irq6 will be the highest priority device. the set priority command is issued in ocw2 to accomplish this, where: r=1, sl=1, and lo-l2 is the binary priority level code of the bottom priority device.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 118 order number: 300641-004us in this mode, internal status is updated by software control during ocw2. however, it is independent of the eoi command. priority changes may be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r=1, sl=1, eoi=1 and lo-l2=irq level to receive bottom priority. 5.6.4.5 poll mode poll mode may be used to conserve space in the interrupt vector table. multiple interrupts that may be serviced by one interrupt service routine do not need separate vectors when the service routine uses the poll command. poll mode may also be used to expand the number of interrupts. the polling interrupt service routine may call the appropriate service routine, instead of providing the interrupt vectors in the vector table. in this mode, the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, disabling its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p=1 in ocw3. the pic treats its next i/o read as an interrupt acknowledge, sets the appropriate isr bit when there is a request, and reads the priority level. interrupts are frozen from the ocw3 write to the i/o read. the byte returned during the i/o read will contain a ?1? in bit 7 when there is an interrupt, and the binary code of the highest priority level in bits 2:0. 5.6.4.6 cascade mode the pic in the intel ? 6300ESB ich has one master 8259 and one slave 8259 cascaded onto the master through irq2. this configuration may handle up to 15 separate priority levels. the master controls the slaves through a three bit internal bus. in the intel ? 6300ESB ich, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. an eoi command must be issued twice: once for the master and once for the slave. 5.6.4.7 edge and level triggered mode in isa systems this mode is programmed using bit 3 in icw1, which sets level or edge for the entire controller. in the intel ? 6300ESB ich, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. this is the edge/level control registers elcr1 and elcr2. when an elcr bit is ?0?, an interrupt request will be recognized by a low to high transition on the corresponding irq input. the irq input may remain high without generating another interrupt. when an elcr bit is ?1?, an interrupt request will be recognized by a high level on the corresponding irq input and there is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first internal inta#. when the irq input goes inactive before this time, a default irq7 vector will be returned. 5.6.4.8 end of interrupt operations an eoi may occur in one of two fashions: by a command word write issued to the pic before returning from a service routine, the eoi command; or automatically when aeoi bit in icw4 is set to one.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 119 5?intel ? 6300ESB ich 5.6.4.9 normal end of interrupt in normal eoi, software writes an eoi command before leaving the interrupt service routine to mark the interrupt as completed. there are two forms of eoi commands: specific and non-specific. when a non-specific eoi command is issued, the pic will clear the highest isr bit of those that are set to one. non-specific eoi is the normal mode of operation of the pic within the intel ? 6300ESB ich, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. when the pic is operated in modes which preserve the fully nested structure, software may determine which isr bit to clear by issuing a specific eoi. an isr bit that is masked will not be cleared by a non-specific eoi when the pic is in the special mask mode. an eoi command must be issued for both the master and slave controller. 5.6.4.10 automatic end of interrupt mode in this mode, the pic will automatically perform a non-specific eoi operation at the trailing edge of the last interrupt acknowledge pulse. from a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single pic. the aeoi mode may only be used in the master controller and not the slave controller. 5.6.5 masking interrupts 5.6.5.1 masking on an individual interrupt request each interrupt request may be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr masks one interrupt channel. masking irq2 on the master controller will mask all requests for service from the slave controller. 5.6.5.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. for example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. the special mask mode enables all interrupts not masked by a bit set in the mask register. normally, when an interrupt service routine acknowledges an interrupt without issuing an eoi to clear the isr bit, the interrupt controller inhibits all lower priority requests. in the special mask mode, any interrupts may be selectively enabled by loading the mask register with the appropriate pattern. the special mask mode is set by ocw3 where: ssmm=1, smm=1, and cleared where ssmm=1, smm=0. 5.6.6 steering pci interrupts the intel ? 6300ESB ich may be programmed to allow pirqa#-pirqh# to be internally routed to interrupts 3-7, 9-12, 14 or 15. the assignment is programmable through the pirqx route control registers, located at 60-63h and 68-6bh in function 0. one or more pirqx# lines may be routed to the same irqx input. when interrupt steering is not required, the route registers may be programmed to disable steering. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a pci board to share a single line across the connector. when a pirqx# is routed to specified irq line, software must change the irq's corresponding elcr bit to level
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 120 order number: 300641-004us sensitive mode. the intel ? 6300ESB ich will internally invert the pirqx# line to send an active high level to the pic. when a pci interrupt is routed onto the pic, the selected irq may no longer be used by an isa device (through serirq). however, active low non-isa interrupts may share their interrupt with pci interrupts. internal sources of the pirqs, including sci and tco interrupts, cause the external pirq to be asserted. the intel ? 6300ESB ich receives the pirq input, like all of the other external sources, and routes it accordingly. 5.6.7 special handling of irq1 and irq12 irq1 and irq12 interrupts are treated in a slightly different fashion from other interrupts in the system. in a legacy pc environment, these interrupts were not held active until serviced, but rather pulsed whenever a key or button was pressed. in newer systems, this pulsing is no longer done. however, the intel ? 6300ESB ich must still handle old keyboard controllers which perform the pulse operation. therefore, the intel ? 6300ESB ich contains logic which may sample and hold these interrupts when so required. two register bits in configuration register d0h in function 0 enable the latching of irq1 and 12. irq1 may optionally be latched through bit 12, and irq12 may optionally be latched through bit 11. when these bits are set, the corresponding interrupt is held to the 8259 until an i/o read from port 60 is seen. the port 60 read is an indication to the keyboard controller that the interrupt has been serviced. another item to note is that on previous components (ichx), it was always ensured that the keyboard controller would exist behind the intel ? 6300ESB ich on the isa bus. on intel ? 6300ESB ich, this is not the case. therefore, the clearing of the latch must be done through a snoop of port 60h. the waveform which performs this snoop is shown in figure 13 . note that the signal which indicates that a port 60 read occurred is only one pci clock wide. this cannot be a handshake signal because the intel ? 6300ESB ich is not necessarily responding to the cycle. figure 13. port 60 read clearing irq1 and irq12 latch 60 data 2 e 0ns 50ns 100ns 150ns 200ns 250ns 3 pciclk ad c/be# frame# irdy# trdy# port60read
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 121 5?intel ? 6300ESB ich 5.7 advanced interrupt controller (apic) (d29:f5) there are two apics in the intel ? 6300ESB ich: apic0 and apic1 (device 29, function 5). apic0?s direct registers are assigned with base address fec0xxxxh; however, only primary (legacy) pci devices can write to these registers. apic1?s direct register are assigned with base address fec1xxxxh. to support legacy devices/drivers on the pci-x segment used with the intel ichx, apic1 has an alternate base address fec0xxxxh. this means devices on the pci-x segment can only write to the irq pin assertion register (either fec0_0020h or fec1_0020h) to generate an interrupt from apic1. apic1 writes to addresses fec1_0020 to fec1_0027 are claimed by apic1 from pci-x. devices on the primary pci bus can write to irq pin assertion register fec0_0020h to generate an apic0 interrupt. devices/drivers on the pci-x segment have write access only to the apic1 irq pin assertion register. devices/drivers on the pci segment can access only apic0 registers. since the intel ? 6300ESB ich does not implement hub interface eoi special cycles, the mch will translate eoi special cycle to a memory write cycle to eoi register at address fec0_0040h and passes it to the intel ? 6300ESB ich. this memory write cycle will be passed to both apic0 and apic1 internally. from the cpu/mch point of view, it should always use address fec0xxxxh to access apic0 registers and address fec1xxxxh to access apic1 registers. apic1 will not respond to cpu/mcu?s access to address fec0xxxxh, other than the eoi cycle stated above. 5.7.1 interrupt handling the i/o apic handles interrupts very differently than the 8259. briefly, these differences are: ? method of interrupt transmission. interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. the intel? 6300ESB ich only supports fsb delivery of interrupts. ? interrupt priority. the priority of interrupts in the i/o apic is independent of the interrupt number. for example, interrupt 10 may be given a higher priority than interrupt 3. ? more interrupts. the i/o apic in the intel ? 6300ESB ich supports a total of 24 interrupts. ? multiple interrupt controllers. the i/o apic interrupt transmission protocol has an arbitration phase, which allows for multiple i/o apics in the system with their own interrupt vectors. the intel ? 6300ESB ich i/o apic must arbitrate for the apic bus before transmitting its interrupt message. 5.7.2 smi/nmi/init/extint delivery modes these delivery modes are not supported by the intel ? 6300ESB ich for the following reasons: nmi/init: this signal has issues with delivery under power management. it cannot be delivered while the processor is in the stop grant state. in addition, this is a break event for power management. breaking on the apic bus message is more difficult than breaking on the pin. smi: on the 82093, the i/o apic could deliver the smi through the pin smiout# or as an apic bus message. when the message was masked by the os, then the smiout# will be used. in other words, there is no way to block the delivery of the smi#, except through bios. adding this interrupt to the i/o apic only increases validation time.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 122 order number: 300641-004us 5.7.3 boot interrupt the intel ? 6300ESB ich?s apic1 contains a capability to logically or several of its interrupt inputs together to generate a single interrupt through pic. this is necessary for systems that do not support the apic, and for boot. the generated interrupt is routed to irq 9. this interrupt is generated when the following conditions met: ? boot interrupt is enabled in configuration register. ? any of pxirq[3:0] or internal interrupt source is asserted. ? boot interrupts are not masked in redirection table. (refer to bit 16 in the redirection table) ? irq9 of pic is enabled with bit 6 set to 0 of the etr1- extended features register, d:31:f0:offset f4h,bit 6 or pirqg# is assigned to an enabled irqx of the pic with etr1 bit 6 set to 1. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. to support this function, all internal interrupt sources to apic1 are level trigger, active low signals immediately after reset.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 123 5?intel ? 6300ESB ich 5.7.4 interrupt mapping only level-triggered interrupts can be shared. pci interrupts (pirqs and pxirqs) are inherently shared on the board; these should, therefore, be programmed as level- triggered. the following tables show the mapping of the various interrupts in non-apic and apic modes. there are two apics within the intel ? 6300ESB ich supporting 24 apic interrupts each. apic0 and apic1 (device 29 function 5). apic0 supports pci messages interrupt from external device. each interrupt has its own unique vector assigned by software. the interrupt vectors are mapped as follows. table 44. interrupt mapping in non-apic non-apic mode irq # via serirq direct from pin internal modules 0 no no 8254 counter 0, mmt#0 1yesno 2 no no 8259 #2 cascade only 3yesnooption for pirqx 4yesnooption for pirqx 5yesnooption for pirqx 6yesnooption for pirqx 7yesnooption for pirqx 8 no no rtc, mmt#1 9 yes no option for pirqx, sci, tco, boot interrupt 10 yes no option for pirqx, sci, tco 11 yes no option for pirqx, sci, tco, mmt #2 12 yes no option for pirqx 13 no no ferr# logic 14 yes yes 3 pirqx, storage (ide/sata) primary (legacy mode) 15 yes yes 3 pirqx, storage (ide/sata) secondary (legacy mode) notes: 1. if an interrupt is used for boot interrupt, pci irq[a:h], sci, or tco, it should not be used for isa-style interrupts (via serirq or irq14/15 pins). irq9 will be default to boot interrupt. 2. in non-apic mode, the pci interrupts are mapped to irq3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15. 3. irq 14 and 15 can only be driven directly from the pins when in legacy ide mode. 4. if irq11 is used for mmt #2, software should ensure irq 11 is not shared with any other devices to ensure the proper operation of mmt #2. the intel ? 6300ESB ich does not prevent sharing of irq 11. 5. sw: boot interrupt may optionally be routed to pirqg# output for programmable pirqx# mapping.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 124 order number: 300641-004us 5.7.5 apic bus functional description table 45. apic interrupt mapping, apic0 agent irq # via serirq direct from pin via pci message internal modules 0 no no no cascade from 8259 #1 1 yes no no 2 2 no no no 8254 counter 0, mmt #0 (legacy mode) 3 yes no no 2 4 yes no no 2 5 yes no no 2 6 yes no no 2 7 yes no no 2 8no no nortc, mmt #1 (legacy mode) 9 yes no no 2 option for sci, tco 10 yes no no 2 option for sci, tco 11 yes no no 2 option for sci, tco, mmt #2 12 yes no no 2 13 no no no ferr# logic 14 yes yes 1 no 2 storage (ide/sata) primary (legacy mode) 15 yes yes 1 no 2 storage (ide/sata) secondary (legacy mode) 16 pirq[a]# pirq[a]# no usb1 uhci controller #1 17 pirq[b]# pirq[b]# no ac?97 audio, modem, option for smbus 18 pirq[c]# pirq[c]# no storage (ide/sata) native mode 19 pirq[d]# pirq[d]# no usb 1.0 uhci controller #2 20 n/a pirq[e]# no 2 option for sci, tco, mmt #0,1,2 21 n/a pirq[f]# no 2 option for sci, tco, mmt #0,1,2 22 n/a pirq[g]# no 2 option for sci, tco, mmt #0,1,2 23 n/a pirq[h]# no 2 usb 2.0 ehci controller, option for sci, tco, mmt #0,1,2 notes: 1. irq 14 and 15 may only be driven directly from the pins when in legacy ide mode. 2. no from external devices, yes of access from processor 3. in apic mode, the pci interrupts a:h are mapped to irq[16:23]. 4. when an interrupt is used for pci irq[a:h], sci, or tco, it should not be used for isa-style interrupts (via serirq) 5. when programming the polarity of internal interrupt sources on the apic, interrupts 0 through 15 receive active-high internal interrupt sources; interrupts 16 through 23 receive active-low internal interrupt sources 6. when irq11 is used for mmt #2, software should ensure irq 11 is not shared with any other devices to ensure the proper operation of mmt #2. the intel ? 6300ESB ich does not prevent sharing of irq 11. 7. pci message interrupts are not prevented by hardware in these cases. however, the system must not program these interrupts as edge-triggered (as required for pci message interrupts) because the internal and external pi rqs on these inputs must be programmed in level-triggered modes.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 125 5?intel ? 6300ESB ich 5.7.5.1 apic bus arbitration the i/o apic uses one wire arbitration to win bus ownership. a rotating priority scheme is used for apic bus arbitration. the winner of the arbitration becomes the lowest priority agent and assumes an arbitration id of zero. all other agents, except the agent whose arbitration id is 15, increment their arbitration ids by one. the agent whose id was 15 will take the winner's arbitration id and will increment it by one. arbitration ids are changed only for messages that are transmitted successfully (except for the low priority messages). a message is transmitted successfully when no cs error or acceptance error was reported for that message. an apic agent may use two different priority schemes: normal or eoi. eoi has the highest priority. eoi priority is used to send eoi messages for level interrupts from a local apic to an i/o apic. when an agent requests the bus with eoi priority, all other agents requesting the bus with normal priorities will back off. table 46. apic interrupt mapping, apic1 agent apic mode supported by apic1 agent irq # via serirq direct from pin from pci message internal modules 0no pxirq0yes 1no pxirq1yes 2no pxirq2yes 3no pxirq3yes 4no no yes 5no no yes 6no no yes 7no no yes 8no no yes 9no no yes 10 no no yes wdt 11 no no yes 12 no no yes 13 no no yes 14 no no yes 15 no no yes 16 no no yes 17 no no yes 18 no no yes 19 no no yes 20 no no yes 21 no no yes 22 no no yes 23 no no yes
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 126 order number: 300641-004us when the intel ? 6300ESB ich detects a bus idle condition on the apic bus, and it has an interrupt to send over the apic bus, it drives a start cycle to begin arbitration, by driving bit 0 to a ?0? on an apicclk rising edge. it then samples bit 1. when bit 1 was a zero, then a local apic started arbitration for an eoi message on the same clock edge that the intel ? 6300ESB ich started arbitration. the intel ? 6300ESB ich has thus lost arbitration and will stop driving the apic bus. when the intel ? 6300ESB ich did not see an eoi message start, it w ill start transferring its arbitration id, located in bits [27:24] of its arbitration id register (arbid). starting in cycle 2, through cycle 5, it will tri-state bit 0, and drive bit 1 to a ?0? when arbid[27] is a ?1?. when arbid[27] is a ?0?, it will also tri-state bit 1. at the end of each cycle, the intel ? 6300ESB ich will sample the state of bit 1 on the apic bus. when the intel ? 6300ESB ich did not drive bit 1 (arbid[27] = ?0?), and it samples a ?0?, then another apic agent started arbitration for the apic bus at the same time as the intel ? 6300ESB ich, and it has higher priority. the intel ? 6300ESB ich will stop driving the apic bus. ta b l e 4 7 describes the arbitration cycles. 5.7.5.2 bus message formats after bus arbitration, the winner is granted exclusive use of the bus and will drive its message. apic messages come in four formats, determined by the delivery mode bits. these four messages are of different length, and are known by all apics on the bus through the transmission of the delivery mode bits: eoi message for level triggered interrupts eoi messages are used by local apics to send an eoi cycle occurring for a level triggered interrupt to an i/o apic. this message is needed so that the i/o apic may differentiate between a new interrupt on the interrupt line versus the same interrupt on the interrupt line. the target of the eoi is given by the local apic through the transmission of the priority vector (v7 through v0) of the interrupt. upon receiving this table 47. arbitration cycles cycle bit 1 bit 0 comment 1 eoi 0 bit 1 = 1: normal, bit 1 = 0: eoi 2not ( arbid[27] )1 arbitration id. when the intel ? 6300ESB ich samples a different value than it sent, it lost arbitration. 3not ( arbid[26] )1 4not ( arbid[25] )1 5not ( arbid[24] )1 table 48. apic message formats message # of cycles delivery mode bits comments eoi 14 xxx end of interrupt transmission from local apic to i/o apic on level interrupts. eoi is known by the eoi bit at the start of arbitration short 21 001, 010, 100, 101, 111 i/o apic delivery on fixed, nmi, smi, reset, extint, and lowest priority with focus processor messages lowest priority 33 001 transmission of lowest priority interrupts when the status field indicates that the processor does not have focus. remote read 39 011 message from one local apic to another to read registers.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 127 5?intel ? 6300ESB ich message, the i/o apic resets the remote irr bit for that interrupt. when the interrupt signal is still active after the irr bit is reset, the i/o apic will treat it as a new interrupt. table 49. eoi message cycle bit 1 bit 0 comments 10 0eoi message 2 - 5 arbid 1 arbitration id 6not(v7)not(v6) interrupt vector bits v7 - v0 from redirection table register 7not(v5)not(v4) 8not(v3)not(v2) 9not(v1)not(v0) 10 not(c1) not(c0) check sum from cycles 6 - 9 11 1 1 postamble 12 not(a) not(a) status cycle 0 13 not(a1) not(a1) status cycle 1 14 1 1 idle
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 128 order number: 300641-004us short message short messages are used for the delivery of fixed, nmi, smi, reset, extint and lowest priority with focus processor interrupts. the delivery mode bits (m2?m0) specify the message. all short messages take 21 cycles including the idle cycle. table 50. short message cycle bit 1 bit 0 comments 1 1 0 normal arbitration 2 - 5 arbid 1 arbitration id 6 not(dm) not(m2) dm 1 = destination mode from bit 11 of the redirection table register 7not(m1)not(m0) m2-m0 = delivery mode from bits 10:8 of the redirection table register 8 not(l) not(tm) l = level, tm = trigger mode 9not(v7)not(v6) interrupt vector bits v7 - v0 from redirection table register 10 not(v5) not(v4) 11 not(v3) not(v2) 12 not(v1) not(v0) 13 not(d7) not(d6) destination field from bits 63:56 of redirection table register 1 14 not(d5) not(d4) 15 not(d3) not(d2) 16 not(d1) not(d0) 17 not(c1) not(c0) checksum for cycles 6 - 16 2 18 1 1 postamble 3 19 not(a) not(a) status cycle 0. see ta b le 5 1 . 20 not(a1) not(a1) status cycle 1. see ta b le 5 1 . 21 1 1 idle notes: 1. when dm is 0 (physical mode), cycles 15 and 16 are the apic id and cycles 13 and 14 are sent as ?1?. when dm is 1 (logical mode), cycles 13 through 16 are the 8-bit destination field. the interpretation of the logical mode 8-bit destination field is performed by the local units using the destination format register. shorthands of ?all-incl-self? and ?all-excl-self? both use physical destination mode and a destination field containing apic id value of all ones. the sending apic knows whether it should (incl) or should not (excl) respond to its own message. 2. the checksum field is the cumulative add (mod 4) of all data bits (dm, m0-3, l, tm, v0-7,d0- 7). the apic driving the message provides this checksum. this, in essence, is the lower two bits of an adder at the end of the message. 3. this cycle allows all apics to perform various internal computations based on the information contained in the received message. one of the computations takes the checksum of the data received in cycles 6 through 16 and compares it with the value in cycle 18. when any apic computes a different checksum than the one passed in cycle 17, the apic will signal an error on the apic bus (?00?) in cycle 19. when this occurs, all apics will assume the message was never sent and the sender must try sending the message again, which includes re-arbitrating for the apic bus. in lowest priority delivery when the interrupt has a focus processor, the focus processor will signal this by driving a ?01? during cycle 19. this tells all the other apics that the interrupt has been accepted, the arbitration is preempted, and short message format is used. cycle 19 and 20 indicates the status of the message, i.e., accepted, check sum error, retry or error. the following table shows the status signal combinations and their meanings for all delivery modes.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 129 5?intel ? 6300ESB ich lowest priority without focus processor (fp) message this message format is used to deliver an interrupt in the lowest priority mode in which it does not have a focus process. cycles 1 through 21 for this message is same as for the short message discussed above. status cycle 19 identifies when there is a focus processor (10) and a status value of 11 in cycle 20 indicates the need for lowest priority arbitration. table 51. apic bus status cycle definition delivery mode a comments a1 comments fixed, eoi 11 checksum ok 1x error 01 accepted 00 retry 10 error xx 01 error xx 00 checksum error xx nmi, smm, reset, extint 11 checksum ok 1x error 01 accepted 00 error 10 error xx 01 error xx 00 checksum error xx lowest priority 11 checksum ok: no focus processor 1x error 01 end and retry 00 go for low priority arbitration 10 error xx 01 checksum ok: focus processor xx 00 checksum error xx remote read 11 checksum ok xx 10 error xx 01 error xx 00 checksum error xx
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 130 order number: 300641-004us table 52. lowest priority message (without focus processor) cycle bit 1 bit 0 comments 1 1 0 normal arbitration 2 - 5 arbid 1 arbitration id 6not(dm)not(m2) dm = destination mode from bit 11 of the redirection table register. 7not(m1)not(m0) m2-m0 = delivery mode from bits 10:8 of the redirection table register. 8 not(l) not(tm) l = level, tm = trigger mode 9not(v7)not(v6) interrupt vector bits v7 - v0 from redirection table register. 10 not(v5) not(v4) 11 not(v3) not(v2) 12 not(v1) not(v0) 13 not(d7) not(d6) destination field from bits 63:56 of redirection table register. 14 not(d5) not(d4) 15 not(d3) not(d2) 16 not(d1) not(d0) 17 not(c1) not(c0) checksum for cycles 6 - 16 18 1 1 postamble 19 not(a) not(a) status cycle 0. 20 not(a1) not(a1) status cycle 1. 21 p7 1 inverted processor priority p7 - p0 22 p6 1 23 p5 1 24 p4 1 25 p3 1 26 p2 1 27 p1 1 28 p0 1 29 arbid3 1 30 arbid2 1 31 arbid1 1 32 arbid0 1 33 s s status 34 1 1 idle notes: 1. cycle 21 through 28 are used to arbitrate for the lowest priority processor. the processor that takes part in the arbitration drives the processor priority on the bus. only the local apics that have ?free interrupt slots? will participate in the lowest priority arbitration. 2. cycles 29 through 32 are used to break tie in case two more processors have lowest priority. the bus arbitration id's are used to break the tie.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 131 5?intel ? 6300ESB ich remote read message remote read message is used when a local apic wishes to read the register in another local apic. the i/o apic in the intel ? 6300ESB ich neither generates or responds to this cycle. the message format is same as short message for the first 21 cycles. table 53. remote read message (sheet 1 of 2) cycle bit 1 bit 0 comments 1 1 0 normal arbitration 2 - 5 arbid 1 arbitration id 6 not(dm) not(m2) dm = destination mode from bit 11 of the redirection table register. 7not(m1)not(m0) m2-m0 = delivery mode from bits 10:8 of the redirection table register. 8 not(l) not(tm) l = level, tm = trigger mode 9not(v7)not(v6) interrupt vector bits v7 - v0 from redirection table register. 10 not(v5) not(v4) 11 not(v3) not(v2) 12 not(v1) not(v0) 13 not(d7) not(d6) destination field from bits 63:56 of redirection table register. 14 not(d5) not(d4) 15 not(d3) not(d2) 16 not(d1) not(d0) 17 not(c1) not(c0) checksum for cycles 6 - 16 18 1 1 postamble 19 not(a) not(a) status cycle 0. 20 not(a1) not(a1) status cycle 1. 21 d31 d30 remote register data 31-0 22 d29 d28 23 d27 d26 24 d25 d24 25 d23 d22 26 d21 d20 27 d19 d18 28 d17 d16 29 d15 d14 30 d13 d12 31 d11 d10 32 d09 d08 33 d07 d06 34 d05 d04 35 d03 d02 36 d01 d00
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 132 order number: 300641-004us 5.7.6 pci message-based interrupts 5.7.6.1 theory of operation the following scheme is only supported when the internal i/o(x) apic is used, rather than just the 8259. the intel ? 6300ESB ich supports the new method for pci devices to deliver interrupts as write cycles rather than using the traditional pirq[a:d] signals. essentially, the pci devices are given a write path directly to a register that will cause the desired interrupt. this mode is only supported when the intel ? 6300ESB ich?s internal i/o apic is enabled. upon recognizing the write from the peripheral, the intel ? 6300ESB ich will send the interrupt message to the processor using the i/o apic?s serial bus. the interrupts associated with the pci message-based interrupt method must be set up for edge triggered mode, rather than level triggered, since the peripheral only does the write to indicate the edge. the following sequence is used: 1. during pci pnp, the pci peripheral is first programmed with an address (message_address) and data value (message_data) that will be used for the interrupt message delivery. for the intel ? 6300ESB ich, the message_address is the irq pin assertion register, which is mapped to memory location: fec0_0020h. 2. to cause the interrupt, the pci peripheral requests the pci bus and when granted, writes the message_data value to the location indicated by the message_address. the message_data value indicates which interrupt occurred. this message_data value is a binary encoded. for example, to indicate that interrupt 7 should go active, the peripheral will write a binary value of 0000111. the message_data w ill be a 32-bit value, although only the lower 5 bits are used. 3. when the prq bit in the apic version register is set, the intel ? 6300ESB ich positively decodes the cycles (as a slave) in medium time. 4. the intel ? 6300ESB ich decodes the binary value written to message_address and sets the appropriate irr bit in the internal i/o apic. the corresponding interrupt must be set up for edge-triggered interrupts. the intel ? 6300ESB ich supports interrupts 00h through 23h. binary values outside this range will not cause any action. 5. after sending the interrupt message to the processor, the intel ? 6300ESB ich will automatically clear the interrupt. 37 s s data status: 00 = valid, 11 = invalid 38 c c check sum for data d31-d00 39 1 1 idle note: cycle 21 through 36 contain the remote register data. the status information in cycle 37 specifies when the data is valid or invalid. remote read cycle is always successful (although the data may be valid or invalid) in that it is never retried. the reason for this is that remote read is a debug feature, and a ?hung? remote apic that is unable to respond should not cause the debugger to hang. table 53. remote read message (sheet 2 of 2) cycle bit 1 bit 0 comments
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 133 5?intel ? 6300ESB ich since they are edge triggered, the interrupts that are allocated to the pci bus for this scheme may not be shared with any other interrupt (such as the standard pci pirq[a:d], those received via serirq#, or the internal level-triggered interrupts such as sci or tco). the intel ? 6300ESB ich will ignore interrupt messages sent by pci masters that attempt to use irq0, 2, 8, or 13. 5.7.6.2 registers and bits associated with pci interrupt delivery capabilities indication the capability to support pci interrupt delivery will be indicated through acpi configuration techniques. this involves the bios creating a data structure that gets reported to the acpi configuration software. the os reads the prq bit in the apic version register to see when the intel ? 6300ESB ich is capable of supporting pci- based interrupt messages. interrupt message register the pci devices will all write their message into the irq pin assertion register, which is a memory-mapped register located at the apic base memory location + 20h. 5.7.7 processor system bus interrupt delivery 5.7.7.1 theory of operation for processors that support processor system bus interrupt delivery, the intel ? 6300ESB ich has an option to let the integrated i/o apic behave as an i/o (x) apic. in this case, it will deliver interrupt messages to the processor in a parallel manner, rather than using the i/o apic serial scheme. the intel ? 6300ESB ich is intended to be compatible with the i/o (x) apic specification, rev 1.1 this is done by the intel ? 6300ESB ich writing (through the hub interface) to a memory location that is snooped by the processor(s). the processor(s) snoop the cycle to know which interrupt goes active. the processor enables the mode by setting the i/o apic enable (apic_en) bit and by setting the dt bit in the i/o apic id register. the following sequence is used: 1. when the intel ? 6300ESB ich detects an interrupt event (active edge for edge- triggered mode or a change for level-triggered mode), it sets or resets the internal irr bit associated with that interrupt. 2. internally, the intel ? 6300ESB ich requests to use the bus in a way that automatically flushes upstream buffers. this may be internally implemented similar to a dma device request. 3. the intel ? 6300ESB ich then delivers the message by performing a write cycle to the appropriate address with the appropriate data. the address and data formats are described below in section 5.7.7.5, ?interrupt message format? . note: psb interrupt delivery compatibility with processor clock control depends on the processor, not the intel ? 6300ESB ich.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 134 order number: 300641-004us 5.7.7.2 edge-triggered operation in this case, the ?assert message? is sent when there is an inactive-to-active edge on the interrupt. 5.7.7.3 level-triggered operation in this case, the ?assert message? is sent when there is an inactive-to-active edge on the interrupt. when the interrupt is still active after an eoi, another ?assert message? is sent to indicate that the interrupt is still active. 5.7.7.4 registers associated with processor system bus interrupt delivery capabilities indication the capability to support processor system bus interrupt delivery will be indicated through acpi configuration techniques. this involves the bios creating a data structure that gets reported to the acpi configuration software. dt bit in the boot configuration register this enables the intel ? 6300ESB ich to deliver interrupts as memory writes. this bit is ignored when the apic mode is not enabled. 5.7.7.5 interrupt message format the intel ? 6300ESB ich writes the message to pci (and to the host controller) as a 32-bit memory write cycle. it uses the formats shown in tab le 54 and tab le 5 5 for the address and data. the local apic (in the processor) has a delivery mode option to interpret processor system bus messages as a smi in which case the processor treats the incoming interrupt as a smi instead of as an interrupt. this does not mean that the intel ? 6300ESB ich has any way to have a smi source from the intel ? 6300ESB ich power management logic cause the i/oapic to send an smi message (there is no way to do this). the intel ? 6300ESB ich?s i/oapic may only send interrupts due to interrupts which do not include smi, nmi or init. this means that in ia32/ia64 based platforms, processor system bus interrupt message format delivery modes 010 (smi/pmi), 100 (nmi), and 101 (init) as indicated in this section, must not be used and is not supported. only the hardware pin connection is supported by the intel ? 6300ESB ich. : table 54. interrupt message address format (sheet 1 of 2) bit description 31:20 will always be feeh 19:12 destination id: this will be the same as bits 63:56 of the i/o redirection table entry for the interrupt associated with this message. 11:4 extended destination id: this will be the same as bits 55:48 of the i/o redirection table entry for the interrupt associated with this message.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 135 5?intel ? 6300ESB ich 5.8 serial interrupt (d31:f0) the intel ? 6300ESB ich supports a serial irq scheme. this allows a single signal to be used to report interrupt requests. the signal used to transmit this information is shared between the host, the intel ? 6300ESB ich, and all peripherals that support serial interrupts. the signal line, serirq, is synchronous to pci clock, and follows the sustained tri-state protocol that is used by all pci signals. this means that when a device has driven serirq low, it will first drive it high synchronous to pci clock and release it the following pci clock. the serial irq protocol defines this sustained tri-state signaling in the following fashion: ? s - sample phase. signal driven low ? r - recovery phase. signal driven high 3 redirection hint: this bit is used by the processor host bridge to allow the interrupt message to be redirected. 0 = the message will be delivered to the agent (processor) listed in bits 19:12. 1 = the message will be delivered to an agent with a lower interrupt priority. this may be derived from bits 10:8 in the data field (see below). the redirection hint bit will be a 1 when bits 10:8 in the delivery mode field associated with corresponding interrupt are encoded as 001 (lowest priority). otherwise, the redirection hint bit will be 0. 2 destination mode: this bit is used only the redirection hint bit is set to 1. when the redirection hint bit and the destination mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical id. 1:0 will always be 00. table 55. interrupt message data format bit description 31:16 will always be 0000h. 15 trigger mode: 1 = level, 0 = edge. same as the corresponding bit in the i/o redirection table for that interrupt. 14 delivery status: 1 = assert, 0 = deassert. when using edge-triggered interrupts, this bit will always be 1, since only the assertion is sent. when using level-triggered interrupts, this bi t indicates the state of the interrupt input. 13:12 will always be 00 11 destination mode: 1 = logical. 0 = physical. same as the corresponding bit in the i/ o redirection table for that interrupt. 10:8 delivery mode: this is the same as the corresponding bits in the i/o redirection table for that interrupt. 000 = fixed 100 = nmi 001 = lowest priority 101 = init 010 = smi/pmi 110 = reserved 011 = reserved 111 = extint 7:0 vector: this is the same as the corresponding bits in the i/o redirection table for that interrupt. table 54. interrupt message address format (sheet 2 of 2) bit description
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 136 order number: 300641-004us ? t - turn-around phase. signal released the intel ? 6300ESB ich supports a message for 21 serial interrupts. these represent the 15 isa interrupts (irq0-1, 2-15), the four pci interrupts, and the control signals smi# and iochk#. the serial irq protocol does not support the additional apic interrupts (20-23). serial interrupt information is transferred using three types of frames: ? start frame: serirq line driven low by the intel ? 6300ESB ich to indicate the start of irq transmission ? data frames: irq information transmitted by peripherals. the intel ? 6300ESB ich will support 21 data frames. ? stop frame: serirq line driven low by the intel ? 6300ESB ich to indicate end of transmission and next mode of operation. note: when the ide primary and secondary controllers are configured for native ide mode, the only way to use the internal irq14 and irq15 connections to the interrupt controllers is through the serial interrupt pin. 5.8.1 start frame the serial irq protocol has two modes of operation which affect the start frame. these two modes are: continuous, where the intel ? 6300ESB ich is solely responsible for generating the start frame; and quiet, where a serial irq peripheral is responsible for beginning the start frame. the mode that must first be entered when enabling the serial irq protocol is continuous mode. in this mode, the intel ? 6300ESB ich w ill assert the start frame. this start frame is 4, 6, or 8 pci clocks wide based upon the serial irq control register, bits 1:0 at 64h in device 31:function 0 configuration space. this is a polling mode. when the serial irq stream enters quiet mode (signaled in the stop frame), the serirq line remains inactive and pulled up between the stop and start frame until a peripheral drives the serirq signal low. the intel ? 6300ESB ich senses the line low and continues to drive it low for the remainder of the start frame. since the first pci clock of the start frame was driven by the peripheral in this mode, the intel ? 6300ESB ich will drive the serirq line low for 1 pci clock less than in continuous mode. this mode of operation allows for a quiet, and therefore lower power, operation. 5.8.2 data frames once the start frame has been initiated, all of the serirq peripherals must start counting frames based on the rising edge of serirq. each of the irq/data frames has exactly 3 phases of 1 clock each: ? sample phase. during this phase, the serirq device drives serirq low when the corresponding interrupt signal is low. when the corresponding interrupt is high, the serirq devices will tri-state the serirq signal. the serirq line will remain high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). a low level during the irq0-1 and irq2-15 frames indicates that an active-high isa interrupt is not being requested, but a low level during the pci int[a:d], smi#, and iochk# frame indicates that an active- low interrupt is being requested. ? recovery phase. during this phase, the device will drive the serirq line high when in the sample phase it was driven low. when it was not driven in the sample phase, it will be tri-stated in this phase. ? turn-around phase. the device will tri-state the serirq line.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 137 5?intel ? 6300ESB ich 5.8.3 stop frame after all data frames, a stop frame is driven by the intel ? 6300ESB ich. the serirq signal is driven low by the intel ? 6300ESB ich for 2 or 3 pci clocks. the number of clocks is determined by the serirq configuration register. the number of clocks determines the next mode: 5.8.4 specific interrupts not supported via serirq there are three interrupts seen through the serial stream which are not supported by the intel ? 6300ESB ich. these interrupts are generated internally, and are not sharable with other devices within the system. these interrupts are: ? irq0. heartbeat interrupt generated off of the internal 8254 counter 0. ? irq8#. rtc interrupt may only be generated internally. ? irq13. floating point error interrupt generated off of the processor assertion of ferr#. the intel ? 6300ESB ich will ignore the state of these interrupts in the serial stream, and will not adjust their level based on the level seen in the serial stream. in addition, the interrupts irq14 and irq15 from the serial stream are treated differently than their isa counterparts. these two frames are not passed to the bus master ide logic. the bus master ide logic expects ide to be behind the intel ? 6300ESB ich. 5.8.5 data frame format tab l e 5 7 shows the format of the data frames. for the pci interrupts (a-d), the output from the intel ? 6300ESB ich is anded with the pci input signal. this way, the interrupt may be signaled through both the pci interrupt input signal and through the serirq signal (they are shared). table 56. stop frame explanation stop frame width next mode 2 pci clocks quiet mode. any serirq device may initiate a start frame 3 pci clocks continuous mode. only the host (intel ? 6300ESB ich) may initiate a start frame table 57. data frame format (sheet 1 of 2) data frame # interrupt clocks past start frame comment 1irq0 2 ignored. irq0 may only be generated through the internal 8524. 2 irq1 5 before port 60h latch 3smi# 8 causes smi# when low. will set the serirq_smi_sts bit, (bit 15). 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 138 order number: 300641-004us 5.9 real time clock (d31:f0) 5.9.1 rtc overview the real time clock (rtc) module provides a battery backed-up date and time keeping device with two banks of static ram with 128 bytes each, although the first bank has 114 bytes for general purpose usage. three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 s to 500 ms, and end of update cycle notification. seconds, minutes, hours, days, day of week, month, and year are counted. daylight savings compensation is optional. the hour is represented in twelve or twenty-four hour format, and data may be represented in bcd or binary format. the design is meant to be functionally compatible with the motorola* ms146818b. the time keeping comes from a 32.768 khz oscillating source, which is divided to achieve an update every second. the lower 14 bytes on the lower ram block has very specific functions. the first ten are for time and date information. the next four (0ah to 0dh) are registers, which configure and report rtc functions. see table 290 for more information. the time and calendar data should match the data mode (bcd or binary) and hour mode (12 or 24 hour) as selected in register b. it is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. the exceptions to these ranges is to store a value of c0-ffh in the alarm bytes to indicate a ?do not care? situation. all alarm conditions must match to trigger an alarm flag, which could trigger an alarm interrupt when enabled. the set bit must be one while programming these locations to avoid clashes with an update cycle. access to time and date information is done through the ram locations. when a ram read from the ten time and date bytes is attempted during an update cycle, the value read will not necessarily represent the true contents of those locations. any ram writes under the same conditions will be ignored. 9irq8 26 ignored. irq8# may only be generated internally or on isa. 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 before port 60h latch 14 irq13 41 ignored. irq13 may only be generated from ferr#. 15 irq14 44 do not include in bm ide interrupt logic. 16 irq15 47 do not include in bm ide interrupt logic. 17 iochck# 50 same as isa iochck# going active. 18 pci inta# 53 drive pirqa# 19 pci intb# 56 drive pirqb# 20 pci intc# 59 drive pirqc# 21 pci intd# 62 drive pirqd# note: siu_serirq period 13 is used to transfer irq12. table 57. data frame format (sheet 2 of 2) data frame # interrupt clocks past start frame comment
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 139 5?intel ? 6300ESB ich note: the intel ? 6300ESB ich supports the ab ility to generate an smi# based on a century rollover. see section 5.9.1.4, ?century rollover? for more information on the century rollover. note: the intel ? 6300ESB ich does not implement month/year alarms. 5.9.1.1 update cycles an update cycle occurs once a second, when the set bit of register b is not asserted and the divide chain is properly configured. during this procedure, the stored time and date will be incremented, overflow will be checked, a matching alarm condition will be checked, and the time and date will be rewritten to the ram locations. the update cycle will start at least 488 s after the uip bit of register a is asserted, and the entire cycle will not take more than 1984 s to complete. the time and date ram locations (0-9) will be disconnected from the external bus during this time. to avoid update and data corruption conditions, external ram access to these locations may safely occur at two times. when an updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date. when the uip bit of register a is detected to be low, there is at least 488 s before the update cycle begins. warning: the overflow conditions for leap years and daylight savings adjustments are based on more than one date or time item. to ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. 5.9.1.2 interrupts the real-time clock interrupt is internally routed within the intel ? 6300ESB ich both to the i/o apic and the 8259. it is mapped to interrupt vector 8. this interrupt does not leave the intel ? 6300ESB ich, nor is it shared with any other interrupt. irq8# from the serirq stream is ignored. 5.9.1.3 lockable ram ranges the rtc?s battery-backed ram supports two 8-byte ranges that may be locked through the configuration space. when the locking bits are set, the corresponding range in the ram will not be readable or writable. a write cycle to those locations will have no effect. a read cycle to those locations will return an undefined value. once a range is locked, the range may be unlocked only by a hard reset, which will invoke the bios and allow it to relock the ram range. 5.9.1.4 century rollover the intel ? 6300ESB ich will detect a rollover when the year byte (rtc i/o space, index offset 09h) transitions form 99 to 00. upon detecting the rollover, the intel ? 6300ESB ich will set the newcentury_sts bit (tcobase + 04h, bit 7). when the system is in an s0 state, this will cause an smi#. the smi# handler may update registers in the rtc ram that are associated with century value. when the system is in a sleep state (s1-s5) when the century rollover occurs, the intel ? 6300ESB ich will also set the newcentury_sts bit, but no smi# is generated. when the system resumes from the sleep state, bios should check the newcentury_sts bit and update the century value in the rtc ram.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 140 order number: 300641-004us 5.9.1.5 clearing battery-backed rtc ram clearing cmos ram in an intel ? 6300ESB ich-based platform may be done by using a jumper on rtcrst# or gpi, or using safemode strap. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. using rtcrst# to clear cmos: a jumper on rtcrst# may be used to clear cmos values, as well as reset to default, the state of those configuration bits that reside in the rtc power well. when the rtcrst# is strapped to ground, the rtc_pwr_sts bit (d31:f0:a4h bit 2) will be set and those configuration bits in the rtc power well will be set to their default state. bios may monitor the state of this bit, and manually clear the rtc cmos array once the system is booted. the normal position would cause rtcrst# to be pulled up through a weak pull-up resistor. ta b l e 5 8 presents which bits are set to their default state when rtcrst# is asserted. using a gpi to clear cmos: a jumper on a gpi may also be used to clear cmos values. bios would detect the setting of this gpi on system boot-up, and manually clear the cmos array. using the safemode strap to clear cmos: a jumper on ac_sdout (safemode strap) may also be used to clear cmos values. bios would detect the setting of the safe_mode status bit (d31:f0: offset d4h bit 2) on system boot-up, and manually clear the cmos array. note: both the gpi and safemode strap techniques to clear cmos require multiple steps to implement. the system is booted with the jumper in new position, then powered back down. the jumper is replaced back to the normal position, then the system is rebooted again. the rtcrst# jumper technique allows the jumper to be moved and then replaced, all while the system is powered off. then, once booted, the rtc_pwr_sts may be detected in the set state. table 58. configuration bits reset by rtcrst# assertion bit name default state register location bit(s) aie rtc reg b i/o space 5 0 af rtc reg c i/o space 5 0 pwr_flr gen_pmcon_3 d31:f0:a4h 1 0 afterg3_en gen_pmcon_3 d31:f0:a4h 0 0 rtc_pwr_sts gen_pmcon_3 d31:f0:a4h 2 1 prbtnor_sts pm1_sts pmbase + 00h 11 0 pme_en gpe0_en pmbase + 2ah 11 0 ri_en gpe0_en pmbase + 2ah 8 0 new_century_sts tco1_sts tcobase + 04h 7 0 intrd_det tco2_sts tcobase + 06h 0 0 top_swap gen_sts d31:f0:d4h 13 0 rtc_en pm1_en pmbase + 02h 10 0 batlow_en gpe0_en pmbase + 2ah 10 0
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 141 5?intel ? 6300ESB ich 5.10 processor interface (d31:f0) the intel ? 6300ESB ich interfaces to the processor with a variety of signals ? standard outputs to the processor: a20m#, smi#, nmi, init#, intr, stpclk#, ignne#, cpuslp# ? the ferr# input to the intel ? 6300ESB ich has special buffer requirements. the vil threshold is compatible with processors that drive ferr# no higher than 1.3v +/- 5%. most intel ? 6300ESB ich outputs to the processor use standard buffers. the intel ? 6300ESB ich has a separate v cc signal which is pulled up at the system level to the processor voltage, and thus determines v oh for the outputs to the processor. note that this is different than previous generations of chips, that have used open-drain outputs. this new method saves up to 12 external pull-up resistors. the intel ? 6300ESB ich does not support the processor?s frc mode. 5.10.1 processor interface signals this section describes each of the signals that interface between the intel ? 6300ESB ich and the processor(s). 5.10.1.1 a20m# the a20m# signal will be active (low) when both of the following conditions are true: ? the alt_a20_gate bit (bit 1 of port92 register) is a ?0? ? the a20gate input signal is a ?0? the a20gate input signal is expected to be generated by the external microcontroller (kbc). 5.10.1.2 init# the init# signal will be active (low) based on any one of several events described in tab l e 5 9 . when any of these events occur, init# will be driven low for 16 pci clocks, then driven high. the 16-clock counter for init# assertion will halt while stpclk# is active. init# will not go active until after stpclk# goes inactive. table 59. init# going active (sheet 1 of 2) cause of init# going active comment shutdown special cycle from processor. port92 write, where init_now (bit 0) transitions from a 0 to a 1.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 142 order number: 300641-004us 5.10.1.3 ferr#/ignne# (coprocessor error) the intel ? 6300ESB ich supports the coprocessor error function with the ferr#/ ignne# pins. the function is enabled through the coproc_err_en bit (device 31:function 0, offset d0, bit 13). ferr# is tied directly to the coprocessor error signal of the processor. when ferr# is driven active by the processor, irq13 goes active (internally). when it detects a write to the coproc_err register, the intel ? 6300ESB ich negates the internal irq13 and drives ignne# active. ignne# remains active until ferr# is driven inactive. ignne# is never driven active unless ferr# is active. when coproc_err_en is not set, the assertion of ferr# will have not generate an internal irq13, nor will the write to f0h generate ignne#. portcf9 write, where rst_cpu (bit 2) was a 0 and sys_rst(bit 1) transitions from 0 to 1. rcin# input signal goes low. rcin# is expected to be driven by the external microcontroller (kbc). 0 to 1 transition on rcin# must occur before the intel ? 6300ESB ich will arm init# to be generated again. note: rcin# signal is expected to be high during s1-m and low during s3, s4, and s5 states. transition on the rcin# signal in those states (or the transition to those states) may not necessarily cause the init# signal to be generated to the processor cpu bist in order to enter bist, the software sets cpu_bist_en bit and then does a full processor reset using the cf9 register. table 59. init# going active (sheet 2 of 2) cause of init# going active comment figure 14. coprocessor error timing diagram ferr# internal irq13 i/o write to f0h ignne#
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 143 5?intel ? 6300ESB ich 5.10.1.4 nmi non-maskable interrupts (nmis) may be generated by several sources, as described in tab l e 6 0 . 5.10.1.5 stpclk# and cpuslp# signals the intel ? 6300ESB ich power management logic controls these active-low signals. refer to section 5.11, ?power management (d31:f0)? for more information on the functionality of these signals. 5.10.2 dual processor issues 5.10.2.1 signal differences in dual processor designs, some of the processor signals are used differently than in uniprocessor designs. 5.10.2.2 dual processor power management for multiple-cpu (or multiple-core) configurations in which more than one stop grant cycle may be generated, the mch is expected to count stop grant cycles and only pass the last one through to the 6300ESB. this prevents the 6300ESB from getting out of sync with the processor on multiple stpclk# assertions. table 60. nmi sources cause of nmi comment serr# goes active (either internally, externally through serr# signal, or through a message from mch) may instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, offset 4e, bit 11). iochk# goes active via serirq# stream (isa system error) may instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, offset 4e, bit 11). d30_pd_sts register (d30:f0:06h), bit 8 (detected parity error on hub interface) enabled by d30:f0:04h, bit 6 d30_secsts register (d30:f0:1eh), bit 8 (detected parity error on pci by north pci unit) enabled by d30:f0:04h, bit 6 d31f0_dev_sts register (d31:f0:06h), bit 8 (detected parity error on pci by south pci unit) table 61. dp signal differences signal difference a20m# / a20gate generally not used, but still supported by the intel ? 6300ESB ich. stpclk# used for s1 state as well as preparation for entry to s3-s5. also allows for therm# based throttling (not through acpi control methods). should be connected to both processors. ferr# / ignne# generally not used, but still supported by the intel ? 6300ESB ich.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 144 order number: 300641-004us because the s1 state will have the stpclk# signal active, the stpclk# signal can be connected to both processors. however, for acpi implementations, the bios must indicate that the 6300ESB only supports the c1 state for dual-processor designs. in going to the s1 state, multiple stop-grant cycles will be generated by the cpus. the intel 6300ESB also has the option to assert the cpu?s slp# signal (cpuslp#). it is assumed that prior to setting the slp_en bit (which causes the transition to the s1 state), the cpus will not be executing code that is likely to delay the stop-grant cycles. in going to the s3, s4, or s5 states, the system will appear to pass through the s1 state; thus, stpclk# and slp# are also used. during the s3, s4, and s5 states, both processors will lose power. upon exit from those states, the processors will have their power restored.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 145 5?intel ? 6300ESB ich 5.11 power management (d31:f0) 5.11.1 features ? acpi power and thermal management support ? processor thrmtrip# emergency shutdown ? acpi 24-bit timer ? software initiated throttling of processor performance for thermal and power reduction ? hardware override to throttle processor performance when system too hot ?sci and smi# generation ? pme# signal for wake up from low-power states (pme signal shared between both pci and pci-x interfaces) ? sys_reset# input to eliminate external glue logic ? system clock control ? acpi c2 state: stop-grant (in desktop) or quickstart (in mobile) state (using stpclk# signal) halts processor?s instruction stream ? system sleeping state control ? acpi s1 state: like c2 state (only stpclk# active, and slp# optional) ? acpi s3 state - suspend to ram (str) ? acpi s4 state - suspend-to-disk(std) ? acpi g2/s5 state - soft off(soff) ? power failure detection and recovery ? supports new output signal - slp_s4# ? streamlined legacy power management support for apm-based systems ? support for prescott processor
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 146 order number: 300641-004us 5.11.2 intel ? 6300ESB ich power states and transition rules ta b l e 6 2 shows the power states defined for intel ? 6300ESB ich-based platforms. the state names generally match the corresponding acpi states. table 62. general power states for systems using intel ? 6300ESB ich state/ substates legacy name / description g0/s0/c0 full on: processor operating. individual devices may be shut down to save power. the different processor operating levels are defined by cx states, as shown in ta b le 6 3 . within the c0 state, the intel ? 6300ESB ich may throttle the stpclk# signal to reduce power consumption. the throttling may be initiated by software or by the thrm# input signal. g0/s0/c1 auto-halt: processor has executed a autohalt instruction and is not executing code. the processor snoops the bus and maintains cache coherency. g0/s0/c2 stop-grant: the stpclk# signal goes active to the processor. the processor performs a stop-grant cycle, halts its instruction stream, and remains in that state until the stpclk# signal goes inactive. in the stop-grant (desktop) state, the processor snoops the bus and maintains cache coherency. note: this state is not supported for ia64 processors. they should instead use c1. g1/s1 stop-grant: similar to g0/s0/c2 state. the intel ? 6300ESB ich also has the option to assert the cpuslp# signal to further reduce processor power consumption. note: the behavior for this state is slightly different when supporting ia64 processors. g1/s3 suspend-to-ram (str): the system context is maintained in system dram, but power is shut off to non-critical circuits. memory is retained, and refreshes continue. all clocks stop except rtc clock. g1/s4 suspend-to-disk (std): the context of the system is maintained on the disk. all power is then shut off to the system except for the logic required to resume. g2/s5 soft off (soff): system context is not maintained. all power is shut off except for the logic required to restart. a full boot is required when waking. g3 mechanical off (moff): system context not maintained. all power is shut off except for the rtc. no ?wake? events are possible, because the system does not have any power. this state occurs when the user removes the batteries, turns off a mechanical switch, or when the system power supply is at a level that is insufficient to power the ?waking? logic. when system power returns, transition will depends on the state just prior to the entry to g3 and the afterg3 bit in the gen_pmcon3 register (d31:f0, offset a4). refer to ta b le 7 1 for more details.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 147 5?intel ? 6300ESB ich tab l e 6 3 shows the transitions rules among the various states. note that transitions among the various states may appear to temporarily transition through intermediate states. for example, in going from s0 to s1, it may appear to pass through the g0/s0/ c2 states. these intermediate transitions and states are not listed in the table. table 63. state transition rules for intel ? 6300ESB i/o controller hub present state transition trigger next state g0/s0/c0 ? processor halt instruction ?level 2 read ?slp_en bit set ? power button override ? mechanical off/power failure ?g0/s0/c1 ?g0/s0/c2 ? g1/sx or g2/s5state ?g2/s5 ?g3 g0/s0/c1 ? any enabled break event ?stpclk# goes active ? power button override ? power failure ?g0/s0/c0 ?g0/s0/c2 ?g2/s5 ?g3 g0/s0/c2 ? any enabled break event ? stpclk# goes inactive and previously in c1 ? power button override ? power failure ?g0/s0/c0 ?g0/s0/c1 ?g2/s5 ?g3 g1/s1, g1/s3, or g1/s4 ? any enabled wake event ? power button override ? power failure ?g0/s0/c0 ?g2/s5 ?g3 g2/s5 ? any enabled wake event ? power failure ? g0/s0/c0 ?g3 g3 ? power returns ? optional to go to s0/c0 (reboot) or g2/s5 (stay off until power button pressed or other wake event). note: some wake events may be preserved through power failure.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 148 order number: 300641-004us 5.11.3 system power planes the system has several independent power planes. these power planes can be shut off and the voltage set to a zero volt level. the power planes and their control signals are listed in ta b le 64 . s 5.11.4 intel ? 6300ESB ich power planes the intel ? 6300ESB ich power planes were previously defined in section 4.1, ?power planes? . although not specific power planes within the intel ? 6300ESB ich, there are many interface signals that go to devices that may be powered down. these include: ? ide: output signals may be tri-stated or driven low and all input buffers may be shut off ? usb: output signals may be tri-stated and all input buffers may by shut off when usb wakeup is not desired. ? ac?97: output signals may be driven low and input buffers may be shut off. table 64. system power plane plane controlled by description processor slp_s3# signal the slp_s3# signal may be used to cut the processor?s power completely. main slp_s3# signal when slp_s3# goes active, power may be shut off to any circuit not required to wake the system from the s3 state. since the s3 state requires that the memory context be preserved, power must be retained to the main memory. the processor, devices on the pci bus, lpc i/f downstream hub interface and agp will typically be shut off when the main power plane is shut off, although there may be small subsections powered. memory slp_s4# signal when the slp_s4# goes active, power may be shut off to any circuit not required to wake the system from the s4. since the memory context does not need to be preserved in the s4 state, the power to the memory may also be shut down. memory slp_s5# signal when the slp_s5# goes active, power may be shut off to any circuit not required to wake the system from the s5. since the memory context does not need to be preserved in the s5 state, the power to the memory may also be shut down. device[n] gpio individual subsystems may have their own power plane. for example, gpio signals may be used to control the power to disk drives, audio amplifiers, or the display screen.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 149 5?intel ? 6300ESB ich 5.11.5 smi#/sci generation upon any smi# event, the intel ? 6300ESB ich will assert smi# to the processor, which will cause it to enter smm space. smi# remains active until the eos bit is set. when the eos bit (bit 1) is set, smi# will go inactive for a minimum of four pci clocks. see section 8.8.3.9, ?smi_en?smi control and enable register? for details on the smi control register. the sci is a level-mode interrupt that is typically handled by an acpi-aware operating system. in non-apic systems (which is the default), the sci irq is routed to one of the 8259 interrupts (irq9, 10, or 11). the 8259 interrupt controller must be programmed to level mode for that interrupt. in systems using the apic, the sci may be routed to interrupts 9, 10, 11, 20, 21, 22, or 23 the interrupt polarity changes depending on whether it is on an interrupt shareable with a pirq or not. the interrupt will remain asserted until all sci sources are removed. tab l e 3 2 shows which events may cause an sci, and tab le 6 5 shows the causes of an smi#. note that some events may be programmed to cause either an smi# or sci. the usage of the event for sci (instead of smi#) is typically associated with an acpi-based system. causes of tco sci are discussed in section 5.12.3, ?tco theory of operation? . table 65. causes of sci cause additional enables 1 where reported pme# pme_en = 1 pme_sts internal ehci wake (pme_b0) pme_b0_en = 1 pme_b0_sts power button press pwrbtn_en = 1 pwrbtn_sts rtc alarm rtc_en = 1 rtc_sts ring indicate ri_en = 1 ri_sts ac?97 wakes ac97_en = 1 ac97_sts usb #1 wakes usb1_en = 1 usb1_sts usb #2 wakes usb2_en = 1 usb2_sts usb #3 wakes usb3_en = 1 usb3_sts thrm# pin active (based on thrm#_pol) thrm_en = 1 thrm_sts acpi timer overflow (2.34 seconds) tmrof_en = 1 tmrof_sts any gpi gpi[x]_route = 10, gpe[x]_en = 1 gpi[x]_sts tco sci logic 1 , 2 tcosci_en = 1 tcosci_sts bios_rls written to 1 gbl_en = 1 gbl_sts wdt 1 st timeout wdt_enable = 1, wdt_int_type = ?01? wdtsci_sts notes: 1. sci_en must be 1 to enable sci. 2. sci may be routed to cause interrupt 9:11 or 20:23 (20:23 only available in apic mode).
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 150 order number: 300641-004us table 66. causes of smi# (sheet 1 of 2) cause additional enables where reported synch pme# sci_en = 0, pme_en = 1 pme_sts internal ehci wake (pme_b0) sci_en = 0, pme_b0_en = 1 pme_b0_sts power button press sci_en = 0, pwrbtn_en = 1 pwrbtn_sts rtc alarm sci_en = 0, rtc_en = 1 rtc_sts ring indicate sci_en = 0, ri_en = 1 ri_sts ac?97 wakes sci_en = 0, ac97_en = 1 ac97_sts usb #1 wakes sci_en = 0, usb1_en = 1 usb1_sts usb #2 wakes sci_en = 0, usb2_en = 1 usb2_sts usb #3 wakes sci_en = 0, usb3_en = 1 usb3_sts thrm# pin active (based on thrm#_pol) sci_en = 0, thrm_en = 1 thrm_sts acpi timer overflow (2.34 seconds) sci_en = 0, tmrof_en = 1 tmrof_sts any gpi gpi[x]_route = 01, gpe[x]_en = 1 gpe1_sts, gpi[x]_sts tco smi logic (see table below) tco_en = 1 tco_sts nmi occurred (and nmis mapped to smi) see nmi section for causes of nmi nmi2smi_en = 1 tco_sts, nmi2smi_sts gbl_rls written to 1 bios_en = 1 bios_sts write to b2h register none apm_sts x periodic timer expires periodic_en = 1 periodic_sts 64 ms timer expires swsmi_tmr_en = 1 swsmi_tmr_sts enhanced usb legacy support event legacy_usb2_en = 1 legacy_usb2_sts enhanced usb intel-specific event intel_usb2_en = 1 intel_usb2_sts classic usb legacy logic (port 64/60 r/w, end of pass through) legacy_usb_en = 1 legacy_usb_sts x classic usb legacy logic (irq) legacy_usb_en = 1 legacy_usb_sts serial irq smi reported none serirq_smi_sts notes: 1. gbl_smi_en must be 1 to enable smi. 2. eos must be written to 1 to re-enable smi for the next one. 3. some smi#s are considered ?synchronous?, in that the processor should recognize the smi# prior to completing the instruction (i/o read, i/o write, memory read, or memory write) that should cause the smi#. this is accomplished by having the smi# signal go active to the processor prior to the processor observing the rdy# signal that terminates the cycle. smi#s marked with x in the synch column are treated as synchronous.synchronous smi#s are not possible in ia64 platforms, since they do not support the smi# signal. 4. nmi2smi_sts is not gated by tco_en.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 151 5?intel ? 6300ESB ich see section 5.12.3, ?tco theory of operation? for details on the tco smi# causes. device monitors matches an address in its range dev[n]_trap_en = 1 devmon_sts, dev[n]_trap_sts x smbus host controller smb_smi_en host controller enabled various bits in the smbus host status register smbus slave smi message none smbus_smi_sts smbus smbalert# signal active none smbus_smi_sts smbus host notify message received host_notify_intren smbus_smi_sts, host_notify_sts access to microcontroller range (62h/66h) mcsmi_en mcsmi_sts x slp_en bit written to 1 smi_on_slp_en = 1 smi_on_slp_en_s ts x wdt 1 st timeout wdt_enable = 1, wdt_int_type = ?10? wdt_smi_sts table 67. causes of tco smi# cause additional enables where reported century rollover none newcentury_sts tco timerout none timeout os writes to tco_dat_in register none os_tco_smi message from mch none mchsmi_sts nmi occurred (and nmis mapped to smi) see nmi section for causes of nmi nmi2smi_en = 1 nmi2smi_sts note: nmi2smi_sts is not gated by tco_en. see table above. intruder# signal goes active intrd_sel = 10 intrd_det changes of the bioswp bit from 0 to 1 bld = 1 bioswr_sts write attempted to bios bioswp = 1 bioswr_sts table 66. causes of smi# (sheet 2 of 2) cause additional enables where reported synch notes: 1. gbl_smi_en must be 1 to enable smi. 2. eos must be written to 1 to re-enable smi for the next one. 3. some smi#s are considered ?synchronous?, in that the processor should recognize the smi# prior to completing the instruction (i/o read, i/o write, memory read, or memory write) that should cause the smi#. this is accomplished by having the smi# signal go active to the processor prior to the processor observing the rdy# signal that terminates the cycle. smi#s marked with x in the synch column are treated as synchronous.synchronous smi#s are not possible in ia64 platforms, since they do not support the smi# signal. 4. nmi2smi_sts is not gated by tco_en.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 152 order number: 300641-004us 5.11.6 dynamic processor clock control the intel ? 6300ESB ich has extensive control for dynamically starting and stopping system clocks. the clock control is used for transitions among the various s0/cx states, and processor throttling. each dynamic clock control method is described in this section. the various sleep states may also perform types of non-dynamic clock control. the intel ? 6300ESB ich supports the acpi c0, c1 and c2 states. c3 and c4 are not supported. the dynamic processor clock control is handled using the following signal: ? stpclk#: used to halt processor instruction stream. note: the intel? 6300ESB ich does support thrm# based throttling. the c1 state (processor auto halt) may be used with either one or two processors, however. processors are free to perform their own dynamic clock control; however, this is done without any coordination by the intel? 6300ESB ich. the c1 state is entered based on the processor performing an auto halt instruction. the c2 state is entered based on the processor reading the level 2 register in the intel ? 6300ESB ich. a c1 or c2 state ends due to a break event. based on the break event, the intel ? 6300ESB ich returns the system to c0 state. ta b l e 6 8 lists the possible break events from c2 states. the break events from c1 are indicated in the processor?s datasheet. the intel ? 6300ESB ich supports the pending break event (pbe) indication from the processor us- ing the ferr# signal. the following rules apply: 1. when stpclk# is detected active by the processor, the ferr# signal from the processor will be redefined to indicate whether an interrupt is pending. the signal is active low (i.e., ferr# will be low to indicate a pending interrupt). 2. when the intel ? 6300ESB ich asserts stpclk#, it will latch the current state of the ferr# signal and continue to present this state to the ferr# state machine (independent of what the ferr# pin does after the latching). 3. when the intel ? 6300ESB ich detects the stop-grant cycle, it will start looking at the ferr# signal as a break event indication. when ferr# is sampled low, a break event is indicated. this will force a transition to the c0 state. 4. when the processor detects the deassertion of stpclk#, the processor will start driving the ferr# signal with the natural value (i.e.the value it would do when the pin was not muxed). the time from stpclk# inactive to the ferr# signal transition back to the native function must be less than 120 ns. table 68. break events event breaks from comment any unmasked interrupt goes active c2 irq[0:15] when using the 8259s, irq[0:23] for i/o xapic0 and i/o xa[ic1. since sci is an interrupt, any sci will also be a break event. any internal event that will cause an nmi or smi# c2 many possible sources. any internal event that will cause init# to go active c2 could be indicated by the keyboard controller through the rcin input signal. processor pending break event indication c2 only available when ferr# enabled for break event indication (see ferr# mux-en in section 8.1.22, ?offset d0h - d3h: gen_cntl? general control register (lpc i/f?d31:f0)? ).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 153 5?intel ? 6300ESB ich 5. the intel ? 6300ESB ich waits at least 180 ns to 8 pci clocks (240 ns) after deasserting stpclk# and then starts using the ferr# signal for an indication of a floating point error. the maximum time that the intel ? 6300ESB ich may wait is bounded such that it must have a chance to look at the ferr# signal before reasserting stpclk#. based on current implementation, that maximum time would be 240 ns (8 pci clocks). since the processor has 120-210 ns to revert to the proper ferr# function, there are 60-30 ns of margin inherent in the timings. the break event associated with this new mechanism does not need to set any particular status bit, since the pending interrupt will be serviced by the processor after returning to the c0 state. 5.11.6.1 throttling using stpclk# throttling is used to lower power consumption or reduce heat. the intel ? 6300ESB ich asserts stpclk# to throttle the processor clock and the processor appears to temporarily enter a c2 state. after a programmable time, the intel ? 6300ESB ich deasserts stpclk# and the processor appears to return to the c0 state. this allows the processor to operate at reduced average power, with a corresponding decrease in performance. two methods are included to start throttling: 1. software enables a timer with a programmable duty cycle. the duty cycle is set by the thtl_dty field and the throttling is enabled using the thtl_en field. this is known as manual throttling. the period is fixed to be in the non-audible range, due to the nature of switching power supplies. 2. a thermal override condition (thrm# signal active for >2 seconds) occurs that unconditionally forces throttling, independent of the thtl_en bit. the throttling due to thermal override has a separate duty cycle (thrm_dty) which may vary by field and system. the thermal override condition will end when thrm# goes inactive. throttling due to the thrm# signal has higher priority than the software initiated throttling. throttling does not occur when the system is in a c2 state, even when thermal override occurs. 5.11.6.2 transition rules among s0/cx and throttling states the following priority rules and assumptions apply among the various s0/cx and throttling states: ? entry to any s0/cx state is mutually exclusive with entry to any s1?s5 state. this is because the processor may only perform one register access at a time and sleep states have higher priority than thermal throttling. ? when the slp_en bit is set (system going to a sleep state (s1?s5), the thtl_en bit may be internally treated as being disabled (no throttling while going to sleep state). note that thermal throttling (based on thrm# signal) cannot be disabled in an s0 state. however, once the slp_en bit is set, the thermal throttling is shut off (since stpclk# will be active in s1?s5 states). ? when the thtl_en bit is set, and a level 2 read then occurs, the system should immediately go and stay in a c2 state until a break event occurs. a level 2 read has higher priority than the software initiated throttling or thermal throttling. ? when thermal override is causing throttling, and a level 2 read then occurs, the system will stay in a c2 state until a break event occurs. a level 2 read has higher priority than the thermal override. ? after an exit from a c2 state (due to a break event), and when the thtl_en bit is still set, or when a thermal override is still occurring, the system will continue to throttle stpclk#. depending on the time of break event, the first transition on stpclk# active may be delayed by up to one thrm period (1024 pci clocks=30.72 microseconds).
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 154 order number: 300641-004us ? the host controller must post stop-grant cycles in such a way that the processor gets an indication of the end of the special cycle prior to the intel ? 6300ESB ich observing the stop-grant cycle. this ensures that the stpclk# signals stays active for a sufficient period after the processor observes the response phase. ? when in the c1 state and the stpclk# signal goes active, the processor will generate a stop-grant cycle, and the system should go to the c2 state. when stpclk# goes inactive, it should return to the c1 state. 5.11.6.3 stpclk# implementation notes the processor treats stpclk# like an interrupt and recognizes it on instruction boundaries (no inta cycles are run). when it recognizes stpclk# active, the processor stops execution on the next instruction boundary, stops the pre-fetch unit, empties internal pipelines and write buffers, and generates a stop-grant bus cycle before entering the stop grant state. the processor may stop the clock to most of its internal modules, and no instructions are executed. the processor exits the stop grant state when it is reset, or upon sampling stpclk# inactive. the processor will latch transitions on the external interrupt signals (smi#, nmi, intr, and init#) while in stop grant state. these interrupts are taken after the deassertion of stpclk#. for the intel ? pentium ? 4 processor, the following edge signals must not transition while stpclk# is active: ? intr ? init# ? smi# ? nmi these signals should be run through a transparent latch internal to the intel ? 6300ESB ich. while stpclk# is inactive (high) these signals propagate to the intel ? 6300ESB ich's pins and onto the processor as normal. however when stpclk# is asserted then these signals are latched so that they may not change until stpclk# is deasserted. this ensures that an edge on these signals is seen while the processor has a valid clock. these signals need to be latched at least 1 hclk clock before stpclk# assertion, and held 16 hclk clocks after stpclk# deassertion. figure 15. latching processor i/f signals with stopclk# stpclk# t- latch smi#, nmi#, intr pciclk smi#, nmi#, intr pin
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 155 5?intel ? 6300ESB ich other implementation notes: ? when stpclk# goes active due to a level read, it must go active prior to the completion of the associated i/o read. this is to ensure that the stpclk# is recognized by the processor prior to it recognizing the end of the i/o cycle. that will prevent the next instruction from being executed. ? the state machine must insure that the stpclk# signal stays high for a minimum period of time. when stpclk# is to go low due to throttling (regular or due to the thrm# signal), this could be very soon after it was driven high. the mch should ensure that the stop-grant cycle coming down the hub interface occurs after the brdy# is seen by the processor. exception: for smi#s that are caused by a processor i/o cycle, when stpclk# is active, the intel ? 6300ESB ich will still drive smi# active. this is because the stpclk# was obviously too late to be recognized at the instruction boundary. the i/o cycles that may cause smi# include: writes to the apm register (b2h), accesses to 60/ 64h when ?legacy usb kbc scheme? is used, traps for monitors 4, 5, 6, and 7, the smi# on slp_en bit, accesses to 62/66h when the mcsmi_en bit is set, access to registers with their associated enable set in the devtrap_en register, and the bios_sts bit (which is set by the processor writing a 1 to the glb_rls bit when the bios_en bit is also set). 5.11.7 sleep states 5.11.7.1 sleep state overview the intel ? 6300ESB ich directly supports different sleep states (s1?s5), which are entered by setting the slp_en bit, or due to a power button press. the entry to the sleep states are based on several assumptions: ? entry to a cx state is mutually exclusive with entry to a sleep state. this is because the processor may only perform one register access at a time. a request to sleep always has higher priority than throttling. ? prior to setting the slp_en bit, the software will turn off processor-controlled throttling. note that thermal throttling cannot be disabled, but setting the slp_en bit will disable thermal throttling (since s1?s5 sleep state has higher priority). ? the g3 state cannot be entered through any software mechanism. the g3 state indicates a complete loss of power. 5.11.7.2 initiating sleep state sleep states (s1?s5) are initiated by: ? masking interrupts, turning off all bus master enable bits, setting the desired type in the slp_typ field and then setting the slp_en bit. the hardware will then attempt to gracefully put the system into the corresponding sleep state by first going to a c2 state. see section 5.11.6, ?dynamic processor clock control? for details on going to the c2 state. ? pressing the pwrbtn# signal for more than four seconds to cause a power button override event. in this case the transition to the s5 state will be less graceful, since there will be no dependencies on observing stop-grant cycles from the processor or on clocks other than the rtc clock.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 156 order number: 300641-004us other assumptions: ? entry to a cx state is mutually exclusive with entry to a sleep state. this is because the processor may only perform one register access at a time. a request to sleep always has higher priority than throttling. ? prior to setting the slp_en bit, the software will turn off processor-controlled throttling. note that thermal throttling cannot be disabled, but setting the slp_en bit will disable throttling (since s1-s5 sleep state has higher priority). ? the g3 state cannot be entered through any software mechanism. the g3 state indicates a complete loss of power. before entering sleep state, an acpi os will mask all interrupts and will turn off all bus master enable bits. for non-acpi systems, the bios will mask interrupts and turn off all bus master enable bits. note: interrupts might not be masked at the i/o subsystem. some operating systems have been observed to only mask interrupts inside the processor. 5.11.7.3 exiting sleep states sleep states (s1?s5) are exited based on wake events. the wake events will force the system to a full on state (s0), although some non-critical subsystems might still be shut off and have to be brought back manually. for example, the hard disk may be shut off during a sleep state, and have to be enabled through a gpio pin before it may be used. upon exit from the intel ? 6300ESB ich-controlled sleep states, the wak_sts bit will be set. the possible causes of wake events (and their restrictions) are shown in ta b l e 7 0 . table 69. sleep types sleep type comment s1 the intel ? 6300ESB ich asserts the stpclk# signal. it also has the option to assert cpuslp# signal. this will lower the processor?s power consumption. no snooping is possible in this state. s3 the intel ? 6300ESB ich asserts slp_s3#. the slp_s3# signal will control the power to non-critical circuits. power will only be retained to devices needed to wake from this sleeping state, as well as to the memory. s4 the intel ? 6300ESB ich asserts slp_s3# and slp_s4#. the slp_s4# signal will shut off the power to the memory subsystem. only devices needed to wake from this state should be powered. s5 same power state as s4. the intel ? 6300ESB ich asserts slp_s3#, slp_s4# and slp_s5#. table 70. causes of wake events (sheet 1 of 2) cause states can wake from how enabled rtc alarm s1 ? s5 set rtc_en bit in pm1_en register note: when in the s5 state due to a powerbutton override, the only wake events are power button, wake smbus slave message (01h), and hard reset smbus slave messages (03h, 04h). note: pme#, rtc, gpi[0:n], and ri# will be wake events from s5 only when it was entered through software setting the slp_en and slp_typ bits, or if there is a power failure.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 157 5?intel ? 6300ESB ich 5.11.7.4 sx-g3-sx, handling power failures in desktop systems, power failures may occur when the ac power is cut (a real power failure) or when the system is unplugged. in either case, pwrok and rsmrst# are assumed to go low. depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. the after_g3 bit provides the ability to program whether or not the system should boot once power returns after a power loss event. when the policy is to not boot, the system will remain in an s5 state (unless previously in s4). there are only three possible events that will wake the system after a power failure. 1. pwrbtn#: pwrbtn# is always enabled as a wake event. when rsmrst# is low (g3 state), the pwrbtn_sts bit is reset. when the intel ? 6300ESB ich exits g3 after power returns (rsmrst# goes high), the pwrbtn# signal is already high (because v cc -standby goes high before rsmrst# goes high) and the pwrbtn_sts bit is 0. 2. ri#: ri# does not have an internal pull-up. therefore, when this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. when this signal goes low (active), when power returns the ri_sts bit will be set and the system will interpret that as a wake event. 3. rtc alarm: the rtc_en bit is in the rtc well and is preserved after a power loss. like pwrbtn_sts the rtc_sts bit is cleared when rsmrst# goes low. the intel ? 6300ESB ich monitors both pwrok and rsmrst# to detect for power failures. when pwrok goes low, the pwrok_flr bit is set. when rsmrst# goes low, pwr_flr is set. power button s1 ? s5 always enabled as wake event gpi[0:n] s1 ? s5 gpe0_en register (after having gone to s5 through slp_en, but not after a power failure.) note: gpis that are in the core well are not capable of waking the system from sleep states where the core well is not powered. usb s1 ? s5 set usb1_en, usb 2_en and usb3_en bits in gpe0_en register ri# s1 ? s5 set ri_en bit in gpe0_en register ac?97 s1 ? s5 set ac?97_en bit in gpe0_en register secondary pme# s1 ? s5 set pme_en bit in gpe0_en register. smbalert# s1 ? s4 smb_wak_en in the gpe0 register. always enabled as wake event smbus slave message s1 ? s5 wake/smi# command always enabled as a wake event. note: smbus slave message may wake the system from s1-s5, as well as from s5 due to power button override. pme_b0 (internal usb ehci controller) s1 ? s5 set pme_b0_en bit in gpe0_en register. table 70. causes of wake events (sheet 2 of 2) cause states can wake from how enabled note: when in the s5 state due to a powerbutton override, the only wake events are power button, wake smbus slave message (01h), and hard reset smbus slave messages (03h, 04h). note: pme#, rtc, gpi[0:n], and ri# will be wake events from s5 only when it was entered through software setting the slp_en and slp_typ bits, or if there is a power failure.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 158 order number: 300641-004us 5.11.8 thermal management the intel ? 6300ESB ich has mechanisms to assist with managing thermal problems in the system. 5.11.8.1 thrm# signal the thrm# signal is used as a status input for a thermal sensor. based on the thrm# signal going active, the intel ? 6300ESB ich generates an smi# or sci (depending on sci_en). when the thrm_pol bit is set low, when the thrm# signal goes low, the thrm_sts bit will be set. this is an indicator that the thermal threshold has been exceeded. when the thrm_en bit is set, then when thrm_sts goes active, either an smi# or sci will be generated (depending on the sci_en bit being set). the power management software (bios or acpi) may then take measures to start reducing the temperature. examples include shutting off unwanted subsystems, or halting the processor. by setting the thrm_pol bit to high, another smi# or sci may optionally be generated when the thrm# signal goes back high. this allows the software (bios or acpi) to turn off the cooling methods. note: thrm# assertion will not cause a tco event message in s1-m, s3, or s4. the level of the signal will not be reported in the heartbeat message. 5.11.8.2 thrm# initiated passive cooling when the thrm# signal remains active for some time greater than two seconds and the intel ? 6300ESB ich is in the s0/g0/c0 state, then the intel ? 6300ESB ich enters an auto-throttling mode, in which it provides a duty cycle on the stpclk# signal. this will reduce the overall power consumption by the system, and should cool the system. the intended result of the cooling is that the thrm# signal should go back inactive. for all programmed values (001?111), thrm# going active will result in stpclk# active for a minimum time of 12.5% and a maximum of 87.5%. the period is 1024 pci clocks. thus, the stpclk# signal may be active for as little as 128 pci clocks or as much as 896 pci clocks. the actual slowdown (and cooling) of the processor w ill depend on the instruction stream, because the processor is allowed to finish the current instruction. furthermore, the intel ? 6300ESB ich waits for the stop-grant cycle before starting the count of the time the stpclk# signal is active. when thrm# goes inactive, the throttling will stop. table 71. transitions due to power failure state at power failure afterg3_en bit transition when power returns s0, s1, s3 1 0 s5 s0 s4 1 0 s4 s0 s5 1 0 s5 s0
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 159 5?intel ? 6300ESB ich note: there is a small window where the intel ? 6300ESB ich may assert stpclk# for one more throttling period after thrm# goes inactive. this is due to a sampling delay on thrm# (the signal is still active internally, but has just gone inactive externally). in case that the intel ? 6300ESB ich is already attempting throttling because the thtl_en bit is set, the duty cycle associated with the thrm# signal will have higher priority. when the intel ? 6300ESB ich is in the c2, or s1?s5 states, then no throttling will be caused by the thrm# signal being active. 5.11.8.3 thrm# override software bit the force_thtl bit allows the bios to force passive cooling, just as though the thrm# signal had been active for two seconds. when this bit is set, the intel ? 6300ESB ich will start throttling using the ratio in the thrm_dty field. when this bit is cleared the intel ? 6300ESB ich w ill stop throttling, unless the thrm# signal has been active for two seconds or when the thtl_en bit is set (indicating that acpi software is attempting throttling). 5.11.8.4 processor initiated passive cooling (via programmed duty cycle on stpclk#) using the thtl_en and thtl_dty bits, the intel ? 6300ESB ich may force a programmed duty cycle on the stpclk# signal. this will reduce the effective instruction rate of the processor and cut its power consumption and heat generation. see section 8.8.3.5, ?proc_cnt?processor control register? for more details on the programming of these bits. 5.11.8.5 active cooling active cooling involves fans. the gpio signals from the intel ? 6300ESB ich may be used to turn on/off a fan. 5.11.9 event input signal usage the intel ? 6300ESB ich has various input signals that trigger specific events. this section describes those signals and how they should be used. 5.11.9.1 pwrbtn# - power button the intel ? 6300ESB ich pwrbtn# signal operates as a ?fixed power button? as described in the acpi specification. pwrbtn# signal has a 16 ms debounce on the input. the state transition descriptions are included in the following table. note: transitions start as soon as the pwrbtn# is pressed (but after the debounce logic) and do not depend on when the power button is released.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 160 order number: 300641-004us power button override function when pwrbtn# is observed active for at least four consecutive seconds, then the state machine should unconditionally transition to the g2/s5 state, regardless of present state (s0?s4). in this case, the transition to the g2/s5 state should not depend on any particular response from the processor (such as a stop-grant cycle), nor any similar dependency from any other subsystem. a power button override will force a transition to s5 even when pwrok is not active . the pwrbtn# status is readable to check when the button is currently being pressed or has been released. the status is taken after the debounce, and is readable through the pwrbtn_lvl bit. note: the four second pwrbtn# assertion should only be used when a system lock-up has occurred. the four second timer starts counting when the intel ? 6300ESB ich is in a s0 state. when the pwrbtn# signal is asserted and held active when the system is in a suspend state (s1?s5), the assertion will cause a wake event. once the system has resumed to the s0 state, the four second timer will start. sleep button the acpi specification defines an optional sleep button. it differs from the power button in that it only is a request to go from s0 to s1?s4 (not s5). also, in an s5 state, the power button may wake the system, but the sleep button cannot. although the intel ? 6300ESB ich does not include a specific signal designated as a sleep button, one of the gpio signals may be used to create a ?control method? sleep button. see the acpi specification for implementation details. 5.11.9.2 ri# - ring indicate the ring indicator may cause a wake event (when enabled) from the s1?s5 states. ta b l e 7 3 shows when the wake event is generated or ignored in different states. when in the g0/s0/cx states, the intel ? 6300ESB ich will generate an interrupt based on ri# active, and the interrupt will be set up as a break event. table 72. transitions due to power button present state event transition/action comment s0/cx pwrbtn# goes low smi# or sci generated (depending on sci_en) software will typically initiate a sleep state. s1-s5 pwrbtn# goes low wake event. transitions to s0 state. standard wakeup g3 pwrbtn# pressed none no effect since no power. not latched nor detected. s0-s4 pwrbtn# held low for at least four consecutive seconds unconditional transition to s5 state. no dependence on processor (such as stop-grant cycles) or any other subsystem.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 161 5?intel ? 6300ESB ich 5.11.9.3 pme# - pci power management event the pme# signal comes from a pci device to request that the system be restarted. the pme# signal may generate an smi#, sci, or optionally a wake event. the event occurs when the pme# signal goes from high to low. no event is caused when it goes from low to high. the intel ? 6300ESB ich supports only one pme# signal which is shared between both the pci and the pci-x interfaces. in the ehci controller, there is an internal pme_b0 bit. this is separate from the external pme# signal and may cause the same effect. 5.11.9.4 sys_reset# signal sys_reset# is a new pin on the intel ? 6300ESB ich that is used to eliminate extra glue logic on the board. before the addition of this pin, a system reset was activated by external glue forcing the pwrok signal low after the reset button was pressed. this pin eliminates the need for that glue. as such, a sys_reset# event should look internally to our chip and externally to the system as when pwrok had gone low. when the sys_reset# pin is detected as active after the 16 ms debounce logic, the intel ? 6300ESB ich will attempt to perform a ?graceful? reset, by waiting up to 25 ms for the smbus to go idle. when the smbus is idle when the pin is detected active, the reset will occur immediately, otherwise the counter will start. when at any point during the count the smbus goes idle the reset will occur. when, however, the counter expires and the smbus is still active, a reset will be forced upon the system even though activity is still occurring. once a reset of this type has occurred, it cannot occur again until sys_reset# has been detected inactive after the debounce logic, and the system is back to a full s0 state as indicated by all of the pwrok inputs being active. 5.11.9.5 thrmtrip# signal when thrmtrip# goes active, the processor is indicating an overheat condition, and the intel ? 6300ESB ich will immediately transition to an s5 state. however, since the processor has overheated, it will not respond to the intel ? 6300ESB ich?s stpclk# pin with a stop grant special cycle. therefore, the intel ? 6300ESB ich will not wait for one. immediately upon seeing thrmtrip# low, the intel ? 6300ESB ich will initiate a transition to the s5 state, drive slp_s3#, slp_s4#, slp_s5# low, and set the cts bit. the transition will look like a power button override. it is extremely important that when a thrmtrip# event occurs, the intel ? 6300ESB ich power down immediately without following the normal s0 -> s5 path. this path may be taken in parallel, but the intel ? 6300ESB ich must immediately enter a power down state. it will do this by driving slp_s3#, slp_s4#, and slp_s5# immediately after sampling thrmtrip# active. table 73. transitions due to ri# signal present state event ri_en event s0 ri# active x ignored s1-s5 ri# active 0 1 ignored wake event note: filtering/debounce on ri# will not be done in the intel ? 6300ESB ich. can be in modem or external.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 162 order number: 300641-004us when the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the intel ? 6300ESB ich, are no longer executing cycles properly. therefore, when thrmtrip# fires and the intel ? 6300ESB ich is relying on state machine logic to perform the power down, the state machine may not be working and the system will not power down. the intel ? 6300ESB ich will follow this flow for thrmtrip#. 1. at boot (pxpcirst# low), thrmtrip# ignored. 2. after power-up (pxpcirst# high), when thrmtrip# sampled active, slp_s3#, slp_s4#, and slp_s5# fire, and normal sequence of sleep machine starts. 3. until sleep machine enters the s5 state, slp_s3#, slp_s4#, and slp_s5# stay active, even when thrmtrip# is now inactive. this is the equivalent of ?latching? the thermal trip event. 4. when s5 state reached, go to step #1, otherwise stay here. when the intel ? 6300ESB ich never reaches s5, the intel ? 6300ESB ich will not reboot until power is cycled. a processor thermal trip event will: ? set the afterg3_en bit ? clear the pwrbtn_sts bit ? clear all the gpe0_en and gpe1_en register bits ? clear the smb_wak_sts bit only when smb_wak_sts was set due to smbus slave receiving message and not set due to smbalert. note: the thrmtrip# pin must be glitch free. 5.11.10 alt access mode before entering a low power state, several registers from powered down parts may need to be saved. in the majority of cases, this is not an issue, as registers have read and write paths. however, several of the isa compatible registers are either read only or write only. to get data out of write-only registers, and to restore data into read-only registers, the intel ? 6300ESB ich implements an alt access mode. when the alt access mode is entered and exited after reading the registers of the intel ? 6300ESB ich timer (8254), the timer starts counting faster (13.5 ms). the following steps listed below may cause problems: 1. bios enters alt access mode for reading the intel ? 6300ESB ich timer related registers. 2. bios exits alt access mode. 3. bios continues through the execution of other needed steps and passes control to the os. after getting control in step #3, when the os does not reprogram the system timer again the timer ticks may be happening faster than expected. for example dos and its associated software assume that the system timer is running at 54.6 ms and as a result the timeouts in the software may be happening faster than expected. for some other oss, such as dos, the bios should restore the timer back to 54.6 ms before passing control to the os. when the bios is entering alt access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from alt access mode.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 163 5?intel ? 6300ESB ich 5.11.10.1write only registers with read paths in alt access mode the registers described in table 76 have read paths in alt access mode. the access number field in the table indicates which register will be returned per access to that port. table 74. write only registers with read paths in alt access mode (sheet 1 of 2) restore data restore data i/o add r # of rd s acces s data i/o add r # of rd s acces s data 00h 2 1 dma chan 0 base address low byte 40h 7 1 timer counter 0 status, bits [5:0] 2 dma chan 0 base address high byte 2 timer counter 0 base count low byte 01h 2 1 dma chan 0 base count low byte 3 timer counter 0 base count high byte 2 dma chan 0 base count high byte 4 timer counter 1 base count low byte 02h 2 1 dma chan 1 base address low byte 5 timer counter 1 base count high byte 2 dma chan 1 base address high byte 6 timer counter 2 base count low byte 03h 2 1 dma chan 1 base count low byte 7 timer counter 2 base count high byte 2 dma chan 1 base count high byte 41h 1 timer counter 1 status, bits [5:0] 04h 2 1 dma chan 2 base address low byte 42h 1 timer counter 2 status, bits [5:0] 2 dma chan 2 base address high byte 70h 1 bit 7 = nmi enable, bits [6:0] = rtc address 05h 2 1 dma chan 2 base count low byte c4h 2 1 dma chan 5 base address low byte 2 dma chan 2 base count high byte 2 dma chan 5 base address high byte 06h 2 1 dma chan 3 base address low byte c6h 2 1 dma chan 5 base count low byte 2 dma chan 3 base address high byte 2 dma chan 5 base count high byte 07h 2 1 dma chan 3 base count low byte c8h 2 1 dma chan 6 base address low byte 2 dma chan 3 base count high byte 2 dma chan 6 base address high byte notes: 1. the ocw1 register must be read before entering alt access mode. 2. bits 5, 3, 1, and 0 return zero.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 164 order number: 300641-004us 5.11.10.2programmable interrupt controller (pic) reserved bits many bits within the pic are reserved, and must have certain values written in order for the pic to operate properly. therefore, there is no need to return these values in alt access mode. when reading pic registers from 20h and a0h, the reserved bits shall return the values listed in the following table. 08h 6 1 dma chan 0-3 command 2 cah 2 1 dma chan 6 base count low byte 2 dma chan 0-3 request 2 dma chan 6 base count high byte 3 dma chan 0 mode: bits(1:0) = ?00? cch 2 1 dma chan 7 base address low byte 4 dma chan 1 mode: bits(1:0) = ?01? 2 dma chan 7 base address high byte 5 dma chan 2 mode: bits(1:0) = ?10? ceh 2 1 dma chan 7 base count low byte 6 dma chan 3 mode: bits(1:0) = ?11?. 2 dma chan 7 base count high byte 20h 12 1 pic icw2 of master controller d0h 6 1 dma chan 4-7 command 2 2 pic icw3 of master controller 2 dma chan 4-7 request 3 pic icw4 of master controller 3 dma chan 4 mode: bits(1:0) = ?00? 4 pic ocw1 of master controller 1 4 dma chan 5 mode: bits(1:0) = ?01? 5 pic ocw2 of master controller 5 dma chan 6 mode: bits(1:0) = ?10? 6 pic ocw3 of master controller 6 dma chan 7 mode: bits(1:0) = ?11?. 7 pic icw2 of slave controller 8 pic icw3 of slave controller 9 pic icw4 of slave controller 10 pic ocw1 of slave controller 1 11 pic ocw2 of slave controller 12 pic ocw3 of slave controller table 74. write only registers with read paths in alt access mode (sheet 2 of 2) restore data restore data i/o add r # of rd s acces s data i/o add r # of rd s acces s data notes: 1. the ocw1 register must be read before entering alt access mode. 2. bits 5, 3, 1, and 0 return zero.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 165 5?intel ? 6300ESB ich 5.11.10.3read-only registers with write paths in alt access mode the registers described in ta b l e 7 6 have write paths to them in alt access mode. software will restore these values after returning from a powered down state. these registers must be handled special by software. when in normal mode, writing to the base address/count register also writes to the current address/count register. therefore, the base address/count must be written first, then the part is put into alt access mode and the current address/count register is written. 5.11.11 system power supplies, planes, and signals 5.11.11.1power plane control with slp_s3#, slp_s4# and slp_s5# the slp_s3# output signal may be used to cut power to the system core supply, since it will only go active for the str state (typically mapped to acpi s3). power must be maintained to system memory, the intel ? 6300ESB ich resume well, and to any other circuits that need to generate wake signals from the str state. cutting power to the core may be done through the power supply, or by external fets to the motherboard. the slp_s4# or slp_s5# output signal may be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the memory may be done through the power supply, or by external fets to the motherboard. 5.11.11.2pwrok signal the pwrok input should go active based on the core supply voltages becoming valid. pwrok should go active at least 16 ms after the power is ensured valid. note: please review these notes regarding the pwrok signal: table 75. pic reserved bits return values pic reserved bits value returned icw2(2:0) 000 icw4(7:5) 000 icw4(3:2) 00 icw4(0) 0 ocw2(4:3) 00 ocw3(7) 0 ocw3(5) reflects bit 6 ocw3(4:3) 01 table 76. register write accesses in alt access mode i/o address register write value 08h dma status register for channels 0-3. d0h dma status register for channels 4-7.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 166 order number: 300641-004us 1. traditional designs have a reset button logically ands with the pwrok signal from the power supply and the processor?s voltage regulator module. when this is done with the intel ? 6300ESB ich, the pwrok_flr bit will be set. the intel ? 6300ESB ich treats this internally as though the rsmrst# signal had gone active. however, it is not treated as a full power failure. when pwrok goes inactive and then active (but rsmrst# stays high), then the intel ? 6300ESB ich will reboot (regardless of the state of the afterg3 bit). when the rsmrst# signal also goes low before pwrok goes high, then this is a full power failure and the reboot policy is controlled by the afterg3 bit. 2. pwrok and rsmrst# are sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the intel ? 6300ESB ich. 5.11.11.3vrmpwrgd signal the vrmpwrgd signal is not implemented in the intel ? 6300ESB ich. vrmpwrgd need to be pulled up to vcc in order to disable internal legacy logic. if not pulled up, this logic may come up in an unknown state.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 167 5?intel ? 6300ESB ich 5.11.11.4controlling leakage and power consumption during low- power states to control leakage in the system, various signals will tri-state or go low during some low-power states. general principles: ? all signals going to powered down planes (either internally or externally) must be either tri-stated or driven low. ? signals with pull-up resistors should not be low during low-power states. this is to avoid the power consumed in the pull-up resistor. ? buses should be halted (and held) in a known state to avoid a floating input (perhaps to some other device). floating inputs may cause extra power consumption. based on the above principles, the following measures are taken: ? during s3 (str), all signals attached to powered down planes will be tri-stated or driven low. 5.11.12 clock generators the clock generator is expected to provide the frequencies shown in ta b l e 7 7 . table 77. intel ? 6300ESB ich clock inputs clock domain frequency source description clk66 66 mhz main clock generator clock for hub interface. should be running in all cx states. stopped in s3 ~ s5 based on slp_s3# assertion. this signal is not 5v tolerant. pciclk 33 mhz main clock generator free-running pci clock to the intel ? 6300ESB ich. provides timing for all transactions on the internal primary pci bus, as well as units inside the intel ? 6300ESB ich. this clock may be stopped in s3, s3 or s5 states. this signal is not 5v tolerant. pxpciclk 66 mhz main clock generator free-running pci clock to the intel ? 6300ESB ich. provides timing for all transactions on the internal primary pci-x bus, as well as units inside the intel ? 6300ESB ich. this clock may be stopped in s3, s3 or s5 states. this signal is not 5v tolerant. clk48 48 mhz main clock generator used by usb controllers. stopped in s3 ~ s5 based on slp_s3# assertion. clk14 14.318 mhz main clock generator used by acpi timers. stopped in s3 ~ s5 based on slp_s3# assertion. ac_bit_clk 12.288 mhz ac?97 codec ac?97 bit clock: 12.288 mhz serial data clock generated by the external codecs. integrated pull down resistor.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 168 order number: 300641-004us 5.11.13 legacy power management theory of operation 5.11.13.1overview instead of relying on acpi software, legacy power management uses bios and various hardware mechanisms. the intel ? 6300ESB ich has a greatly simplified method for legacy power management compared with previous component generations. the scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. however, the os is assumed to be at least apm enabled. without apm calls, there is no quick way to know when the system is idle between keystrokes. the intel ? 6300ESB ich does not support the burst modes found in previous components. 5.11.13.2apm feature notes the intel ? 6300ESB ich has a timer that, when enabled by the 1min_en bit in the smi control and enable register, will generate an smi# once per minute. the smi handler may check for system activity by reading the devact_sts register. when none of the system bits are set, the smi handler may increment a software counter. when the counter reaches a sufficient number of consecutive minutes with no activity, the smi handler may then put the system into a lower power state. when there is activity, various bits in the devact_sts register will be set. software clears the bits by writing a one to the bit position. the devact_sts register allows for monitoring various internal devices, or super i/o devices (sp, pp, fdc) on lpc or pci, keyboard controller accesses, or audio functions on lpc or pci. other pci activity may be monitored by checking the pci interrupts. 5.12 system management (d31:f0) 5.12.1 overview of system management functions the intel ? 6300ESB ich provides various functions to make a system easier to manage and to lower the total cost of ownership (tco) of the system. it builds on functions that have been found in prior generations of serial interface acpi-compatible processor system monitor components products, such as the lm78 and lm80. features and functions may be augmented through external a/d converters and gpio, as well as an external microcontroller. the intel ? 6300ESB ich supports the following features and functions: ? first hard coded timer to generate smi# after programmable time. ? first timeout causes smi#. allows for smm-based recovery from os lockup. ? os-based software agent accesses the intel ? 6300ESB ich to periodically reload timer. ? ability for smm handler to generate ?tco? interrupt to os. ? allows for os-based code augmentation. ? ability for os to generate smi#. ? call-back from os to tco code in smm handler. ? second hard coded timer to generate reboot after programmable time.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 169 5?intel ? 6300ESB ich ? used only after first timeout occurs. ? second timeout allows for system ?reset and reboot? when a hardware error is detected. various system states are preserved through this special reset to allow for possible error detection and correction. ? reset associated with ?reboot? may attempt to preserve some registers for diagnostic purposes. ? smi# handler must periodically reload second timer to prevent ?reboot? (timeout during smi is assumed as broken processor or stuck hardware). ? option to generate limited reset when second timeout occurs. ? ability to detect a ?broken? processor. ? detects when the processor fails to restart after it has been reset. ? when processor failure detected, option to pulse a gpio or send smbus message. the smbus message may be used to indicate to an external lan controller to send a distress message. the gpio may control an led with optional blink. ? ability to handle various errors (such as ecc errors) indicated by mch. ? can generate smi# or tco interrupt. ? intruder detect input when the system cover is removed. ? may generate tco interrupt or smi#. ? ability for tco messages to coexist with standard smbus devices. ? detection of bad fwh programming. done by checking that data on the first read is not ffh. 5.12.2 tco signal usage 5.12.2.1 intruder# signal this signal may be used to detect the chassis being opened. the activation of this signal may be used to cause an smi#, and is reported through the heartbeat/event mechanism. when smi# is desired, the signal?s level may be read, so this may be used as a type of general purpose input. 5.12.2.2 pin straps some the tco functions are decided at powerup (rising edge of pwrok). see section 3.21, ?pin straps? for specific assignments of the pin straps. 5.12.2.3 smlink signals the intel ? 6300ESB ich supports tco compatible mode connectivity. the intel ? 6300ESB ich supports lan controllers. a lan controller can be used to receive or retrieve tco message or information on host smbus if needed. in legacy tco mode messages will be driven via smlink. for the intel ? 6300ESB ich, messages on this link will use smbus protocol at the rates described in section 5.12, ?system management (d31:f0)? for tco compatible mode. note: all mention of ?lan? refers to an external lan controller.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 170 order number: 300641-004us 5.12.3 tco theory of operation 5.12.3.1 overview the system management functions are designed to allow the system to diagnose failing subsystems. the intent of this logic is that some of the system management functionality be provided without the aid of an external microcontroller. 5.12.3.2 detecting a system lockup when the processor is reset, it is expected to fetch its first instruction. when the processor fails to fetch the first instruction after reset, the tco timer will timeout twice and the intel ? 6300ESB ich w ill assert pxpcirst#. when tco reboots are not enabled, then the intel ? 6300ESB ich will either: ? the smlink will still send out the first 8 bits of the message. after the eighth bit, the logic will stall because there is no integrated lan controller to send the ack. the logic will abort the transfer. external logic may monitor the toggling and use that to drive led. ? if an lan controller is connected: send the appropriate message to the lan controller. when tco reboots are enabled, then the intel ? 6300ESB ich will attempt to reboot the system. note: when the no-reboot bit (d31:f0:offset d4:bit 1) is set (no reboots are intended), and the second_to_sts bit (tco i/o offset 06h, bit 1) is set, and the doacpu_sts bit (tco i/o offset 06h, bit 2), the intel ? 6300ESB ich will indicate this in the tco message by setting the cpu missing bit in the message. when the no-reboot bit is not set (reboots intended), and the second_to_sts bit is set, the intel ? 6300ESB ich will attempt to reboot. after the reboot, the second_to_sts bit will still be set. when the processor fails to fetch the first instruction, the doa_cpu_sts bit is set, and when the tco timer times out (actually for the third time, the first 2 times caused the second_to_sts bit to be set), the intel ? 6300ESB ich will set the cpu missing event bit for the tco message. 5.12.3.3 handling an os lockup under some conditions, the os may lock up. to handle this, the tco timer is used with the following algorithm: 1. bios programs the tco timer, through the tco_tmr register, with an initial value. generally, this will probably be set to four seconds, but could be greater. 2. an os-based software agent periodically writes to the tco_rld register to reload the timer and keep it from generating the smi#. the software agent may read the tco_rld register to see when it is close to timing out, and possibly determine if the time-out should be increased. 3. when the timer reaches 0, an smi# may be generated. this should only occur when the os was not able to reload the timer. it is assumed that the os will not be able to reload the timer if it has locked up. 4. upon generating the smi#, the tco timer automatically reloads with the value in the tco_tmr register and start counting down. 5. the smi handler may then: a. read the timeout bit in the tco_sts register to check that the smi# was caused by the tco timer.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 171 5?intel ? 6300ESB ich b. write to the tco_rld register to reload the timer to make sure the tco timer does not reach 0 again. c. attempt to recover. may need to periodically reload the tco timer. the exact recovery algorithm will be system-specific. when after the timeout smi is generated, and the tco timer again reaches 0, and reboots are enabled, the system management logic will reset (and reboot) the system. this would be in the case where the processor or system is locked up. during every boot, bios should read the second_to_sts bit in the tco_sts register to see if this is normal boot or a reboot due to the timeout. 5.12.3.4 handling an intruder the intel ? 6300ESB ich has an input signal, intruder#, that may be attached to a switch that is activated by the system?s case being open. this input has a two rtc clock debounce. when intruder# goes active (after the debouncer), this will set the intrd_det bit in the tco_sts register. the intrd_sel bits in the tco_cnt register may enable the intel ? 6300ESB ich to cause an smi# or interrupt. the bios or interrupt handler may then cause a transition to the s5 state by writing to the slp_en bit. the software may also directly read the status of the intruder# signal (high or low) by clearing and then reading the intrd_det bit. this allows the signal to be used as a gpi when the intruder function is not required. when the intruder# signal goes inactive some point after the intrd_det bit is written as a 1, the intrd_det signal will go to a 0 when intruder# input signal goes inactive. note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. note: the intrd_det bit resides in the intel ? 6300ESB ich?s rtc well, and is set and cleared synchronously with the rtc clock. thus, when software attempts to clear intrd_det (by writing a ?1? to the bit location) there may be as much as two rtc clocks (about 65 s) delay before the bit is actually cleared. also, the intruder# signal should be asserted for a minimum of 1 ms in order to ensure that the intrd_det bit will be set. note: when the intruder# signal is still active when software attempts to clear the intrd_det bit, the bit will remain set and the smi will be generated again immediately. the smi handler may clear the intrd_sel bits to avoid further smis. however, when the intruder# signal goes inactive and then active again, there will not be further smis, since the intrd_sel bits would select that no smi# be generated. 5.12.3.5 detecting improper fwh programming the intel ? 6300ESB ich may detect the case where the fwh is not programmed. this will result in the first instruction fetched to have a value of ffh. when this occurs, the intel ? 6300ESB ich will set the bad_bios bit, which may then be reported through the heartbeat and event reporting via an lan controller. 5.12.3.6 handling an ecc error or other memory error the host controller provides a message to indicate that it would like to cause an smi#, sci, serr#, or nmi. the software must check the host controller as to the exact cause of the error.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 172 order number: 300641-004us 5.12.4 heartbeat and event reporting through smlink/ smbus smlink signals are implemented on the intel ? 6300ESB ich ich to support tco compatible mode. heartbeat and event reporting are accomplished via the smlink signals. 5.12.4.1 overview 5.12.4.1.1 tco compatible mode the intel ? 6300ESB ich may function directly with a lan controller to report messages to a network management console without the aid of the system processor. this is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. note: a system that has locked up and cannot be restarted with a power button press is assumed to have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond the intel ? 6300ESB ich?s recovery mechanisms. the basic scheme is for the intel ? 6300ESB ich to send specific messages through the smlink i/f to the lan. upon receiving the smlink message, the lan has a prepared ethernet message that it may send to a network management console. the prepared message is stored in a non-volatile memory connected directly to the lan. messages will be sent by the intel ? 6300ESB ich to a lan either because a specific event has occurred (see tab le 78 ), or they will be sent periodically (also known as a heartbeat). the event and heartbeat messages will have exactly the same form. whenever an event occurs that causes the intel ? 6300ESB ich to send a new message, it will increment its seq[3:0] field. for heartbeat messages, the sequence number will not increment. table 78. event transitions that cause messages event assertion ? deassertion ? comments intruder# pin yes no must be in ?heartbeat mode? (g1 or hung g0). thrm# pin yes yes must be in ?heartbeat mode?. note that the thrm# pin is isolated when the core power is off, thus preventing this event in s3-s5. also, the thrm# pin is sampled with the pci clock, which means that thrm# transitions cannot be detected in s1-m. watchdog timer expired yes no (na) ?heartbeat mode? entered send_now bit yes na occurs in g0 gpio[11]/smbalert# pin yes yes must be in ?heartbeat mode? (g1 or hung g0). cpu_pwr_flr yes no ?heartbeat mode? entered {intel ? 6300ESB ich dcn36}. note: the gpio[11]/smbalert# pin will trigger an event message (when enabled by the gpio11_alert_disable bit) regardless of whether it is configured as a gpi or not.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 173 5?intel ? 6300ESB ich when a triggering event occurs while a message is already being generated and sent, the new event may not appear in the current message. if not, then a second message will be generated, with the seq[3:0] field incremented, to report the new event. the following rules/steps apply when the system is in a g0 state and the policy is for the intel ? 6300ESB ich to reboot the system after a hardware lockup: 1. upon detecting the lockup the second_to_sts bit will be set. the intel ? 6300ESB ich may send up to 1 event message to the lan. the intel ? 6300ESB ich will then attempt to reboot the processor. 2. when the reboot at step 1 is successful then the bios should clear the second_to_sts bit. this will prevent any further heartbeats from being sent. the bios may then perform addition recovery/boot steps. warning: it is important that the bios clears the second_to_sts bit, as the messages (alerts) will interfere with the lan device driver from working properly. the alerts reset part of the lan and would prevent an os?s device driver from sending or receiving some messages. 3. when the reboot attempt in step 1 is not successful, then the timer will timeout a third time. at this point the system has locked up and was unsuccessful in rebooting. the intel ? 6300ESB ich will not attempt to automatically reboot again. the intel ? 6300ESB ich will start sending a message every heartbeat period (30- 32 seconds). the heartbeats will continue until some external intervention occurs (reset, power failure, etc.). 4. after step 3 (unsuccessful reboot after third timeout), when the user does a power button override, the system will go to an s5 state. the intel ? 6300ESB ich will continue sending the messages every heartbeat period. 5. after step 4 (power button override after unsuccessful reboot) when the user presses the power button again, the system should wake to an s0 state and the processor should start executing the bios. 6. when step 5 (power button press) is successful in waking the system, the intel ? 6300ESB ich will continue sending messages every heartbeat period until the bios clears the second_to_sts bit. 7. when step 5 (power button press) is unsuccessful in waking the system, the intel ? 6300ESB ich will continue sending a message every heartbeat period. the intel ? 6300ESB ich will not attempt to automatically reboot again. the intel ? 6300ESB ich will start sending a message every heartbeat period (30-32 seconds). the heartbeats will continue until some external intervention occurs (reset, power failure, etc.). 8. after step 3 (unsuccessful reboot after third timeout), when a reset is attempted (using a button that pulses pwrok low or through the message on the smbus slave i/f), the intel ? 6300ESB ich w ill attempt to reset the system. 9. after step 8 (reset attempt), when the reset is successful, then the bios will be run. the intel ? 6300ESB ich w ill continue sending a message every heartbeat period until the bios clears the second_to_sts bit. 10. after step 8 (reset attempt), when the reset is unsuccessful, then the intel ? 6300ESB ich will continue sending a message every heartbeat period. the intel ? 6300ESB ich will not attempt to reboot the system again without external intervention.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 174 order number: 300641-004us the following rules/steps apply when the system is in a g0 state and the policy is for the intel ? 6300ESB ich to not reboot the system after a hardware lockup: 1. upon detecting the lockup the second_to_sts bit will be set. the intel ? 6300ESB ich will send a message with the watchdog (wd) event status bit set (and any other bits that must also be set). this message will be sent as soon as the lockup is detected, and will be sent with the next (incremented) sequence number. 2. after step 1, the intel ? 6300ESB ich w ill send a message every heartbeat period until some external intervention occurs. 3. rules/steps 4-10 apply when no user intervention (resets, power button presses, smbus reset messages) occur after a third timeout of the watchdog timer. when the intervention occurs before the third timeout, then jump to rule/step11. 4. after step 3 (third timeout), when the user does a power button override, the system will go to an s5 state. the intel ? 6300ESB ich will continue sending heartbeats at this point. 5. after step 4 (power button override), when the user presses the power button again, the system should wake to an s0 state and the processor should start executing the bios. 6. when step 5 (power button press) is successful in waking the system, the intel ? 6300ESB ich will continue sending heartbeats until the bios clears the second_to_sts bit. 7. when step 5 (power button press) is unsuccessful in waking the system, the intel ? 6300ESB ich will continue sending heartbeats. the intel ? 6300ESB ich will not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). 8. after step 3 (third timeout), when a reset is attempted (using a button that pulses pwrok low or through the message on the smbus slave i/f), the intel ? 6300ESB ich will attempt to reset the system. 9. when step 8 (reset attempt) is successful, then the bios will be run. the intel ? 6300ESB ich will continue sending heartbeats until the bios clears the second_to_sts bit. 10. when step 8 (reset attempt), is unsuccessful, then the intel ? 6300ESB ich will continue sending heartbeats. the intel ? 6300ESB ich will not attempt to reboot the system again without external intervention. 11. this and the following rules/steps apply when the user intervention (power button press, reset, smbus message, etc.) occur prior to the third timeout of the watchdog timer. 12. after step 1 (second timeout), when the user does a power button override, the system will go to an s5 state. the intel ? 6300ESB ich will continue sending heartbeats at this point. 13. after step 12 (power button override), when the user presses the power button again, the system should wake to an s0 state and the processor should start executing the bios. 14. when step 13 (power button press) is successful in waking the system, the intel ? 6300ESB ich will continue sending heartbeats until the bios clears the second_to_sts bit. 15. when step 13 (power button press) is unsuccessful in waking the system, the intel ? 6300ESB ich will continue sending heartbeats. the intel ? 6300ESB ich will not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). 16. after step 1 (second timeout), when a reset is attempted (using a button that pulses pwrok low or through the message on the smbus slave i/f), the intel ? 6300ESB ich will attempt to reset the system. 17. when step 16 (reset attempt) is successful, then the bios will be run. the intel ? 6300ESB ich will continue sending heartbeats until the bios clears the second_to_sts bit. 18. when step 16 (reset attempt), is unsuccessful, then the intel ? 6300ESB ich will continue sending heartbeats. the intel ? 6300ESB ich will not attempt to reboot the system again without external intervention.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 175 5?intel ? 6300ESB ich the following rules will apply when the system is in a g1 (s1-s4) state: 1. the intel ? 6300ESB ich will send a heartbeat message every heartbeat period (30-32 seconds). 2. when an event occurs prior to the system being shut down, the intel ? 6300ESB ich will immediately send another event message with the next (incremented) sequence number. 3. after the event, it will resume sending heartbeat messages. note: there is a boundary condition when a hardware event (event or heartbeat) happens right as the system is transitioning into a g0 state. in this condition, the hardware will send messages even though the system will be in a g0 state (and the status bits could potentially indicate that). normally the intel ? 6300ESB ich will not send heartbeats in the g0 state (except in the case of a lockup). note: a spurious alert could occur in the following sequence: a. the processor has initiated an alert using the send_now bit b. during the alert, the thrm#, intruder# or gpi[11] changes state c. the system then goes to a non-s0 state. once the system transitions to the non-s0 state, it may send a single alert with an incremented sequence number. note: an inaccurate alert message may be generated in the following scenario: a. the system successfully boots after a second watchdog timeout occurs. b. pwrok goes low (typically due to a reset button press) or a power button override occurs (before the second_to_sts bit is cleared). c. an alert message indicating that the processor is missing or locked up is generated with a new sequence number.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 176 order number: 300641-004us 5.13 general purpose i/o 5.13.1 gpio mapping table 79. gpio implementation (sheet 1 of 2) gpio type alternate function power well tolera nt notes gpi[0] input only pxreq[2]# core 5.0 v gpio_use_sel bit 0 enables req/gnt[a]# pair. input active status read from gpe0_sts register bit 16. input active high/low set through gpi_inv register bit 0. note: gpeo_sts register, section 8.8.3.7 gpi_inv register, section 8.10.6 gpi[1] input only pxreq[3]# core 5.0 v gpio_use_sel bit 1 enables req/gnt[b]# pair. input active status read from gpe0_sts register bit 17 input active high/low set through gpi_inv register bit 1. gpi[2:5] input only pirq[e:h]# core 5.0 v gpio_use_sel bits [2:5] enable pirq[e:h]#. input active status read from gpe0_sts reg. bits [18:21]. input active high/low set through gpi_inv reg. bit [2:5]. gpi[6] input only unmuxed core 3.3 v input active status read from gpe0_sts register bit 22. input active high/low set through gpi_inv register bit 6. gpi[7] input only unmuxed core 3.3 v input active status read from gpe0_sts register bit 23. input active high/low set through gpi_inv register bit 7 gpi[8] input only unmuxed resum e 3.3 v input active status read from gpe0_sts register bit 24. input active high/low set through gpi_inv register bit 8. gpi[11] input only smbalert# resum e 3.3 v gpio_use_sel bit 11 enables smbalert# input active status read from gpe0_sts register bit 27. input active high/low set through gpi_inv register bit 11. gpi[12] input only unmuxed resum e 3.3 v input active status read from gpe0_sts register bit 28. input active high/low set through gpi_inv register bit 12. gpi[13] input only unmuxed resum e 3.3 v input active status read from gpe0_sts register bit 29. input active high/low set through gpi_inv register bit 13. notes: 1. gpio[0:7], gpio[16:21, 23], and gpio[32:43] are in the core well. 2. gpio[8:13] and gpio[24:28] are in the suspend well. 3. core-well gpio are 5v tolerant, except for gpio[7:6] and [32:43]. 4. resume-well gpio are not 5v tolerant. 5. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 177 5?intel ? 6300ESB ich gpo[16] outpu t only pxgnt[2]# core 5.0 v output controlled through gp_lvl register bit 16. ttl driver output note: gp_lvl register, section 8.10.4 gpo[17] outpu t only pxgnt[3]# core 5.0 v output controlled through gp_lvl register bit 17. ttl driver output gpo[18] outpu t only unmuxed core 5.0 v output controlled through gp_lvl register bits [18:19]. ttl driver output gpo[19] outpu t only unmuxed core 5.0 v output controlled through gp_lvl register bits [18:19]. ttl driver output gpo[20 outpu t only unmuxed core 5.0 v output controlled through gp_lvl register bit 20. ttl driver output gpo[21] outpu t only unmuxed core 5.0 v output controlled through gp_lvl register bit 21. ttl driver output gpio[23 outpu t only unmuxed core 5.0 v output controlled through gp_lvl register bit [23]. ttl driver output gpio[24] i/o unmuxed resum e 3.3 v input active status read from gp_lvl register bit 24. output controlled through gp_lvl register bit 24. ttl driver output gpio[25] i/o unmuxed resum e 3.3 v blink enabled through gpo_blink register bit 25. input active status read from gp_lvl register bit 25 output controlled through gp_lvl register bit 25. ttl driver output gpio[27:2 8] i/o unmuxed resum e 3.3 v input active status read from gp_lvl register bits [27:28] output controlled through gp_lvl register bits [27:28] ttl driver output gpio[32] i/o wdt_tout# core 3.3 v gpio[36:3 3] i pxirq[3:0]# core 3.3 v gpio[39:3 7] i/o unmuxed core 3.3 v gpio[43:4 0] i/o unmuxed core 3.3 v these gpios have high strength output capability (for driving leds) gpio[57:5 6] od unmuxed resum e and rtc 3.3 v table 79. gpio implementation (sheet 2 of 2) gpio type alternate function power well tolera nt notes notes: 1. gpio[0:7], gpio[16:21, 23], and gpio[32:43] are in the core well. 2. gpio[8:13] and gpio[24:28] are in the suspend well. 3. core-well gpio are 5v tolerant, except for gpio[7:6] and [32:43]. 4. resume-well gpio are not 5v tolerant. 5. gpio[56:57] pads are in the suspend well, the register bits are in the rtc well.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 178 order number: 300641-004us 5.13.2 power wells some gpios exist in the resume power plane. care must be taken to make sure gpio signals are not driven high into powered-down planes. some intel ? 6300ESB ich gpios may be connected to pins on devices that exist in the core well. when these gpios are outputs, there is a danger that a loss of core power (pwrok low) or a power button override event will result in the intel ? 6300ESB ich driving a pin to a logic ?1? to another device that is powered down. 5.13.3 smi# and sci routing the routing bits for gpio[0:15] allow an input to be routed to smi# or sci, or neither. see section 8.8.3.3 for the routing register note: a bit may be routed to either an smi# or an sci, but not both. 5.13.4 triggering gpio[0:15] have ?sticky? bits on the input. see section 8.8.3.7 for the gpe0_sts register. as long as the signal goes active for at least 2 clocks, the intel ? 6300ESB ich will keep the sticky status bit active. the active level (high or low) can be selected via the gp_inv register. if the system is in an s0 or s1-d state, the gpi are sampled at 33 mhz, so the signal only needs to be active for about 60 ns to be latched. in the s3-s5 states, the gpi are sampled at 32.768 khz, and thus must be active for at least 61 microseconds to be latched. note: gpis that are in the core well are not capable of waking the system from sleep states where the core well is not powered. if the input signal is still active when the latch is cleared, it will again be set (another edge is not required). this makes these signals level? triggered inputs. 5.14 ide controller (d31:f1) 5.14.1 overview the intel ? 6300ESB ich ide controller features two sets of interface signals (primary and secondary) that may be independently enabled, tri-stated or driven low. the intel ? 6300ESB ich ide controller supports both legacy mode and native mode ide interface. in native mode, the ide controller is a fully pci compliant software interface and does not use any legacy i/o or interrupt resources. the ide interfaces of the intel ? 6300ESB ich may support several types of data transfers: programmed i/o (pio): processor is in control of the data transfer. 8237 style dma: dma protocol that resembles the dma on the isa bus, although it does not use the 8237 in the intel ? 6300ESB ich. this protocol off loads the processor from moving data. this allows higher transfer rate of up to 16 mbytes/s.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 179 5?intel ? 6300ESB ich ultra ata/33: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 33 mbytes/s. ultra ata/66: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 66 mbytes/s. ultra ata/100: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 100 mbytes/s. 5.14.2 pio transfers 5.14.2.1 overview the intel ? 6300ESB ich ide controller includes both compatible and fast timing modes. the fast timing modes may be enabled only for the ide data ports. all other transactions to the ide registers are run in single transaction mode with compatible timings. up to two ide devices may be attached per ide connector (drive 0 and drive 1). the idetim and sidetim registers permit different timing modes to be programmed for drive 0 and drive 1 of the same connector. the ultra ata/33/66/100 synchronous dma timing modes may also be applied to each drive by programming the ide i/o configuration register and the synchronous dma control and timing registers. when a drive is enabled for synchronous dma mode operation, the dma transfers are executed with the synchronous dma timings. the pio transfers are executed using compatible timings or fast timings when also enabled. 5.14.2.2 ide port decode the command and control block registers are accessed differently depending on the decode mode, which is selected by the programming interface configuration register (offset 09h). note: the primary and secondary channels are controlled by separate bits, allowing one to be in native mode and the other in legacy mode simultaneously. 5.14.2.3 ide legacy mode and native mode the intel ? 6300ESB ich ide controller supports both legacy mode and pci native mode. in legacy mode, the command and control block registers are accessible at fixed i/o addresses, may not be accessed through the i/o bars. these blocks are decoded when i/o space is enabled through the p-ata function?s configuration space and ata decode is enabled through the ptim/stim registers, bit 15. an access to these addresses results in the assertion of the appropriate chip select (cs1#/cs3#) and the command strobes (dior#, diow#). there are two i/o ranges for each ide cable: the command block, which corresponds to the cs1p#/cs1s# chip select, and the control block, which corresponds to the cs3p#/cs3s# chip select. the command block is an 8 byte range, while the control block is a 4 byte range. ? command block offset: 01f0h for primary, 0170h for secondary ? control block offset: 03f4h for primary, 0374h for secondary tab l e 8 0 and ta b l e 8 1 specify the registers and transaction timings as they affect the intel ? 6300ESB ich hardware definition.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 180 order number: 300641-004us note: the data register (i/o offset 00h) should be accessed using 16-bit or 32-bit i/o instructions. all other registers should be accessed using 8-bit i/o instructions. note: these registers are implemented in the ide device. therefore, accesses to these i/o registers cause corresponding accesses on the ide interface. in native mode, the intel ? 6300ESB ich w ill not decode the legacy ranges. the same offsets are used as in ta b l e 8 0 , however, the base addresses are selected using the pci bars, rather than fixed i/o locations. for accesses to the alt status register in the control block, the p-ata host controller must always force the upper address bit (pda[2] or sda[2]) to 1 in order to ensure proper decode by the p-ata device. unlike the legacy mode fixed address location, the native mode address for this register may contain a 0 in address bit 2 when it is received by the p-ata host controller. 5.14.2.4 pio ide timing modes ide data port transaction latency consists of startup latency, cycle latency, and shutdown latency. startup latency is incurred when a pci master cycle targeting the ide data port is decoded and the da[2:0] and csxx# lines are not set up. startup latency provides the setup time for the da[2:0] and csxx# lines prior to assertion of the read and write strobes (dior# and diow#). cycle latency consists of the i/o command strobe assertion length and recovery time. recovery time is provided so that transactions may occur back-to-back on the ide interface (without incurring startup and shutdown latency) without violating minimum cycle periods for the ide interface. the command strobe assertion width for the enhanced timing mode is selected by the ide_tim register and may be set to 2, 3, 4, or 5 pci clocks. the recovery time is selected by the ide_tim register and may be set to 1, 2, 3, or 4 pci clocks. when iordy is asserted when the initial sample point is reached, no wait-states are added to the command strobe assertion length. when iordy is negated when the initial sample point is reached, additional wait-states are added. since the rising edge of iordy must be synchronized, at least two additional pci clocks are added. table 80. ide legacy i/o ports: command block registers (cs1x# chip select) i/o offset register function (read) register function (write) 00h data data 01h error features 02h sector count sector count 03h sector number sector number 04h cylinder low cylinder low 05h cylinder high cylinder high 06h drive head 07h status command note: for accesses to the alt status register in the control block, the intel ? 6300ESB ich must always force the upper address bit (pda[2] or sda[2]) to 1 in order to ensure proper native mode decode by the ide device. unlike the legacy mode fixed address location, the native mode address for this register may contain a 0 in address bit 2 when it is received by the intel ? 6300ESB ich.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 181 5?intel ? 6300ESB ich shutdown latency is incurred after outstanding scheduled ide data port transactions (either a non-empty write post buffer or an outstanding read prefetch cycles) have completed and before other transactions may proceed. it provides hold time on the da[2:0] and csxx# lines with respect to the read and write strobes (dior# and diow#). shutdown latency is two pci clocks in duration. the ide timings for various transaction types are shown in ta b l e 8 1 . note that bit 2 (16-bit i/o recovery enable) of the isa i/o recovery timer register does not add wait-states to ide data port read accesses when any of the fast timing modes are enabled. 5.14.2.5 iordy masking the iordy signal may be ignored and assumed asserted at the first iordy sample point (isp) on a drive by drive basis through the idetim register. 5.14.2.6 pio 32-bit ide data port accesses a 32-bit pci transaction run to the ide data address (01f0h primary, 0170h secondary) results in two back to back 16-bit transactions to the ide data port. the 32-bit data port feature is enabled for all timings, not just enhanced timing. for compatible timings, a shutdown and startup latency is incurred between the two 16-bit halves of the ide transaction. this ensures that the chip selects will be deasserted for at least two pci clocks between the two cycles. 5.14.2.7 pio ide data port prefetching and posting the intel ? 6300ESB ich may be programmed through the idetim registers to allow data to be posted to and prefetched from the ide data ports. data pre fetching is initiated when a data port read occurs. the read prefetch eliminates latency to the ide data ports and allows them to be performed back to back for the highest possible pio data transfer rates. the first data port read of a sector is called the demand read. subsequent data port reads from the sector are called prefetch reads. the demand read and all prefetch reads much be of the same size (16 or 32 bits). data posting is performed for writes to the ide data ports. the transaction is completed on the pci bus after the data is received by the intel ? 6300ESB ich. the intel ? 6300ESB ich will then run the ide cycle to transfer the data to the drive. when the intel ? 6300ESB ich write buffer is non-empty and an unrelated (non-data or opposite channel) ide transaction occurs, that transaction will be stalled until all current data in the write buffer is transferred to the drive. table 81. ide transaction timings (pci clocks) ide transaction type startup latency iordy sample point (isp) recovery time (rct) shutdown latency non-data port compatible 4 11 22 2 data port compatible 3 6 14 2 fast timing mode 2 2 1 2
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 182 order number: 300641-004us 5.14.3 bus master function the intel ? 6300ESB ich may act as a pci bus master on behalf of an ide slave device. two pci bus master channels are provided, one channel for each ide connector (primary and secondary). by performing the ide data transfer as a pci bus master, the intel ? 6300ESB ich off-loads the processor and improves system performance in multitasking environments. both devices attached to a connector may be programmed for bus master transfers, but only one device per connector may be active at a time. 5.14.3.1 physical region descriptor format the physical memory region to be transferred is described by a physical region descriptor (prd). the prds are stored sequentially in a descriptor table in memory. the data transfer proceeds until all regions described by the prds in the table have been transferred. note that the intel ? 6300ESB ich bus master ide function does not support memory regions or descriptor tables located on isa. descriptor tables must not cross a 64-kbyte boundary. each prd entry in the table is 8 bytes in length. the first 4 bytes specify the byte address of a physical memory region. this memory region must be dword aligned and must not cross a 64-kbyte boundary. the next two bytes specify the size or transfer count of the region in bytes (64-kbyte limit per region). a value of zero in these two bytes indicates 64 kbytes (thus the minimum transfer count is 1). when bit 7 (eot) of the last byte is a 1, it indicates that this is the final prd in the descriptor table. bus master operation terminates when the last descriptor has been retired. when the bus master ide controller is reading data from the memory regions, bit 1 of the base address is masked and byte enables are asserted for all read transfers. when writing data, bit 1 of the base address is not masked and if set, will cause the lower word byte enables to be deasserted for the first dword transfer. the write to pci will typically consist of a 32-byte cache line. when valid data ends prior to end of the cache line, the byte enables will be deasserted for invalid data. the total sum of the byte counts in every prd of the descriptor table must be equal to or greater than the size of the disk transfer request. when greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the bus master ide command register to zero) when the drive issues an interrupt to signal transfer completion. figure 16. physical region descriptor table entry 051910_3.d rw byte 3 byte 2 byte 1 byte 0 eot reserved byte count [15:1] memory region physical base address [31:1] memory region main memory 0 0
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 183 5?intel ? 6300ESB ich 5.14.3.2 line buffer a single line buffer exists for the intel ? 6300ESB ich bus master ide interface. this buffer is not shared with any other function. the buffer is maintained in either the read state or the write state. memory writes are typically 4-dword bursts and invalid dwords have c/be[3:0]#=0fh. the line buffer allows burst data transfers to proceed at peak transfer rates. the bus master ide active bit in bus master ide status register is reset automatically when the controller has transferred all data associated with a descriptor table (as determined by eot bit in last prd). the ide interrupt status bit is set when the ide device generates an interrupt. these events may occur prior to line buffer emptying for memory writes. when either of these conditions exist, all pci master non-memory read accesses to the intel ? 6300ESB ich are retried until all data in the line buffers has been transferred to memory. 5.14.3.3 bus master ide timings the timing modes used for bus master ide transfers are identical to those for pio transfers. the dma timing enable only bits in ide timing register may be used to program fast timing mode for dma transactions only. this is useful for ide devices whose dma transfer timings are faster that its pio transfer timings. the ide device dma request signal is sampled on the same pci clock that dior# or diow# is deasserted. when inactive, the dma acknowledge signal is deasserted on the next pci clock and no more transfers take place until dma request is asserted again. 5.14.3.4 interrupts legacy mode: the intel ? 6300ESB ich is connected to irq14 for the primary interrupt and irq15 for the secondary interrupt. this connection is done from the isa pin, before any mask registers. this implies the following: ? bus master ide is operating under an interrupt based driver. therefore, it will not operate under environments where the ide device drives an interrupt but the interrupt is masked in the system. ? bus master ide devices are connected directly off of the intel ? 6300ESB ich. ide interrupts cannot be communicated through pci devices or the serial stream. caution: in this mode, the intel ? 6300ESB ich will not drive the pci interrupt associated with this function. that is only used in native mode. native mode: in this case both the primary and secondary channels share an interrupt. it will be internally connected to pirq[c]# (irq18 in apic mode). the interrupt will be active- low and shared. behavioral notes in native mode ? the irq14 and irq15 pins do not affect the internal irq14 and irq15 inputs to the interrupt controllers. the ide logic forces these signals inactive in such a way that the serial irq source may be used. ? the irq14 and irq15 inputs (not external irq[14:15] pins) to the interrupt controller may come from other sources (serial irq, pirqx). ? the irq14 and irq15 pins are inverted from active-high to the active-low pirq.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 184 order number: 300641-004us ? when switching the ide controller to native mode, the ide interrupt pin register will be masked (see section 9.1.19, ?offset 3dh: intr_pn?interrupt pin register (ide?d31:f1)? ). when an interrupt occurs while the masking is in place and the interrupt is still active when the masking ends, the interrupt will be allowed to be asserted. ? the active-low pirq must be masked by hardware when the iose bit is cleared in order to allow other interrupts that are shared with this pin to be delivered and serviced. when the iose bit is 0, software may not clear the ide interrupt status bits. when in native mode, a ?1? in the bus master interrupt status bit (bit 2 of bmisp/bmiss) forces the interrupt asserted. this bit must be cleared in order to deassert the interrupt. this implementation is different from the legacy mode. 5.14.3.5 bus master ide operation to initiate a bus master transfer between memory and an ide device, the following steps are required: 1. software prepares a prd table in system memory. the prd table must be dword aligned and must not cross a 64-kbyte boundary. 2. software provides the starting address of the prd table by loading the prd table pointer register. the direction of the data transfer is specified by setting the read/ write control bit. the interrupt bit and error bit in the status register are cleared. 3. software issues the appropriate dma transfer command to the disk device. 4. the bus master function is engaged by software writing a '1' to the start bit in the command register. the first entry in the prd table is fetched and loaded into two registers which are not visible by software, the current base and current count registers. these registers hold the current value of the address and byte count loaded from the prd table. the value in these registers is only valid when there is an active command to an ide device. 5. once the prd is loaded internally, the ide device will receive a dma acknowledge. 6. the controller transfers data to/from memory responding to dma requests from the ide device. the ide device and the host controller may or may not throttle the transfer several times. when the last data transfer for a region has been completed on the ide interface, the next descriptor is fetched from the table. the descriptor contents are loaded into the current base and current count registers. 7. at the end of the transfer the ide device signals an interrupt. 8. in response to the interrupt, software resets the start/stop bit in the command register. it then reads the controller status followed by the drive status to determine when the transfer completed successfully. the last prd in a table has the end of list (eol) bit set. the pci bus master data transfers will terminate when the physical region described by the last prd in the table has been completely transferred. the active bit in the status register will be reset and the ddrq signal will be masked. the buffer is flushed (when in the write state) or invalidated (when in the read state) when a terminal count condition exists; that is, the current region descriptor has the eol bit set and that region has been exhausted. the buffer is also flushed (write state) or invalidated (read state) when the interrupt bit in the bus master ide status register is set. software that reads the status register and finds the error bit reset, and either the active bit reset or the interrupt bit set, may be assured that all data destined for system memory has been transferred and that data is valid in system memory. ta b l e 8 2 describes how to interpret the interrupt and active bits in the status register after a dma transfer has started. during concurrent dma or ultra ata transfers, the intel ? 6300ESB ich ide interface will arbitrate between the primary and secondary ide cables when a prd expires.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 185 5?intel ? 6300ESB ich 5.14.3.6 error conditions ide devices are sector based mass storage devices. the drivers handle errors on a sector basis; either a sector is transferred successfully or it is not. a sector is 512 bytes. when the ide device does not complete the transfer due to a hardware or software error, the command will eventually be stopped by the driver setting command start bit to zero when the driver times out the disk transaction. information in the ide device registers help isolate the cause of the problem. when the controller encounters an error while doing the bus master transfers, it will stop the transfer (i.e., reset the active bit in the command register) and set the error bit in the bus master ide status register. the controller does not generate an interrupt when this happens. the device driver may use device specific information (pci configuration space status register and ide drive register) to determine what caused the error. whenever a requested transfer does not complete properly, information in the ide device registers (sector count) may be used to determine how much of the transfer was completed and to construct a new prd table to complete the requested operation. in most cases the existing prd table may be used to complete the operation. 5.14.3.7 8237-like protocol 8237 mode dma is similar in form to dma used on the isa bus. this mode uses pins familiar to the isa bus, namely a dma request, a dma acknowledge, and i/o read/ write strobes. these pins have similar characteristics to their isa counterparts in terms of when data is valid relative to strobe edges, and the polarity of the strobes, however the intel ? 6300ESB ich does not use the 8237 for this mode. table 82. interrupt/active bit interaction definition interrup t active description 01 dma transfer is in progress. no interrupt has been generated by the ide device. 10 the ide device generated an interrupt. the controller exhausted the physical region descriptors. this is the normal completion case where the size of the physical memory regions was equal to the ide device transfer size. 11 the ide device generated an interrupt. the controller has not reached the end of the physical memory regions. this is a valid completion case where the size of the physical memory regions was larger than the ide device transfer size. 00 this bit combination signals an error condition. when the error bit in the status register is set, the controller has some problem transferring data to/from memory. specifics of the error have to be determined using bus- specific information. when the error bit is not set, then the prd's specified a smaller size than the ide transfer size.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 186 order number: 300641-004us 5.14.4 ultra ata/33 protocol ultra ata/33 is enabled through configuration register 48h in device 31:function 1 for each ide device. the ide signal protocols are significantly different under this mode than for the 8237 mode. these differences allow the following enhancements to the transfer: ? a source synchronous protocol to allow higher data transfer rates of up to 33 mbytes/s. the device that drives the data lines also drives the data strobe signal. ? both the source and destination may pause the transfer. the source pauses the burst by not toggling its strobe signal, while the destination pauses the burst by deasserting a redefined signal, dmardy#. ? 16 bit wide crc error checking, sent from the intel ? 6300ESB ich to the ide device on ddack# deassertion. ultra ata/33 is a physical protocol used to transfer data between a ultra ata/33 capable ide controller such as the intel ? 6300ESB ich and one or more ultra ata/33 capable ide devices. it utilizes the standard bus master ide functionality and interface to initiate and control the transfer. ultra ata/33 utilizes a ?source synchronous? signaling protocol to transfer data at rates up to 33 mbytes/s. the ultra ata/33 definition also incorporates a cyclic redundancy checking (crc-16) error checking protocol. 5.14.4.1 signal descriptions the ultra ata/33 protocol requires no extra signal pins on the ide connector. it does redefine a number of the standard ide control signals when in ultra ata/33 mode. these redefinitions are shown in the following table. read cycles are defined as transferring data from the ide device to the intel ? 6300ESB ich. write cycles are defined as transferring data from the intel ? 6300ESB ich to ide device. the diow# signal is redefined as stop for both read and write transfers. this is always driven by the intel ? 6300ESB ich and is used to request that a transfer be stopped or as an acknowledgment to stop a request from the ide device. the dior# signal is redefined as dmardy# for transferring data from the ide device to the intel ? 6300ESB ich (read). it is used by the intel ? 6300ESB ich to signal when it is ready to transfer data and to add wait-states to the current transaction. the dior# signal is redefined as strobe for transferring data from the intel ? 6300ESB ich to the ide device (write). it is the data strobe signal driven by the intel ? 6300ESB ich on which data is transferred during each rising and falling edge transition. the iordy signal is redefined as strobe for transferring data from the ide device to the intel ? 6300ESB ich (read). it is the data strobe signal driven by the ide device on which data is transferred during each rising and falling edge transition. the iordy signal is redefined as dmardy# for transferring data from the intel ? 6300ESB ich to the ide device (write). it is used by the ide device to signal when it is ready to transfer data and to add wait-states to the current transaction. table 83. ultraata/33 control signal redefinitions standard ide signal definition ultra ata/33 read cycle definition ultra ata/33 write cycle definition intel ? 6300ESB ich primary channel signal intel ? 6300ESB ich secondary channel signal diow# stop stop pdiow# sdiow# dior# dmardy# strobe pdior# sdior# iordy strobe dmardy# piordy siordy
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 187 5?intel ? 6300ESB ich all other signals on the ide connector retain their functional definitions during ultra ata/33 operation. 5.14.4.2 operation initial setup programming consists of enabling and performing the proper configuration of the intel ? 6300ESB ich and the ide device for ultra ata/33 operation. for the intel ? 6300ESB ich, this consists of enabling synchronous dma mode and setting up appropriate synchronous dma timings. when ready to transfer data to or from an ide device, the bus master ide programming model is followed. once programmed, the drive and intel ? 6300ESB ich control the transfer of data through the ultra ata/33 protocol. the actual data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase. the ide device begins the start-up phase by asserting dmarq signal. when ready to begin the transfer, the intel ? 6300ESB ich w ill assert dmack# signal. when dmack# signal is asserted, the host controller will drive cs0# and cs1# inactive, da0?da2 low. for write cycles, the intel ? 6300ESB ich will deassert stop, wait for the ide device to assert dmardy#, and then drive the first data word and strobe signal. for read cycles, the intel ? 6300ESB ich will tri-state the dd lines, deassert stop, and assert dmardy#. the ide device will then send the first data word and strobe. the data transfer phase continues the burst transfers with the data transmitter (intel ? 6300ESB ich - writes, ide device - reads) providing data and toggling strobe. data is transferred (latched by receiver) on each rising and falling edge of strobe. the transmitter may pause the burst by holding strobe high or low, resuming the burst by again toggling strobe. the receiver may pause the burst by deasserting dmardy# and resumes the transfers by asserting dmardy#. the intel ? 6300ESB ich will pause a burst transaction in order to prevent an internal line buffer over or under flow condition, resuming once the condition has cleared. it may also pause a transaction when the current prd byte count has expired, resuming once it has fetched the next prd. warning: the current burst may be terminated by either the transmitter or receiver. a burst termination consists of a stop request, stop acknowledge and transfer of crc data. the intel ? 6300ESB ich may stop a burst by asserting stop, with the ide device acknowledging by deasserting dmarq. the ide device stops a burst by deasserting dmarq and the intel ? 6300ESB ich acknowledges by asserting stop. the transmitter then drives the strobe signal to a high level. the intel ? 6300ESB ich will then drive the crc value onto the dd lines and deassert dmack#. the ide device will latch the crc value on rising edge of dmack#. the intel ? 6300ESB ich will terminate a burst transfer when it needs to service the opposite ide channel, when a programmed i/o (pio) cycle is executed to the ide channel currently running the burst, or upon transferring the last data from the final prd. 5.14.4.3 crc calculation cyclic redundancy checking (crc-16) is used for error checking on ultra ata/33 transfers. the crc value is calculated for all data by both the intel ? 6300ESB ich and the ide device over the duration of the ultra ata/33 burst transfer segment. this segment is defined as all data transferred with a valid strobe edge from ddack# assertion to ddack# deassertion. at the end of the transfer burst segment, the intel ?
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 188 order number: 300641-004us 6300ESB ich will drive the crc value onto the dd[15:0] signals. it is then latched by the ide device on deassertion of ddack#. the ide device compares the intel ? 6300ESB ich crc value to its own and reports an error if there is a mismatch. 5.14.5 ultra ata/66 protocol in addition to ultra ata/33, the intel ? 6300ESB ich supports the ultra ata/66 protocol. the ultra ata/66 protocol is enabled through config bits 3:0 at offset 54h. the two protocols are similar, and are intended to be device driver compatible. the ultra ata/66 logic may achieve transfer rates of up to 66mbytes/s. in order to achieve the higher data rate, the timings are shortened and the quality of the cable is improved to reduce reflections, noise, and inductive coupling. note that the improved cable is required and will still plug into the standard ide connector. the ultra ata/66 protocol also supports a 44 mbytes/s mode. 5.14.6 ultra ata/100 protocol when the ata_fast bit is set for any of the four ide devices, then the timings for the transfers to and from the corresponding device run at a higher rate. the intel ? 6300ESB ich ultra ata/100 logic may achieve read transfer rates up to 100 mbytes/s, and write transfer rates up to 88.9 mbytes/s. the cable improvements required for ultra ata/66 are sufficient for ultra ata/100, so no further cable improvements are required when implementing ultra ata/100. 5.14.7 ultra ata/33/66/100 timing the timings for ultra ata/33/66/100 modes are programmed through the synchronous dma timing register and the ide configuration register. different timings may be programmed for each drive in the system. the base clock frequency for each drive is selected in the ide configuration register. the cycle time (ct) and ready to pause (rp) time (defined as multiples of the base clock) are programmed in the synchronous dma timing register. the cycle time represents the minimum pulse width of the data strobe (strobe) signal. the ready to pause time represents the number of base clock periods that the intel ? 6300ESB ich will wait from deassertion of dmardy# to the assertion of stop when it desires to stop a burst read transaction. note: the internal base clock for ultra ata/100 (mode 5) runs at 133 mhz, and the cycle time (ct) must be set for three base clocks. the intel ? 6300ESB ich will thus toggle the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe edge. this means that the intel ? 6300ESB ich will perform mode 5 write transfers at a maximum rate of 88.9 mbytes/s. for read transfers, the read strobe will be driven by the ata/100 device, and the intel ? 6300ESB ich supports reads at the maximum rate of 100 mbytes/s.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 189 5?intel ? 6300ESB ich 5.15 sata host controller (d31:f2) 5.15.1 overview the intel ? 6300ESB ich sata controller features two sets of interface signals that may be independently enabled, tri-stated or driven low. each interface is supported by an independent dma controller. the intel ? 6300ESB ich sata controller interacts with an attached mass storage device through a register interface that is equivalent to that presented by a traditional ide host adapter. the host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. 5.15.2 theory of operation 5.15.2.1 standard ata emulation the intel ? 6300ESB ich contains a set of registers that shadow the contents of the legacy ide registers. the behavior of the command and control block registers, pio and dma data transfers, resets, and interrupts are all emulated. 5.15.2.2 48-bit lba operation (logical block addressing) the sata host controller supports 48-bit lba through the host-to-device register fis, frame information structure, when accesses are performed through writes to the task file. the sata host controller will ensure that the correct data is put into the correct byte of the host-to-device fis. there are special considerations when reading from the task file to support 48-bit lba operation. software may need to read all 16 bits. since the registers are only 8 bits wide and act as a fifo, a bit must be set in the device/control register, which is at offset 3f6h for primary and 376h for secondary (or their native counterparts). when software clears bit 7 of the control register before performing a read, the last item written will be returned from the fifo. when software sets bit 7 of the control register before performing a read, the first item written will be returned from the fifo. 5.15.3 hot plug operation dynamic hot plug (such as surprise removal) is not supported by the sata host controller. however, using the spc register configuration bits, and power management flows, a device may be powered down by software, and the port may then be powered off, allowing removal and insertion of a new device. 5.15.4 power management operation power management of the intel ? 6300ESB ich sata controller and ports will cover operations of the host controller and the sata wire.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 190 order number: 300641-004us 5.15.4.1 power state mappings the following pci power management states for devices are supported by the intel ? 6300ESB ich sata controller: d0 ? working d3 ? very deep sleep. this state is split into two sub-states, d3 hot (may respond to pci configuration accesses) and d3 cold (cannot respond to pci configuration accesses). these two sub-states are considered the same, where d3 hot has v cc , but d3 cold does not. this is the only state allowed for the host controller when the system is in an s1-s5 state. sata devices may also have multiple power states. from parallel ata, three device states are supported through acpi. they are: d0 ? device is working and instantly available. d1 ? device enters when it receives a standby immediate command. exit latency from this state is in seconds d3 ? from the sata device?s perspective, no different than a d1 state, in that it is entered through the standby immediate command. however, an acpi method is also called which will reset the device and then cut its power. each of these device states are subsets of the host controller?s d0 state. finally, sata defines three phy layer power states, which have no equivalent mappings to parallel ata. they are: phy ready ? phy logic and pll are both on and active partial ? phy logic is powered, but in a reduced state. exit latency is no longer than 10 ns slumber ? phy logic is powered, but in a reduced state. exit latency may be up to 10 ms. since these states have much lower exit latency than the acpi d1 and d3 states, the sata controller defines these states as sub-states of the device d0 state. figure 17. sata power states host = d0 device = d3 power resume latency host = d3 device = d3 phy = off device = d0 phy = ready device = d1 phy = slumber phy = partial phy = off (port disabled) phy = slumber phy = off (port disabled) phy = slumber phy = off (port disabled)
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 191 5?intel ? 6300ESB ich 5.15.4.2 power state transitions 5.15.4.2.1 partial and slumber state entry/exit the partial and slumber states save interface power when the interface is idle. it would be most analogous to pci clkrun# (in power savings, not in mechanism), where the interface may have power saved while no commands are pending. the sata controller defines phy layer power management (as performed through primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. the sata controller will accept device transition types, but will not issue any transitions as a host. all received requests from a sata device will be acked. when an operation is performed to the sata controller such that it needs to use the sata cable, the controller must check whether the link is in the partial or slumber states, and if so, must issue a com_wake to bring the link back online. similarly, the sata device must perform the same action. 5.15.4.2.2 device d1, d3 states these states are entered after some period of time when software has determined that no commands will be sent to this device for some time. the mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. the command most likely to be used in ata/atapi is the ?standby immediate? command. 5.15.4.2.3 host controller d3 state after the interface and device have been put into a low power state, the host controller may be put into a low power state. this is performed through the pci power management registers in configuration space. there are two very important aspects to note when using pci power management. 1. when the power state is d3, only accesses to configuration space are allowed. any attempt to access the memory or i/o spaces must result in master abort. 2. when the power state is d3, no interrupts may be generated, even when they are enabled. when an interrupt status bit is pending when the controller transitions to d0, an interrupt may be generated. when the controller is put into d3, it is assumed that software has properly shut down the device and disabled the ports. therefore, there is no need to sustain any values on the port wires. the interface will be treated as though no device is present on the cable, and power will be minimized. 5.15.4.3 smi trapping (apm) offset 48h, bits 3:0 in the power management i/o space contain control for generating smi# on accesses to the ide i/o spaces. these bits map to the legacy ranges only (1f0-1f7h, 3f6h, 170-177h, and 376h). when the sata controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set will cause the cycle to not be forwarded to the sata controller, and an smi# is generated. to block accesses to the native ide ranges, software must use the generic power management control registers described in section 8.8.1.7, ?offset c4h, c6h, c8h, cah: mon[n]_trp_rng?i/o monitor [4:7] trap range register for devices 4-7 (pm? d31:f0)? .
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 192 order number: 300641-004us 5.15.5 sata interrupts the following table summarizes interrupt behavior for msi and wire-modes. in the table ?bits? refers to the 4 possible interrupt bits in i/o space, which are: bmisp.prdis (offset 02h, bit 7), bmisp.i (offset 02h, bit 2), bmiss.prdis (offset 0ah, bit 7), and bmiss.i (offset 0ah, bit 2). see section 20.2, ?bus master ide i/o registers (d31:f2)? for i/o space register details. 5.15.6 sataled# the sataled# pin is driven low to indicate sata drive activity. when sataled# is asserted, the led is active. 5.16 multimedia event timers 5.16.1 overview this function provides a set of timers that may be used by the operating system. the timers are defined such that in the future, the os may be able to assign specific timers to be used directly by specific applications. each timer may be configured to cause a separate interrupt. this specification allows for a block of 32 timers, with support for up to eight blocks, for a total of 256 timers. however, specific implementations may include only a subset of these timers. the intel ? 6300ESB ich provides three timers. the three timers are implemented as a single counter each with its own comparator and value register. each timer?s counter increases monotonically. each individual timer may generate an interrupt when the value in its value register matches the value in the main counter. some of the timers may be enabled to generate a periodic interrupt. the registers associated with these timers are mapped to a memory space (much like the i/o apic). however, it is not implemented as a standard pci function. the bios reports to the operating system the location of the register space. the hardware may support an assignable decode space, however the bios will set this space prior to handing it over to the os (see section 6.4, ?memory map? ). it is not expected that the os will move the location of these timers once it is set by the bios. in the intel ? 6300ESB ich, one timer block is implemented. the timer block has one counter and three timers (comparators). future devices may have a different number of implemented timers. various capabilities registers indicate the number of timers and the capabilities of each. table 84. sata msi vs. pci irq actions interrupt register wire-mode action msi action all bits are ?0?. wire inactive no action one or more bits set to ?1?. wire active send message one or more bits set to ?1?, new bit gets set to ?1?. wire active send message one or more bits set to ?1?, software clears some (but not all) bits. wire active send message one or more bits set to ?1?, software clears all bits. wire inactive no action software clears one or more bits, and one or more bits is set simultaneously. wire active send message
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 193 5?intel ? 6300ESB ich 5.16.2 timer accuracy 1. the timers are accurate over any 1 ms period to within 0.005% of the time specified in the timer resolution fields. 2. within any 100 ms period, the timer will report a time that is up to two ticks too early or too late. each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. the timer is monotonic. it will not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). the main counter will be clocked by the 14.31818 mhz clock, synchronized into the 66.666 mhz domain. this w ill result in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. the main counter will be as accurate as the 14.3818 mhz clock. 5.16.3 interrupt mapping mapping option #1: legacy option in this case, the legacy rout bit (leg_rt_cnf) will be set. this will force the mapping found in tab l e 8 5 . see section 15.1.3, ?offset 010-017h: general config register? for leg_rt_cnf details. mapping option #2: standard option in this case, the legacy rout bit (leg_rt_cnf) will be zero. each timer has its own routing control. the supported interrupt values are irq 20, 21, 22, and 23. see section 15.1.3, ?offset 010-017h: general config register? for leg_rt_cnf details. 5.16.4 periodic vs. non-periodic modes non-periodic mode when a timer is set up for non-periodic mode, it will generate a value in the main counter which matches the value in the timer?s comparator register. when the timer is set up for 32-bit mode, it will generate another interrupt when the main counter wraps around and matches this same value again. timer 0 is configurable to 32 (default) or 64-bit mode, whereas timers 1 and 2 only support 32-bit mode. during run-time, the value in the timer?s comparator value register will not be changed by the hardware. software may change the value. warning: software must be careful when programming the comparator registers. when the value written to the register is not sufficiently far in the future, the counter table 85. legacy routing time r 8259 mapping apic mapping comment 0 irq0 irq2 in this case, the 8254 timer will not cause any interrupts. 1 irq8 irq8 in this case, the rtc will not cause any interrupts. 2 as per irq routing field as per irq routing field
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 194 order number: 300641-004us may pass the value before it reaches the register and the interrupt will be missed. all three timers support non-periodic mode. periodic mode timer 0 is the only timer that supports periodic mode. when timer 0 is set up for periodic mode, the software writes a value into the timer?s comparator value register. when the main counter value matches the value in the timer?s comparator value register, an interrupt may be generated. the hardware will then automatically increase the value in the comparator value register by the last value written to that register. to make the periodic mode work properly, the main counter is typically written with a value of zero so that the first interrupt occurs at the right point for the comparator. when the main counter is not set to zero, interrupts may not occur as expected. during run-time, the value in the timer?s comparator value register may be read by software to find out when the next periodic interrupt will be generated (not the rate at which it generates interrupts). software is expected to remember the last value written to the comparator?s value register (the rate at which interrupts are generated). when software wants to change the periodic rate, it should write a new value to the comparator value register. at the point when the timer?s comparator indicates a match, this new value will be added to derive the next matching point. when the software resets the main counter, the value in the comparator?s value register needs to be reset as well. this may be done by setting the timer0_val_set_cnf bit. again, to avoid race conditions, this should be done with the main counter halted. see section 15, ?multimedia timer registers? for register and bits details. the following usage model is expected: 1. software clears the enable_cnf bit to prevent any interrupts 2. software clears the main counter by writing a value of 00h to it. 3. software sets the timer0_val_set_cnf bit. 4. software writes the new value in the timer0_comparator_val register 5. software sets the enable_cnf bit to enable interrupts. warning: as the timer period approaches zero, the interrupts associated with the periodic timer may not get completely serviced before the next timer match occurs. interrupts may get lost and/or system performance may be degraded in this case. the timer 0 comparator value register cannot be programmed reliably by a single 64- bit write in a 32-bit environment except when only the periodic rate is being changed during run-time. when the actual timer 0 comparator value needs to be reinitialized, the following software solution will always work regardless of the environment: 1. set timer0_val_set_cnf bit 2. set the lower 32 bits of the timer0 comparator value register 3. set timer0_val_set_cnf bit 4. set the upper 32 bits of the timer0 comparator value register
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 195 5?intel ? 6300ESB ich 5.16.5 enabling the timers the bios or os pnp code should route the interrupts. this includes the legacy rout bit, interrupt rout bit (for each timer), interrupt type (to select the edge or level type for each timer) the device driver code should do the following for an available timer: 1. set the overall enable bit (offset 04h, bit 0). 2. set the timer type field (selects one-shot or periodic). 3. set the interrupt enable. 4. set the comparator value. 5.16.6 interrupt levels interrupts directed to the internal 8259s are active high. see section 5.7, ?advanced interrupt controller (apic) (d29:f5)? for information regarding the polarity programming of the i/o apic for detecting internal interrupts. when the interrupts are mapped to the i/o apic and set for level-triggered mode, they may be shared with pci interrupts, although it is unlikely for the os to attempt this. when more than one timer is configured to share the same irq using the timern_int_rout_cnf fields, the software must configure the timers to level-triggered mode. edge-triggered interrupts cannot be shared. 5.16.7 handling interrupts when each timer has a unique interrupt and the timer has been configured for edge- triggered mode, no specific steps are required. no read is required to process the interrupt. when a timer has been configured to level-triggered mode, its interrupt must be cleared by the software. this is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. independent of the mode, software may read the value in the main counter to see how much time has passed between when the interrupt was generated and when it was first serviced. when timer 0 is set up to generate a periodic interrupt, the software may check to see how much time remains until the next interrupt by checking the timer value register. 5.16.8 issues related to 64-bit timers with 32-bit processors a 32-bit timer may be read directly using processors that are capable of 32-bit or 64- bit instructions. however, a 32-bit processor may not be able to directly read 64-bit timer. a race condition comes up when a 32-bit processor reads the 64-bit register using two separate 32-bit reads. the danger is that just after reading one half, the other half rolls over and changes the first half. when a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 196 order number: 300641-004us when a 32-bit processor does not want to halt the timer, it may use the 64-bit timer as a 32-bit timer by setting the timern_32mode_cnf bit. this will cause the timer to behave as a 32-bit timer. the upper 32 bits will always be 0. 5.17 usb uhci controllers (d29:f0 and f1) 5.17.1 overview the intel ? 6300ESB ich contains two usb uhci host controllers. each host controller includes a root hub with two separate usb ports each, for a total of four usb ports. the intel ? 6300ESB ich host controllers support the standard universal host controller interface (uhci) specification, rev 1.1. overcurrent detection on all four usb ports is supported. the overcurrent inputs are 5v-tolerant and may be used as gpis when not needed. the intel ? 6300ESB ich?s usb uhci controllers are arbitrated differently from standard pci devices to improve arbitration latency. the usb uhci controllers use the analog front end (afe) embedded cell that allows support for usb high-speed signaling rates instead of usb i/o buffers. 5.17.2 data structures in main memory this section describes the details of the data structures used to communicate control, status, and data between software and the intel ? 6300ESB ich: frame lists, transfer descriptors, and queue heads. frame lists are aligned on 4-kbyte boundaries. transfer descriptors and queue heads are aligned on 16-byte boundaries. 5.17.2.1 frame list pointer the frame list pointer contains a link pointer to the first data object to be processed in the frame, as well as the control bits defined in tab l e 8 6 . table 86. frame list pointer bit description bit description 31:4 frame list pointer (flp): this field contains the address of the first data object to be processed in the frame and corresponds to memory address signals [31:4], respectively. 3:2 reserved. these bits must be written as zero. 1 qh/td select (q): this bit indicates to the hardware whether the item referenced by the link pointer is a td (transfer descriptor) or a qh (queue head). this allows the intel ? 6300ESB ich to perform the proper type of processing on the item after it is fetched. 1 = qh 0 = td 0 terminate (t): this bit indicates to the intel ? 6300ESB ich whether the schedule for this frame has valid entries in it. 1 = empty frame (pointer is invalid). 0 = pointer is valid (points to a qh or td).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 197 5?intel ? 6300ESB ich 5.17.2.2 transfer descriptors (td) transfer descriptors (tds) express the characteristics of the transaction requested on usb by a client. tds are always aligned on 16-byte boundaries, and the elements of the td are shown in figure 18 . the four different usb transfer types are supported by a small number of control bits in the descriptor that the intel ? 6300ESB ich interprets during operation. all transfer descriptors have the same basic, 32-byte structure. during operation, the intel ? 6300ESB ich hardware performs consistency checks on some fields of the td. when a consistency check fails, the intel ? 6300ESB ich halts immediately and issues an interrupt to the system. this interrupt cannot be masked within the intel ? 6300ESB ich. figure 18. transfer descriptor table 87. td link pointer bit description 31:4 link pointer (lp): bits [31:4] correspond to memory address signals [31:4], respectively. this field points to another td or qh. 3 reserved. must be 0 when writing this field. 2 depth/breadth select (vf): this bit is only valid for queued tds and indicates to the hardware whether it should process in a depth first or breadth first fashion. when set to depth first, it informs the intel ? 6300ESB ich to process the next transaction in the queue rather than starting a new queue. 0 = breadth first 1 = depth first 1 qh/td select (q): this bit informs the intel ? 6300ESB ich whether the item referenced by the link pointer is another td or a qh. this allows the intel ? 6300ESB ich to perform the proper type of processing on the item after it is fetched. 0 = td 1 = qh 0 terminate (t): this bit informs the intel ? 6300ESB ich that the link pointer in this td does not point to another valid entry. when encountered in a queue context, this bit indicates to the intel ? 6300ESB ich that there are no more valid entries in the queue. a td encountered outside of a queue context with the t bit set informs the intel ? 6300ESB ich that this is the last td in the frame. 0 = link pointer field is valid. 1 = link pointer field not valid. q v f 0 0 1 2 3 4 31 l i n k p o i n t e r maxlen b u f f e r p o i n t e r t 7 8 15 16 23 24 10 11 14 18 19 20 r d status r a c t l e n e n d p t d e v i c e a d d r e s s p i d r i o c i o o s l s c _ e r r s p d 25 26 27 28 29 30 21 r = r e s e r v e d ich read/write ich read only
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 198 order number: 300641-004us table 88. td control and status (sheet 1 of 3) bit description 31:30 reserved. 29 short packet detect (spd): when a packet has this bit set to 1 and the packet is an input packet, is in a queue; and successfully completes with an actual length less than the maximum length then the td is marked inactive, the queue header is not updated and the usbint status bit (status register) is set at the end of the frame. in addition, when the interrupt is enabled, the interrupt will be sent at the end of the frame. note that any error (e.g., babble or fifo error) prevents the short packet from being reported. the behavior is undefined when this bit is set with output packets or packets outside of queues. 0 = disable 1 = enable 28:27 error counter (c_err): this field is a 2-bit down counter that keeps track of the number of errors detected while executing this td. when this field is programmed with a non zero value during setup, the intel ? 6300ESB ich decrements the count and writes it back to the td when the transaction fails. when the counter counts from one to zero, the intel ? 6300ESB ich marks the td inactive, sets the ?stalled? and error status bit for the error that caused the transition to zero in the td. an interrupt will be generated to host controller driver (hcd) when the decrement to zero was caused by data buffer error, bit stuff error, or when enabled, a crc or timeout error. when hcd programs this field to zero during setup, the intel ? 6300ESB ich will not count errors for this td and there will be no limit on the retries of this td. bits[28:27]interrupt after 00 no error limit 01 1 error 10 2 errors 11 3 errors error decrement counter error decrement counter crc error yes data buffer error yes timeout error yes stalled no 1 nak received no bit stuff error yes babble detected no ? ? detection of babble or stall automatically deactivates the td. thus, count is not decremented. 26 low speed device (ls): this bit indicates that the target device (usb data source or sink) is a low speed device, running at 1.5 mb/s, instead of at full speed (12 mb/s). there are special restrictions on schedule placement for low speed tds. when an intel ? 6300ESB ich root hub port is connected to a full speed device and this bit is set to a 1 for a low speed transaction, the intel ? 6300ESB ich sends out a low speed preamble on that port before sending the pid. no preamble is sent when a intel ? 6300ESB ich root hub port is connected to a low speed device. 0 = full speed device 1 = low speed device 25 isochronous select (ios): the field specifies the type of the data structure. when this bit is set to a 1, then the td is an isochronous transfer. isochronous tds are always marked inactive by the hardware after execution, regardless of the results of the transaction. 0 = non-isochronous transfer descriptor 1 = isochronous transfer descriptor 24 interrupt on complete (ioc): this specifies that the intel ? 6300ESB ich should issue an interrupt on completion of the frame in which this transfer descriptor is executed. even when the active bit in the td is already cleared when the td is fetched (no transaction will occur on usb), an ioc interrupt is generated at the end of the frame. 1 = issue ioc
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 199 5?intel ? 6300ESB ich 23 active: for intel ? 6300ESB ich schedule execution operations, see section 5.17.3, ?data transfers to/from main memory? , data transfers to/from main memory. 0 = when the transaction associated with this descriptor is completed, the intel ? 6300ESB ich sets this bit to 0 indicating that the descriptor should not be executed when it is next encountered in the schedule. the active bit is also set to 0 when a stall handshake is received from the endpoint. 1 = set to 1 by software to enable the execution of a message transaction by the intel ? 6300ESB ich. 22 stalled: 1 = set to a 1 by the intel ? 6300ESB ich during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this td. this may be caused by babble, the error counter counting down to zero, or reception of the stall handshake from the device during the transaction. any time that a transaction results in the stalled bit being set, the active bit is also cleared (set to 0). when a stall handshake is received from a setup transaction, a time-out error will also be reported. 21 data buffer error (dbe): 1 = set to a 1 by the intel ? 6300ESB ich during status update to indicate that the intel ? 6300ESB ich is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun). when this occurs, the actual length and max length field of the td will not match. in the case of an underrun, the intel ? 6300ESB ich will transmit an incorrect crc (thus invalidating the data at the endpoint) and leave the td active (unless error count reached zero). when an overrun condition occurs, the intel ? 6300ESB ich will force a timeout condition on the usb, invalidating the transaction at the source. 20 babble detected (babd): 1 = set to a 1 by the intel ? 6300ESB ich during status update when ?babble? is detected during the transaction generated by this descriptor. babble is unexpected bus activity for more than a preset amount of time. in addition to setting this bit, the intel ? 6300ESB ich also sets the ?stalled? bit (bit 22) to a 1. since ?babble? is considered a fatal error for that transfer, setting the ?stalled? bit to a 1 insures that no more transactions occur as a result of this descriptor. detection of babble causes immediate termination of the current frame. no further tds in the frame are executed. execution resumes with the next frame list index. 19 negative acknowledgment (nak) received (nakr): 1 = set to a 1 by the intel ? 6300ESB ich during status update when the intel ? 6300ESB ich receives a ?nak? packet during the transaction generated by this descriptor. when a nak handshake is received from a setup transaction, a time- out error will also be reported. 18 crc/time-out error (crc_tout): 1 = set to a 1 by the intel ? 6300ESB ich as follows: during a status update in the case that no response is received from the target device/ endpoint within the time specified by the protocol chapter of the usb specification. during a status update when a cyclic redundancy check (crc) error is detected during the transaction associated with this transfer descriptor. in the transmit case (out or setup command), this is in response to the intel ? 6300ESB ich detecting a timeout from the target device/endpoint. in the receive case (in command), th is is in response to the intel ? 6300ESB ich?s crc checker circuitry detecting an error on the data received from the device/endpoint or a nak or stall handshake being received in response to a setup transaction. 17 bit stuff error (bse): 1 = this bit is set to a 1 by the intel ? 6300ESB ich during status update to indicate that the receive data stream contained a sequence of more than 6 ones in a row. table 88. td control and status (sheet 2 of 3) bit description
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 200 order number: 300641-004us 16 bus turn around time-out (btto): 1 = this bit is set to a 1 by the intel ? 6300ESB ich during status updates to indicate that a bus time-out condition was detected for this usb transaction. this time-out is specially defined as not detecting an idle-to ?k? state start of packet (sop) transition from 16 to 18 bit times after the se0-to-ide transition of previous end of packet (eop). 15:11 reserved 10:0 actual length (actlen): the actual length field is written by the intel ? 6300ESB ich at the conclusion of a usb transaction to indicate the actual number of bytes that were transferred. it may be used by the software to maintain data integrity. the value programmed in this register is encoded as n-1 (see maximum length field description in the td token). table 89. td token bit description 31:21 maximum length (maxlen): the maximum length field specifies the maximum number of data bytes allowed for the transfer. the maximum length value does not include protocol bytes, such as packet id (pid) and crc. the maximum data packet is 1280 bytes. the 1280 packet length is the longest packet theoretically ensured to fit into a frame. actual packet maximum lengths are set by hcd according to the type and speed of the transfer. note that the maximum length allowed by the usb specification is 1023 bytes. the valid encodings for this field are: 0x000 = 1 byte 0x001 = 2 bytes .... 0x3fe = 1023 bytes 0x3ff = 1024 bytes .... 0x4ff = 1280 bytes 0x7ff = 0 bytes (null data packet) note that values from 500h to 7feh are illegal and cause a consistency check failure. in the transmit case, the intel ? 6300ESB ich uses this value as a terminal count for the number of bytes it fetches from host memory. in most cases, this is the number of bytes it will actually transmit. in rare cases, the intel ? 6300ESB ich may be unable to access memory (e.g., due to excessive latency) in time to avoid underrunning the 20 reserved. 19 data toggle (d): this bit is used to synchronize data transfers between a usb endpoint and the host. this bit determines which data pid is sent or expected (0=data0 and 1=data1). the data toggle bit provides a 1-bit sequence number to check whether the previous packet completed. this bit must always be 0 for isochronous tds. 18:15 endpoint (endpt): this 4-bit field extends the addressing internal to a particular device by providing 16 endpoints. this permits more flexible addressing of devices in which more than one sub-channel is required. 14:8 device address: this field identifies the specific device serving as the data source or sink. 7:0 packet identification (pid): this field contains the packet id to be used for this transaction. only the in (69h), out (e1h), and setup (2dh) tokens are allowed. any other value in this field causes a consistency check failure resulting in an immediate halt of the intel ? 6300ESB ich. bits [3:0] are complements of bits [7:4]. table 88. td control and status (sheet 3 of 3) bit description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 201 5?intel ? 6300ESB ich 5.17.2.3 queue head (qh) queue heads are special structures used to support the requirements of control, bulk, and interrupt transfers. since these tds are not automatically retired after each use, their maintenance requirements may be reduced by putting them into a queue. queue heads must be aligned on a 16-byte boundary, and the elements are shown in tab l e 9 1 . table 90. td buffer pointer bit description 31:0 buffer pointer (buff_pnt): bits [31:0] corresponds to memory address [31:0], respectively. it points to the beginning of the buffer that will be used during this transaction. this buffer must be at least as long as the value in the maximum length field described int the td token. the data buffer may be byte-aligned. table 91. queue head block bytes description attributes 00-03 queue head link pointer ro 04-07 queue element link pointer r/w table 92. queue head link pointer bit description 31:4 queue head link pointer (qhlp): this field contains the address of the next data object to be processed in the horizontal list and corresponds to memory address signals [31:4], respectively. 3:2 reserved. these bits must be written as zeros. 1 qh/td select (q): this bit indicates to the hardware whether the item referenced by the link pointer is another td or a qh. 0 = td 1 = qh 0 terminate (t): this bit indicates to the intel ? 6300ESB ich that this is the last qh in the schedule. when there are active tds in this queue, they are the last to be executed in this frame. 0 = pointer is valid (points to a qh or td). 1 = last qh (pointer is invalid). table 93. queue element link pointer (sheet 1 of 2) bit description 31:4 queue element link pointer (qelp): this field contains the address of the next td or qh to be processed in this queue and corresponds to memory address signals [31:4], respectively.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 202 order number: 300641-004us 5.17.3 data transfers to/from main memory the following sections describe the details on how hcd and the intel ? 6300ESB ich communicate through the schedule data structures. the discussion is organized in a top-down manner, beginning with the basics of walking the frame list, followed by a description of generic processing steps common to all transfer descriptors, and finally a discussion on transfer queuing. 5.17.3.1 executing the schedule software programs the intel ? 6300ESB ich with the starting address of the frame list and the frame list index, then causes the intel ? 6300ESB ich to execute the schedule by setting the run/stop bit in the control register to run. the intel ? 6300ESB ich processes the schedule one entry at a time; the next element in the frame list is not fetched until the current element in the frame list is retired. schedule execution proceeds in the following fashion: 1. the intel ? 6300ESB ich first fetches an entry from the frame list. this entry has three fields. bit 0 indicates whether the address pointer field is valid. bit 1 indicates whether the address points to a transfer descriptor or to a queue head. the third field is the pointer itself. 2. when isochronous traffic is to be moved in a given frame, the frame list entry points to a transfer descriptor. when no isochronous data is to be moved in that frame, the entry points to a queue head or the entry is marked invalid and no transfers are initiated in that frame. 3. when the frame list entry indicates that it points to a transfer descriptor, the intel ? 6300ESB ich fetches the entry and begins the operations necessary to initiate a transaction on usb. each td contains a link field that points to the next entry, as well as indicating whether it is a td or a qh. 4. when the frame list entry contains a pointer to a qh, the intel ? 6300ESB ich processes the information from the qh to determine the address of the next data object that it should process. 5. the td/qh process continues until the millisecond allotted to the current frame expires. at this point, the intel ? 6300ESB ich fetches the next entry from the frame list. when the intel ? 6300ESB ich is not able to process all of the transfer descriptors during a given frame, those descriptors are retired by software without having been executed. 3:2 reserved. 1 qh/td select (q): this bit indicates to the hardware whether the item referenced by the link pointer is another td or a qh. for entries in a queue, this bit is typically set to zero. 0 = td 1 = qh 0 terminate (t): this bit indicates to the intel ? 6300ESB ich that there are no valid tds in this queue. when hcd has new queue entries it overwrites this value with a new td pointer to the queue entry. 0 = pointer is valid. 1 = terminate (no valid queue entries). table 93. queue element link pointer (sheet 2 of 2) bit description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 203 5?intel ? 6300ESB ich 5.17.3.2 processing transfer descriptors the intel ? 6300ESB ich executes a td using the following generalized algorithm. these basic steps are common across all modes of tds. subsequent sections present processing steps unique to each td mode. 1. the intel ? 6300ESB ich fetches td or qh from the current link pointer. 2. when a qh, go to 1 to fetch from the queue element link pointer. when inactive, go to 12. 3. build token, actual bits are in td token. 4. when (host-to-function) then [ pci access ] issue request for data, (referenced through td.bufferpointer) wait for first chunk data arrival end if 5. [ begin usb transaction ] issue token (from token built in 2, above) and begin data transfer. if (host-to-function) then go to 6 else go to 7 end if 6. fetch data from memory (through td bufferpointer) and transfer over usb until td max-length bytes have been read and transferred. [ concurrent system memory and usb accesses ]. go to 8. 7. wait for data to arrive (from usb). write incoming bytes into memory beginning at td bufferpointer. internal hc buffer should signal end of data packet. number of bytes received must be td max-length; the length of the memory area referenced by td bufferpointer. 8. issue handshake based on status of data received (ack or time-out). go to 10. 9. wait for handshake, when required [ end of usb transaction ]. 10. update status [ pci access ] (td.status and td.actuallength). when the td was an isochronous td, mark the td inactive. go to 12. when not an isochronous td, and td completed successfully, mark the td inactive. go to 11. when not successful, and the error count has not been reached, leave the td active. when the error count has been reached, mark the td inactive. go to 12. 11. write the link pointer from the current td into the element pointer field of the qh structure. when the vf bit is set in the td link pointer, go to 2. 12. proceed to next entry.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 204 order number: 300641-004us 5.17.3.3 command register, status register, and td status bit interaction note that when a nak or stall response is received from a setup transaction, a time- out error will be reported. this will cause the error counter to decrement and the crc/ time-out error status bit to be set within the td control and status dword during write back. when the error counter changes from 1 to 0, the active bit will be reset to 0 and stalled bit to 1 as normal. 5.17.3.4 transfer queuing transfer queues are used to implement an ensured data delivery stream to a usb endpoint. transfer queues are composed of two parts: a queue header (qh) and a linked list. the linked list of tds and qhs has an indeterminate length (0 to n). table 94. command register, status register and td status bit interaction condition intel ? 6300ESB ich usb status register actions td status register actions crc/time-out error set usb error int bit 1 , clear hc halted bit clear active bit 1 and set stall bit 1 . illegal pid, pid error, max length (illegal) clear run/stop bit in command register set hc process error and hc halted bits pci master/target abort clear run/stop bit in command register set host system error and hc halted bits suspend mode clear run/stop bit in command register 2 set hc halted bit resume received and suspend mode = 1 set resume received bit run/stop = 0 clear run/stop bit in command register set hc halted bit config flag set set config flag in command register hc reset/global reset clear run/stop and config flag in command register clear usb int, usb error int, resume received, host system error, hc process error, and hc halted bits ioc = 1 in td status set usb int bit stall set usb error int bit clear active bit 1 and set stall bit. bit stuff/data buffer error set usb error int bit 1 . clear active bit 1 and set stall bit 1 . short packet detect set usb int bit clear active bit notes: 1. only when error counter counted down from 1 to 0. 2. suspend mode may be entered only when run/stop bit is 0.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 205 5?intel ? 6300ESB ich the qh contains two link pointers and is organized as two contiguous dwords. the first dword is a horizontal pointer (queue head link pointer), used to link a single transfer queue with either another transfer queue, or a td (target data structure depends on q bit). when the t bit is set, this qh represents the last data structure in the current frame. the t bit informs the intel ? 6300ESB ich that no further processing is required until the beginning of the next frame. the second dword is a vertical pointer (queue element link pointer) to the first data structure (td or qh) being managed by this qh. when the t bit is set, the queue is empty. this pointer may reference a td or another qh. figure 19 illustrates four example queue conditions. the first qh (on far left) is an example of an ?empty? queue; the termination bit (t bit), in the vertical link pointer field, is set to 1. the horizontal link pointer references another qh. the next queue is the expected typical configuration. the horizontal link pointer references another qh, and the vertical link pointer references a valid td. typically, the vertical pointer in a qh points to a td. however, as shown in figure 19 (third example from left side of figure) the vertical pointer could point to another qh. when this occurs, a new q context is entered and the q context just exited is null (the intel ? 6300ESB ich will not update the vertical pointer field). the far right qh is an example of a frame ?termination? node. since its horizontal link pointer has its termination bit set, the intel ? 6300ESB ich assumes there is no more work to complete for the current frame. transfer queues are based on the following characteristics: ? a qh?s vertical link pointer (queue element link pointer) references the ?top? queue member. a qh?s horizontal link pointer (queue head link pointer) references the ?next? work element in the frame. ? each queue member?s link pointer references the next element within the queue. in the simplest model, the intel ? 6300ESB ich follows vertical link point to a queue element, then executes the element. when the completion status of the td satisfies the advance criteria as shown in tab le 9 5 , the intel ? 6300ESB ich advances the queue figure 19. example queue conditions f r a m e l i s t p o i n t e r q t 0 1 2 31 l i n k p o i n t e r ( h o r i z ) q t 0 1 2 31 link pointer (vert) q t i n d i c a t e s ' n u l l ' q u e u e h e a d l i n k p o i n t e r q t t d q h l i n k p o i n t e r q t t d l i n k p o i n t e r q t t d indicates 'nil' next pointer indicates 'nil' next pointer q h l i n k p o i n t e r ( h o r i z ) q t 0 1 2 31 link pointer (vert) q t q h l i n k p o i n t e r ( h o r i z ) q t 0 1 2 31 link pointer (vert) q t q h l i n k p o i n t e r ( h o r i z ) q t 0 1 2 31 link pointer (vert) q t q h l i n k p o i n t e r ( h o r i z ) q t 0 1 2 31 link pointer (vert) q t l i n k p o i n t e r q t t d l i n k p o i n t e r q t t d l i n k p o i n t e r ( h o r z ) = q u e u e h e a d l i n k p o i n t e r f i e l d i n q h d w o r d 0 l i n k p o i n t e r ( v e r t ) = q u e u e e l e m e n t l i n k p o i n t e r f i e l d i n q h d w o r d 1
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 206 order number: 300641-004us by writing the just-executed td?s link pointer back into the qh?s queue element link pointer. the next time the queue head is traversed, the next queue element will be the top element. the traversal has two options: breadth first, or depth first. a flag bit in each td (vf - vertical traversal flag) controls whether traversal is breadth or depth first. the default mode of traversal is breadth-first. for breadth-first, the intel ? 6300ESB ich only executes the top element from each queue. the execution path is shown below: 1. qh (queue element link pointer) 2. td 3. write-back to qh (queue element link pointer) 4. qh (queue head link pointer). breadth-first is also performed for every transaction execution that fails the advance criteria. this means that when a queued td fails, the queue does not advance and the intel ? 6300ESB ich traverses the qh?s queue head link pointer. in a depth-first traversal, the top queue element must complete successfully to satisfy the advance criteria for the queue. when the intel ? 6300ESB ich is currently processing a queue, and the advance criteria are met, and the vf bit is set, the intel ? 6300ESB ich follows the td?s link pointer to the next schedule work item. note that regardless of traversal model, when the advance criteria are met, the successful td?s link pointer is written back to the qh?s queue element link pointer. when the intel ? 6300ESB ich encounters a qh, it caches the qh internally, and sets internal state to indicate it is in a q-context. it needs this state to update the correct qh (for auto advancement) and also to make the correct decisions on how to traverse the frame list. restricting the advancement of queues to advancement criteria implements an ensured data delivery stream. a queue is never advanced on an error completion status (even in the event the error count was exhausted). ta b l e 9 5 lists the general queue advance criteria, which are based on the execution status of the td at the ?top? of a currently ?active? queue. ta b l e 9 6 is a decision table illustrating the valid combinations of link pointer bits and the valid actions taken when advancement criteria for a queued transfer descriptor are met. the column headings for the link pointer fields are encoded, based on the following list: table 95. queue advance criteria function-to-host (in) host-to-function (out) non-null null error/nak non-null null error/nak advance q advance q retry q element advance q advance q retry q element
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 207 5?intel ? 6300ESB ich legend: qh.lp = queue head link pointer (or horizontal link pointer) qe.q = q bit in qe qe.lp = queue element link pointer (or vertical link pointer) qe.t = t bit in qe td.lp = td link pointer td. vf = vf bit in td qh.q = q bit in qh td.q = q bit in td qh.t = t bit in qh td. t = t bit in td q t qhlp qh qt qelp qe vf tdlp td vf q t table 96. usb schedule list traversal decision table q contex t qh.q qh.t qe.q qe.t td.vf td.q td.t description 0 ----x00 not in queue - execute td. use td.lp to get next td 0 - - - - x x 1 not in queue - execute td. end of frame 0 ----x10 not in queue - execute td. use td.lp to get next (qh+qe). set q context to 1. 1 00000xx in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. use qh.lp to get next td. 1 xx00100 in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. use td.lp to get next td. 1 xx00110 in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. use td.lp to get next (qh+qe). 100x1xxx in queue. empty queue. use qh.lp to get next td 1 x x 1 0 - - - in queue. use qe.lp to get (qh+qe) 1 x1000xx in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. end of frame 1 x 1 x 1 x x x in queue. empty queue. end of frame 1 10000xx in queue. use qe.lp to get td. execute td. update qe.lp with td.lp. use qh.lp to get next (qh+qe). 110x1xxx in queue. empty queue. use qh.lp to get next (qh+qe)
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 208 order number: 300641-004us 5.17.4 data encoding and bit stuffing the usb employs nrzi data encoding (non-return to zero inverted) when transmitting packets. in nrzi encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. a string of zeros causes the nrzi data to toggle each bit time. a string of ones causes long periods with no transitions in the data. in order to ensure adequate signal transitions, bit stuffing is employed by the transmitting device when sending a packet on the usb. a zero is inserted after every six consecutive ones in the data stream before the data is nrzi encoded to force a transition in the nrzi data stream. this gives the receiver logic a data transition at least once every seven bit times to ensure the data and clock lock. a waveform of the data encoding is shown in figure 20 . bit stuffing is enabled beginning with the sync pattern and throughout the entire transmission. the data ?one? that ends the sync pattern is counted as the first one in a sequence. bit stuffing is always enforced, without exception. when required by the bit stuffing rules, a zero bit will be inserted even when it is the last bit before the end-of- packet (eop) signal. 5.17.5 bus protocol 5.17.5.1 bit ordering bits are sent out onto the bus least significant bit (lsb) first, followed by next lsb, through to the most significant bit (msb) last. 5.17.5.2 sync field all packets begin with a synchronization (sync) field, which is a coded sequence that generates a maximum edge transition density. the sync field appears on the bus as idle followed by the binary string ?kjkjkjkk,? in its nrzi encoding. it is used by the input circuitry to align incoming data with the local clock and is defined to be eight bits in length. sync serves only as a synchronization mechanism and is not shown in the following packet diagrams. the last two bits in the sync field are a marker that is used to identify the first bit of the pid. all subsequent bits in the packet must be indexed from this point. 5.17.5.3 packet field formats field formats for the token, data, and handshake packets are described in the following section. the effects of nrzi coding and bit stuffing have been removed for the sake of clarity. all packets have distinct start and end of packet delimiters. figure 20. usb data encoding clock data bit stuffed data nrzi data
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 209 5?intel ? 6300ESB ich table 97. pid format bit data sent bit data sent 0pid 0 4not(pid 0) 1pid 1 5not(pid 1) 2pid 2 6not(pid 2) 3pid 3 7not(pid 3)
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 210 order number: 300641-004us packet identifier field a packet identifier (pid) immediately follows the sync field of every usb packet. a pid consists of a four bit packet type field followed by a four-bit check field as shown in ta b l e 9 7 . the pid indicates the type of packet and, by inference, the format of the packet and the type of error detection applied to the packet. the four-bit check field of the pid insures reliable decoding of the pid so that the remainder of the packet is interpreted correctly. the pid check field is generated by performing a ones complement of the packet type field. any pid received with a failed check field or which decodes to a non-defined value is assumed to be corrupted and the remainder of the packet is assumed to be corrupted and is ignored by the receiver. pid types, codes, and descriptions are listed in tab l e 9 8 . pids are divided into four coding groups: token, data, handshake, and special, with the first two transmitted pid bits (pid[1:0]) indicating which group. this accounts for the distribution of pid codes. 5.17.5.4 address fields function endpoints are addressed using two fields: the function address field and endpoint field. address field table 98. pid types pid type pid name pid[3:0] description to k e n out b0001 address + endpoint number in host -> function transaction in b1001 address + endpoint number in function -> host transaction sof b0101 start of frame marker and frame number setup b1101 address + endpoint number in host -> function transaction for setup to a control endpoint data data0 b0011 data packet pid even data1 b1011 data packet pid odd handshake ack b0010 receiver accepts error free data packet nak b1010 rx device cannot accept data or tx device cannot send data stall b1110 endpoint is stalled special pre b1100 host-issued preamble. enables downstream bus traffic to low speed devices. table 99. address field bit data sent bit data sent 0addr 0 4 addr 4 1addr 1 5 addr 5 2addr 2 6 addr 6 3addr 3
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 211 5?intel ? 6300ESB ich the function address (addr) field specifies the function, through its address, that is either the source or destination of a data packet, depending on the value of the token pid. as shown in tab le 9 9 , a total of 128 addresses are specified as addr[6:0]. the addr field is specified for in, setup, and out tokens. endpoint field an additional four-bit endpoint (endp) field, shown in table 100 , permits more flexible addressing of functions in which more than one sub-channel is required. endpoint numbers are function specific. the endpoint field is defined for in, setup, and out token pids only. 5.17.5.5 frame number field the frame number field is an 11-bit field that is incremented by the host on a per frame basis. the frame number field rolls over upon reaching its maximum value of x7ff, and is sent only for sof tokens at the start of each frame. 5.17.5.6 data field the data field may range from zero to 1023 bytes and must be an integral numbers of bytes. data bits within each byte are shifted out lsb first. 5.17.5.7 cyclic redundancy check (crc) crc is used to protect the all non-pid fields in token and data packets. in this context, these fields are considered to be protected fields. the pid is not included in the crc check of a packet containing crc. all crcs are generated over their respective fields in the transmitter before bit stuffing is performed. similarly, crcs are decoded in the receiver after stuffed bits have been removed. token and data packet crcs provide 100% coverage for all single and double bit errors. a failed crc is considered to indicate that one or more of the protected fields is corrupted and causes the receiver to ignore those fields, and, in most cases, the entire packet. 5.17.6 packet formats 5.17.6.1 token packets table 101 shows the field formats for a token packet. a token consists of a pid, specifying either in, out, or setup packet type, and addr and endp fields. for out and setup transactions, the address and endpoint fields uniquely identify the endpoint that will receive the subsequent data packet. for in transactions, these fields uniquely identify which endpoint should transmit a data packet. only the intel ? 6300ESB ich may issue token packets. in pids define a data transaction from a function to the intel ? 6300ESB ich. out and setup pids define data transactions from the intel ? 6300ESB ich to a function. table 100. endpoint field bit data sent 0endp 0 1endp 1 2endp 2 3endp 3
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 212 order number: 300641-004us token packets have a five-bit crc which covers the address and endpoint fields as shown above. the crc does not cover the pid, which has its own check field. token and sof packets are delimited by an eop after three bytes of packet field data. when a packet decodes as an otherwise valid token or sof but does not terminate with an eop after three bytes, it must be considered invalid and ignored by the receiver. 5.17.6.2 start of frame packets table 102 shows a start of frame (sof) packet. sof packets are issued by the host at a nominal rate of once every 1.00 ms +/- 0.05. sof packets consist of a pid indicating packet type followed by an 11-bit frame number field. the sof token comprises the token-only transaction that distributes a start of frame marker and accompanying frame number at precisely timed intervals corresponding to the start of each frame. all full speed functions, including hubs, must receive and decode the sof packet. the sof token does not cause any receiving function to generate a return packet; therefore, sof delivery to any given function cannot be ensured. the sof packet delivers two pieces of timing information. a function is informed that a start of frame has occurred when it detects the sof pid. frame timing sensitive functions, which do not need to keep track of frame number, need only decode the sof pid; they may ignore the frame number and its crc. when a function needs to track frame number, it must comprehend both the pid and the time stamp. 5.17.6.3 data packets a data packet consists of a pid, a data field, and a crc as shown in ta b l e 1 0 3 . there are two types of data packets, identified by differing pids: data0 and data1. two data packet pids are defined to support data toggle synchronization. data must always be sent in integral numbers of bytes. the data crc is computed over only the data field in the packet and does not include the pid, which has its own check field. table 101. token format packet width pid 8 bits addr 7 bits endp 4 bits crc5 5 bits table 102. sof packet packet width pid 8 bits frame number 11 bits crc5 5 bits table 103. data packet format packet width pid 8 bits data 0-1023 bytes crc16 16 bits
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 213 5?intel ? 6300ESB ich 5.17.6.4 handshake packets handshake packets consist of only a pid. handshake packets are used to report the status of a data transaction and may return values indicating successful reception of data, flow control, and stall conditions. only transaction types that support flow control may return handshakes. handshakes are always returned in the handshake phase of a transaction and may be returned, instead of data, in the data phase. handshake packets are delimited by an eop after one byte of packet field. when a packet is decoded as an otherwise valid handshake but does not terminate with an eop after one byte, it must be considered invalid and ignored by the receiver. there are three types of handshake packets: ? ack indicates that the data packet was received without bit stuff or crc errors over the data field and that the data pid was received correctly. an ack handshake is applicable only in transactions in which data has been transmitted and where a handshake is expected. ack may be returned by the host for in transactions and by a function for out transactions. ? nak indicates that a function was unable to accept data from the host (out) or that a function has no data to transmit to the host (in). nak may only be returned by functions in the data phase of in transactions or the handshake phase of out transactions. the host may not issue a nak. nak is used for flow control purposes to indicate that a function is temporarily unable to transmit or receive data, but will eventually be able to do so without need of host intervention. nak is also used by interrupt endpoints to indicate that no interrupt is pending. ? stall is returned by a function in response to an in token or after the data phase of an out. stall indicates that a function is unable to transmit or receive data, and that the condition requires host intervention to remove the stall. once a function?s endpoint is stalled, the function must continue returning stall until the condition causing the stall has been cleared through host intervention. the host is not permitted to return a stall under any condition. 5.17.6.5 handshake responses in transaction a function may respond to an in transaction with a stall or nak. when the token received was corrupted, the function will issue no response. when the function may transmit data, it will issue the data packet. the intel ? 6300ESB ich, as the usb host, may return only one type of handshake on an in transaction, an ack. when it receives a corrupted data, or cannot accept data due to a condition such as an internal buffer overrun, it discards the data and issues no response. out transaction a function may respond to an out transaction with a stall, ack, or nak. when the transaction contained corrupted data, it will issue no response. setup transaction setup defines a special type of host to function data transaction which permits the host to initialize an endpoint?s synchronization bits to those of the host. upon receiving a setup transaction, a function must accept the data. setup transactions cannot be stalled or naked and the receiving function must accept the setup transfer?s data. when a non-control endpoint receives a setup pid, it must ignore the transaction and return no response.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 214 order number: 300641-004us 5.17.7 usb interrupts 5.17.7.1 overview there are two general groups of usb interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from an intel ? 6300ESB ich operation error. all transaction-based sources may be masked by software through the intel ? 6300ESB ich?s interrupt enable register. additionally, individual transfer descriptors may be marked to generate an interrupt on completion. when the intel ? 6300ESB ich drives an interrupt for usb, it internally drives the pirq[a]# pin for usb function #0, pirq[d]# pin for usb function #1 until all sources of the interrupt are cleared. in order to accommodate some operating systems, the interrupt pin register must contain a different value for each function of this new multi- function device. 5.17.7.2 transaction based interrupts these interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. this ensures that software may safely process through (frame list current index -1) when it is servicing an interrupt. crc error/time-out a crc/time-out error occurs when a packet transmitted from the intel ? 6300ESB ich to a usb device or a packet transmitted from a usb device to the intel ? 6300ESB ich generates a crc error. the intel ? 6300ESB ich is informed of this event by a time-out from the usb device or by the intel ? 6300ESB ich?s crc checker generating an error on reception of the packet. additionally, a usb bus time-out occurs when usb devices do not respond to a transaction phase within 19-bit times of an eop. either of these conditions will cause the c_err field of the td to decrement. when the c_err field decrements to zero, the following occurs: ? the active bit in the td is cleared ? the stalled bit in the td is set ? the crc/time-out bit in the td is set. ? at the end of the frame, the usb error interrupt bit is set in the hc status register. when the crc/time out interrupt is enabled in the interrupt enable register, a hardware interrupt will be signaled to the system. interrupt on completion transfer descriptors contain a bit that may be set to cause an interrupt on their completion. the completion of the transaction associated with that block causes the usb interrupt bit in the hc status register to be set at the end of the frame in which the transfer completed. when a td is encountered with the ioc bit set to 1, the ioc bit in the hc status register is set to 1 at the end of the frame when the active bit in the td is set to 0 (even when it was set to zero when initially read). when the ioc enable bit of interrupt enable register (bit 2 of i/o offset 04h) is set, a hardware interrupt is signaled to the system. the usb interrupt bit in the hc status register is set either when the td completes successfully or because of errors. when the completion is because of errors, the usb error bit in the hc status register is also set. short packet detect
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 215 5?intel ? 6300ESB ich a transfer set is a collection of data which requires more than one usb transaction to completely move the data across the usb interface. an example might be a large print file which requires numerous tds in multiple frames to completely transfer the data. reception of a data packet that is less than the endpoint?s max packet size during control, bulk or interrupt transfers signals the completion of the transfer set, even when there are active tds remaining for this transfer set. setting the spd bit in a td indicates to the hc to set the usb interrupt bit in the hc status register at the end of the frame in which this event occurs. this feature streamlines the processing of input on these transfer types. when the short packet interrupt enable bit in the interrupt enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred. serial bus babble when a device transmits on the usb for a time greater than its assigned max length, it is said to be babbling. since isochrony may be destroyed by a babbling device, this error results in the active bit in the td being cleared to 0 and the stalled and babble bits being set to one. the c_err field is not decremented for a babble. the usb error interrupt bit in the hc status register is set to 1 at the end of the frame. a hardware interrupt is signaled to the system. when an eof babble was caused by the intel ? 6300ESB ich (due to incorrect schedule for instance), the intel ? 6300ESB ich will force a bit stuff error followed by an eop and the start of the next frame. stalled this event indicates that a device/endpoint returned a stall handshake during a transaction or that the transaction ended in an error condition. the tds stalled bit is set and the active bit is cleared. reception of a stall does not decrement the error counter. a hardware interrupt is signaled to the system. data buffer error this event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. this would generally be caused by the intel ? 6300ESB ich not being able to access required data buffers in memory within necessary latency requirements. either of these conditions will cause the c_err field of the td to be decremented. when c_err decrements to zero, the active bit in the td is cleared, the stalled bit is set, the usb error interrupt bit in the hc status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. bit stuff error a bit stuff error results from the detection of a sequence of more that 6 ones in a row within the incoming data stream. this will cause the c_err field of the td to be decremented. when the c_err field decrements to 0, the active bit in the td is cleared to 0, the stalled bit is set to one, the usb error interrupt bit in the hc status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 216 order number: 300641-004us 5.17.7.3 non-transaction based interrupts when an intel ? 6300ESB ich process error or system error occurs, the intel ? 6300ESB ich halts and immediately issues a hardware interrupt to the system. resume received this event indicates that the intel ? 6300ESB ich received a resume signal from a device on the usb bus during a global suspend. when this interrupt is enabled in the interrupt enable register, a hardware interrupt will be signaled to the system allowing the usb to be brought out of the suspend state and returned to normal operation. intel ? 6300ESB ich process error the hc monitors certain critical fields during operation to ensure that it does not process corrupted data structures. these include checking for a valid pid and verifying that the maxlength field is less than 1280. when it detects a condition that would indicate that it is processing corrupted data structures, it immediately halts processing, sets the hc process error bit in the hc status register and signals a hardware interrupt to the system. this interrupt cannot be disabled through the interrupt enable register. host system error the intel ? 6300ESB ich sets this bit to 1 when a pci parity error, pci master abort, or pci target abort occur. when this error occurs, the intel ? 6300ESB ich clears the run/ stop bit in the command register to prevent further execution of the scheduled tds. this interrupt cannot be disabled through the interrupt enable register. 5.17.8 usb power management the host controller may be put into a suspended state and its power may be removed. this requires that certain bits of information are retained in the resume power plane of the intel ? 6300ESB ich so that a device on a port may wake the system. such a device may be a fax-modem, which will wake up the machine to receive a fax or take a voice message. the settings of the following bits in i/o space will be maintained when the intel ? 6300ESB ich enters the s3, s4 or s5 states: when the intel ? 6300ESB ich detects a resume event on any of its ports, it will set the corresponding usb_sts bit in acpi space. when usb is enabled as a wake/break event, the system will wake up and an sci will be generated. table 104. bits maintained in low power states register offset bit description command 00h 3 enter global suspend mode (egsm) status 02h 2 resume detect port status and control 10h and 12h 2 port enabled/disabled 6resume detect 8 low speed device attached 12 suspend
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 217 5?intel ? 6300ESB ich 5.17.9 usb legacy keyboard operation typically when a usb keyboard is plugged into the system, and a standard keyboard is not, the system may not boot, and dos legacy software will not run, because the keyboard will not be identified. in an intel ? 6300ESB ich system port 60/64 emulation will allow the usb keyboard and dos legacy software to run. port 60/64 emulation registers may be enabled by bios typically in a pre-os environment and may be disabled during run time. the intel ? 6300ESB ich implements a series of trapping operations that will snoop accesses that typically go to the keyboard controller and put the expected data from the usb keyboard into ports 60/64. the following table summarizes the implementation of the bits in the usb legacy keyboard/mouse control registers. table 105. usb legacy keyboard/mouse control register bit implementation (sheet 1 of 2) bit # bit name summary details 15 smi caused by end of pass- through logically 1 bit for all controllers note this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a one to this bit in any of the three host controllers. this bit may either be implemented separately for each controller or shared and aliased. 13 pci interrupt enable independent enable each bit provides individual host control. 12 smi caused by usb interrupt independent status individual status bits for each controller. 11 smi caused by port 64 write logically 1 bit for all controllers note this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a one to this bit in any of the three host controllers. this bit may either be implemented separately for each controller or shared and aliased. 10 smi caused by port 64 read logically 1 bit for all controllers note this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a one to this bit in any of the three host controllers. this bit may either be implemented separately for each controller or shared and aliased. 9 smi caused by port 60 write logically 1 bit for all controllers note this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a one to this bit in any of the three host controllers. this bit may either be implemented separately for each controller or shared and aliased. 8 smi caused by port 60 read logically 1 bit for all controllers note this bit in all host controllers will be set at the same time and cleared at the same time. it is cleared whenever software writes a one to this bit in any of the three host controllers. this bit may either be implemented separately for each controller or shared and aliased. 7 smi at end of pass-through enable separate enables ored together this bit enables the generation of the smi based on bit 15 within the same function. when bit 15 is implemented as a shared/aliased bit across all functions, the bit 7?s from all three controllers are ored together and used to enable the smi based on bit 15. 6 pass through state logically 1 bit for all controllers this bit in all host controllers reflects the state of the pass-through state machine. software may force this bit to zero by clearing the a20gate pass-through enable (bit 5) in all of the host controllers. 5 a20gate pass- through enable ored together to enable the pass-through state machine when any of these bits in the three host controllers is set, the intel ? 6300ESB ich will enable the legacy keyboard a20gate pass-through sequence. this prevents the smi status bits (11:8) from asserting in all three controllers when the specific sequence of i/o cycles is observed.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 218 order number: 300641-004us note: the scheme described below assumes that the keyboard controller (8042 or equivalent) is on the lpc bus. this legacy operation is performed through smm space. figure 21 shows the enable and status path. the latched smi source (60r, 60w, 64r, 64w) is available in the status register. since the enable is after the latch, it is possible to check for other events that didn't necessarily cause an smi. it is the software's responsibility to logically and the value with the appropriate enable bits. note also that the smi is generated before the pci cycle completes (e.g., before trdy# goes active) to ensure that the processor doesn't complete the cycle before the smi is observed. this method is used on mpiix and has been validated. the logic will also need to block the accesses to the 8042. when there is an external 8042, then this is simply accomplished by not activating the 8042 cs. this is simply done by logically anding the four enables (60r, 60w, 64r, 64w) with the four types of accesses to determine when 8042cs should go active. an additional term is required for the ?pass-through? case. the state table for the diagram is shown in table 106 . 4smi on usb irq independent enable each bit provides individual host control. 3 smi on port 64 writes enable separate enables ored together each bit enables smi generation when the corresponding bit 11 is set. when bit 11 is implemented as a shared/aliased bit across all functions, then the bit 3?s from all three controllers are ored together and used to enable the smi based on bit 11. 2 smi on port 64 reads enable separate enables or?ed together each bit enables smi generation if the corresponding bit 10 is set. if bit 10 is implemented as a shared/aliased bit across all functions, then the bit 2's from all three controllers are or'ed together and used to enable the smi based on bit 10. 1 smi on port 60 writes enable separate enables or?ed together each bit enables smi generation if the corresponding bit 9 is set. if bit 9 is implemented as a shared/aliased bit across all functions, then the bit 1's from all three controllers are or'ed together and used to enable the smi based on bit 9. 0 smi on port 60 reads enable separate enables or?ed together each bit enables smi generation if the corresponding bit 8 is set. if bit 8 is implemented as a shared/aliased bit across all functions, then the bit 0's from all three controllers are or'ed together and used to enable the smi based on bit 8. note: if bit 7 of the extended test mode register 1 (d31:f0, offset f4h etr1, section 9.1.36) is set. port 60/64h reads and writes from an external pci agent will not affect set bits 8-11 and will not cause an smi independent of the setting of bits 0-3 table 105. usb legacy keyboard/mouse control register bit implementation (sheet 2 of 2) bit # bit name summary details
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 219 5?intel ? 6300ESB ich figure 21. usb legacy keyboard flow diagram kbc accesses pci config read, write 60 read clear smi_60_r en_smi_on_60r comb . decoder and same for 60w, 64r, 64w smi or to individual "caused by" "bits" to pirqd# to "caused by" bit and and en_pirqd# usb_irq clear usb_irq en_smi_on_irq s d r s d r not (north pci gnt) north pci cycle
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 220 order number: 300641-004us table 106. usb legacy keyboard state transitions current state action data value next state comment idle 64h / write d1h gatestate 1 standard d1 command. cycle passed through to 8042. smi# doesn't go active. pstate (offset c0, bit 6) goes to 1. idle 64h / write not d1h idle bit 3 in config register determines if cycle passed through to 8042 and if smi# generated. idle 64h / read n/a idle bit 2 in config register determines if cycle passed through to 8042 and if smi# generated. idle 60h / write don't care idle bit 1 in config register determines if cycle passed through to 8042 and if smi# generated. idle 60h / read n/a idle bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. gatestate1 60h / write xxh gatestate 2 cycle passed through to 8042, even if trap enabled in bit 1 in config register. no smi# generated. pstate remains 1. when data value is not dfh or ddh then the 8042 may chose to ignore it. gatestate1 64h / write d1h gatestate 1 cycle passed through to 8042, even if trap enabled through bit 3 in config register. no smi# generated. pstate remains 1. stay in gatestate1 because this is part of the double-trigger sequence. gatestate1 64h / write not d1h idle bit 3 in config space determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. when bit 7 in config register is set, then smi# should be generated. gatestate1 60h / read n/a idle this is an invalid sequence. bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. when bit 7 in config register is set, then smi# should be generated. gatestate1 64h / read n/a gatestate 1 just stay in same state. generate an smi# when enabled in bit 2 of config register. pstate remains 1. gatestate2 64 / write ffh idle standard end of sequence. cycle passed through to 8042. pstate goes to 0. bit 7 in config space determines if smi# should be generated. gatestate2 64h / write not ffh idle improper end of sequence. bit 3 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. when bit 7 in config register is set, then smi# should be generated. gatestate2 64h / read n/a gatestate 2 just stay in same state. generate an smi# when enabled in bit 2 of config register. pstate remains 1.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 221 5?intel ? 6300ESB ich 5.18 usb ehci controller (d29:f7) 5.18.1 overview the intel ? 6300ESB ich contains an enhanced host controller interface (ehci) compliant host controller which supports up to four high-speed usb 2.0 specification compliant root ports. high-speed usb 2.0 allows data transfers up to 480 mbps using the same pins as the four full-speed and low-speed usb universal host controller interface (uhci) ports. the intel ? 6300ESB ich contains port-routing logic that determines whether a usb port is controlled by one of the uhci controllers or by the ehci controller. a usb 2.0 based debug port is also implemented in the intel ? 6300ESB ich. a summary of the key architectural differences between the usb uhci host controllers and the usb ehci host controller are shown in the table below: 5.18.2 ehc initialization the following descriptions step through the expected intel ? 6300ESB ich enhanced host controller (ehc) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off. gatestate2 60h / write xxh idle improper end of sequence. bit 1 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. when bit 7 in config register is set, then smi# should be generated. gatestate2 60h / read n/a idle improper end of sequence. bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. when bit 7 in config register is set, then smi# should be generated. notes: 1. if bit 7 of the extended test mode register 1 (d31:f0, offset f4h etr1, section 9.1.36) is set. port 60/64h reads and writes from an external pci agent will not affect set bits 8-11 and will not cause an smi independent of the setting of bits 0-3 2. system software should ensure that the host controller and an external pci agent are not simultaneously executing keyboard accesses including an a20gate pass-through sequence to port 60h & 64h. this is not supported and the results may be indeterminate. table 106. usb legacy keyboard state transitions current state action data value next state comment table 107. uhci vs. ehci feature usb 1.1 uhci usb 2.0 ehci accessible by i/o space memory space memory data structure single linked list separated into periodic and asynchronous lists. differential signaling voltage 3.3 v 400 mv ports per controller 2 4
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 222 order number: 300641-004us 5.18.2.1 power on the suspend well is a ?deeper? power plane than the core well, which means that the suspend well is always functional when the core well is functional but the core well may not be functional when the suspend well is. therefore, the suspend well reset pin (rsmrst#) deasserts before the core well reset pin (pwrok) rises. 1. the suspend well reset deasserts, leaving all registers and logic in the suspend well in the default state. however, it is not possible to read any registers until after the core well reset deasserts. note that normally the suspend well reset will only occur when a desktop system is unplugged or the battery is removed from a mobile system. in other words, suspend well resets are not easily achieved by software or the end-user. this step will typically not occur immediately before the remaining steps. 2. the core well reset deasserts, leaving all registers and logic in the core well in the default state. the ehc configuration space is accessible at this point. note that the core well reset may (and typically does) occur without the suspend well reset asserting. this means that all of the configure flag and port status and control bits (and any other suspend-well logic) may be in any valid state at this time. 5.18.2.2 bios initialization bios performs a number of platform customization steps after the core well has powered up as described in the intel ? 6300ESB ich bios specification . 5.18.2.3 driver initialization see chapter 4 of the enhanced host controller interface specification for universal serial bus, revision 0.96 . 5.18.2.4 ehc resets in addition to the standard intel ? 6300ESB ich hardware resets, portions of the ehc are reset by the hcreset bit and the transition from the d3hot device power management state to the d0 state. the effects of each of these resets are:
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 223 5?intel ? 6300ESB ich when the detailed register descriptions give exceptions to these rules, those exceptions override these rules. this summary is provided to help explain the reasons for the reset policies. 5.18.3 data structures in main memory see section 3 and appendix b of the enhanced host controller interface specification for universal serial bus, revision 0.96. table 108. ehc resets reset does reset does not reset comments hcreset bit set memory space registers except structural parameters (which is written by bios). configuration registers the hcreset must only affect registers that the ehci driver controls. pci configuration space and bios-programmed parameters cannot be reset. see section 11.2.2.1, ?offset caplength + 00 - 03h: usb ehci cmd?usb ehci command register? for information regarding offset 00h, bit 1. software writes the device power state from d3 hot (11b) to d0 (00b). core well registers (except bios- programmed registers). suspend well registers; bios- programmed core well registers the d3-to-d0 transition must not cause wake information (suspend well) to be lost. it also must not clear bios- programmed registers because bios may not be invoked following the d3-to- d0 transition. see section 11.1.17, ?offset 54 - 55h: power management control/status? for more information.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 224 order number: 300641-004us 5.18.4 usb 2.0 enhanced host controller dma the intel ? 6300ESB ich usb 2.0 ehc implements three sources of usb packets. they are, in order of priority on usb during each microframe: 1. usb 2.0 debug port (see section 5.18.11, ?usb 2.0 ehci based debug port? ) 2. periodic dma engine 3. asynchronous dma engine the intel ? 6300ESB ich always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. when there is time left in the microframe, then the ehc performs any pending asynchronous traffic until the end of the microframe (eof1). note that the debug port traffic is only presented on one port (port #0), while the other ports are idle during this time. the following subsections describe the policies of the periodic and asynchronous dma engines. 5.18.4.1 periodic list execution the periodic dma engine contains buffering for two control structures (two transactions). by implementing two entries, the ehc is able to pipeline the memory accesses for the next transaction while executing the current transaction on the usb ports. note that a multiple-packet, high-bandwidth transaction occupies one of these buffer entries, which means that up to six 1-kbyte data packets may be associated with the two buffered control structures. 5.18.4.1.1 read policies for periodic dma the periodic dma engine performs reads for the following structures. table 109. read policies for periodic dma memory structure size (dwords) comments periodic frame list entry 1 the ehc reads the entry for each microframe. the frame list is not internally cached across microframes. itd 23 only the 64-bit addressing format is supported. sitd 9 only the 64-bit addressing format is supported. qtd 13 only the 64-bit addressing format is supported. queue head 17 only the 64-bit addressing format is supported. out data up to 257 the intel ? 6300ESB ich breaks large read requests down into smaller aligned read requests based on the setting of the read request max length field. frame span transversa l no de 2
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 225 5?intel ? 6300ESB ich the ehc periodic dma engine (pde) does not generate accesses to main memory unless all three of the following conditions are met. ? the hchalted bit is 0 (memory space, offset 04h, bit 12). software clears this bit indirectly by setting the run/stop bit to 1. see section 11.2.2.2, ?offset caplength + 04 - 07h: usb ehci sts?usb ehci status? for more information. ? the periodic schedule status bit is 1 (memory space, offset 04h, bit 14). software sets this bit indirectly by setting the periodic schedule enable bit to 1. see section 11.2.2.2, ?offset caplength + 04 - 07h: usb ehci sts?usb ehci status? for more information. ? the bus master enable bit is 1 (configuration space, offset 04h, bit 2). see section 11.1.1, ?offset 04 - 05h: command register? for more information. note: prefetching is limited to the current and next microframes only. note: once the pde checks the length of a periodic packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the ehc switches over to run asynchronous traffic. 5.18.4.1.2 write policies for periodic dma the periodic dma engine performs writes for the following reasons. table 110. write policies for periodic dma memory structure size (dwords ) comments itd status write 1 only the dword that corresponds to the just- executed microframe?s status is written. all bytes of the dword are written. sitd status write 3 dwords 0c:17h are written. ioc and buffer pointer fields are re-written with the original value. interrupt queue head overlay 14 only the 64-bit addressing format is supported. dwords 0c:43h are written. interrupt queue head status write 5 dwords 14:27h are written. interrupt qtd status write 3 dwords 04:0fh are written. pid code, ioc, buffer pointers, and alt. next qtd pointers are re-written with the original value. in data up to 257 the intel ? 6300ESB ich breaks data writes down into 16 dword aligned chunks. notes: 1. the periodic dma engine (pde) will only generate writes after a transaction is executed on usb. 2. status writes are always performed after in data writes for the same transaction.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 226 order number: 300641-004us 5.18.4.2 asynchronous list execution the asynchronous dma engine contains buffering for two control structures (two transactions). by implementing two entries, the ehc is able to pipeline the memory accesses for the next transaction while executing the current transaction on the usb ports. 5.18.4.2.1 read policies for asynchronous dma the asynchronous dma engine performs reads for the following structures. the ehc asynchronous dma engine (ade) does not generate accesses to main memory unless all four of the following conditions are met. (note that the ade may be active when the periodic schedule is actively executed, unlike the description in the ehci specification; since the ehc contains independent dma engines, the ade may perform memory accesses interleaved with the pde accesses.) ? the hchalted bit is 0 (memory space, offset 04h, bit 12). software clears this bit indirectly by setting the run/stop bit to 1. ? the asynchronous schedule status bit is 1 (memory space, offset 04h, bit 15). software sets this bit indirectly by setting the asynchronous schedule enable bit to 1. see section 11.2.2.2, ?offset caplength + 04 - 07h: usb ehci sts?usb ehci status? for more information. ? the bus master enable bit is 1 (configuration space, offset 04h, bit 2). see section 11.1.1, ?offset 04 - 05h: command register? for more information. ? the ade is not sleeping due to the detection of an empty schedule. there is not one single bit that indicates this state. however, the sleeping state is entered when the queue head with the h bit set is encountered when the reclamation bit in the usb ehci status register is 0. see section 11.2.2.2, ?offset caplength + 04 - 07h: usb ehci sts?usb ehci status? for information regarding offset 04h, bit 13. note: the ade does not fetch data when a qh is encountered in the ping state. an ack handshake in response to the ping results in the ade writing the qh to the out state, which results in the fetching and delivery of the out data on the next iteration through the asynchronous list. note: once the ade checks the length of an asynchronous packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the ehc stops all activity on the usb ports for the remainder of that microframe. note: once the ade detects an ?empty? asynchronous schedule as described in section 4 of the ehci specification, it implements a waking mechanism like the one in the example. the amount of time that the ade ?sleeps? is 10 s 30 ns. table 111. read policies for asynchronous dma memory structure size (dw) comments qtd 13 only the 64-bit addressing format is supported. queue head 17 only the 64-bit addressing format is supported. out data up to 129 the intel ? 6300ESB ich breaks large read requests down into smaller aligned read requests based on the setting of the read request max length field.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 227 5?intel ? 6300ESB ich 5.18.4.2.2 write policies for asynchronous dma the asynchronous dma engine performs writes for the following reasons. 5.18.5 data encoding and bit stuffing see chapter 8 of the universal serial bus revision 2.0 specification . 5.18.6 packet formats see chapter 8 of the universal serial bus revision 2.0 specification . 5.18.7 usb ehci interrupts and error conditions section 4 of the ehci specification goes into detail on the ehc interrupts and the error conditions that cause them. all error conditions that the ehc detects may be reported through the ehci interrupt status bits. only intel ? 6300ESB ich-specific interrupt and error-reporting behavior is documented in this section. the ehci interrupts section must be read first, followed by this section of the eds to fully comprehend the ehc interrupt and error-reporting functionality. ? based on the ehc?s buffer sizes and buffer management policies, the data buffer error may not occur on the intel ? 6300ESB ich. ? master abort and target abort responses from hub interface on ehc-initiated read packets will be treated as fatal host errors. the ehc halts when these conditions are encountered. ? the intel ? 6300ESB ich may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. the requirement in the ehci specification (that the status is written to memory) is met internally, even though the write may not be seen on the hub interface before the interrupt is asserted. ? since the intel ? 6300ESB ich supports the 1024-element frame list size, the frame list rollover interrupt occurs every 1024 milliseconds. table 112. write policies for asynchronous dma memory structure size (dwords ) comments asynchronous queue head overlay 14 only the 64-bit addressing format is supported. dwords 0c:43h are written. asynchronous queue head status write 34 dwords 14:1fh are written. asynchronous qtd status write 3 dwords 04:0fh are written. pid code, ioc, buffer pointer (page 0), and alt. next qtd pointers are re-written with the original value. in data up to 1297 the intel ? 6300ESB ich breaks data writes down into 16 dword aligned chunks. notes: 1. the asynchronous dma engine (ade) will only generate writes after a transaction is executed on usb. 2. status writes are always performed after in data writes for the same transaction.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 228 order number: 300641-004us ? the intel ? 6300ESB ich delivers interrupts using pirq#[h]. ? the intel ? 6300ESB ich does not modify the cerr count on an interrupt in when the ?do complete-split? execution criteria are not met. ? for complete-split transactions in the periodic list, the ?missed microframe? bit does not get set on a control-structure-fetch that fails the late-start test. when subsequent accesses to that control structure do not fail the late-start test, then the ?missed microframe? bit will get set and written back. 5.18.7.1 aborts on usb ehci-initiated memory reads when a read initiated by the ehc is aborted, the ehc treats it as a fatal host error. the following actions are taken when this occurs: ? the host system error status bit is set. see section 11.2.2.2, ?offset caplength + 04 - 07h: usb ehci sts?usb ehci status? for information regarding offset 04h, bit 4. ? the dma engines are halted after completing up to one more transaction on the usb interface. ? when enabled (by the host system error enable), an interrupt is generated. see section 11.2.2.3, ?offset caplength + 08 - 0bh: usb ehci intr?usb ehci interrupt enable? for information regarding offset 08h, bit 4. ? when the status is master abort, the received master abort bit in configuration space is set. section 11.1.2, ?offset 06 - 07h: device status? for information regarding offset 06h, bit 13. ? when the status is target abort, the received target abort bit in configuration space is set. section 11.1.2, ?offset 06 - 07h: device status? for information regarding offset 06h, bit 12. ? when enabled (by the serr enable bit in the function?s configuration space, see section 11.1.1, ?offset 04 - 05h: command register? , offset 04h, bit 8), the signaled system error bit is set by the intel ? 6300ESB ich when it signals serr# (internally). section 11.1.2, ?offset 06 - 07h: device status? for information regarding offset 06h, bit 14. 5.18.8 usb ehci power management 5.18.8.1 pause feature this feature allows platforms, especially mobile systems, to dynamically enter low- power states during brief periods when the system is idle, i.e., between keystrokes. this is useful for enabling power management features like c3, c4, and intel ? speedstep ? technology in the intel ? 6300ESB ich. the policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. normally, when the ehc is enabled, it regularly accesses main memory while traversing the dma schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. suspending all of the enabled ports may prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the usb ports that makes this unacceptable for the purpose of dynamic power management. as a result, the ehci software drivers are allowed to pause the ehc?s dma engines when it knows that the traffic patterns of the attached devices may afford the delay. the pause only prevents the ehc from generating memory accesses; the sof packets continue to be generated on the usb ports (unlike the suspended state).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 229 5?intel ? 6300ESB ich 5.18.8.2 suspend feature the ehci specification describes the details of port suspend and resume in detail in section 4.3. 5.18.8.3 acpi device states the usb ehci function only supports the d0 and d3 pci power management states. notes regarding the intel ? 6300ESB ich implementation of the device states: 1. the ehc hardware does not inherently consume any more power when it is in the d0 state than it does in the d3 state. however, software is required to suspend or disable all ports prior to entering the d3 state such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ehc features are enabled. 3. in the d3 state, accesses to the ehc memory-mapped i/o range will master abort. note that, since the debug port uses the same memory range, the debug port is only operational when the ehc is in the d0 state. 4. in the d3 state, the ehc interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power state field is written to d0 from d3, an internal reset is generated. see section ehc resets for general rules on the effects of this reset. 6. attempts to write any other value into the device power state field other than 00b (d0 state) and 11b (d3 state) will complete normally without changing the current value in this field. see section 11.1.17, ?offset 54 - 55h: power management control/status? for information regarding offset 54h, bits [1:0]. 5.18.8.4 acpi system states the ehc behavior as it relates to other power management states in the system is summarized in the following list: ? the system is always in the s0 state when the ehc is in the d0 state. however, when the ehc is in the d3 state, the system may be in any power management state (including s0). ? when in d0, the pause feature (see section 5.18.8.1, ?pause feature? ) enables dynamic processor low-power states to be entered. ? all core well logic is reset in the s3/s4/s5 states (core power turns off). 5.18.8.5 low-power system considerations the intel ? 6300ESB ich usb ehci implementation does not behave differently in low power configurations. however, some features may be especially useful for the low power configurations. ? low-power systems are not likely to use all four of the usb ports that are provided on the intel ? 6300ESB ich. with this in mind, the intel ? 6300ESB ich provides mechanisms for changing the structural parameters of the ehc and hiding unused usb uhci controllers. see intel ? 6300ESB ich bios specification on how bios should configure the intel ? 6300ESB ich. ? low-power systems may want to minimize the conditions that will wake the system. the intel ? 6300ESB ich implements the ?wake enable? bits in the port status and control registers, as specified in the ehci spec, for this purpose. ? low-power systems may want to cut suspend well power to some or all usb ports when in a low-power state. the intel ? 6300ESB ich implements the optional port wake capability register in the ehc configuration space for this platform-specific information to be communicated to software.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 230 order number: 300641-004us 5.18.9 interaction with classic host controllers the enhanced host controller shares the four usb ports with two uhci host controllers in the intel ? 6300ESB ich. the usb uhci controller at d29:f0 shares ports 0 and 1 and the usb uhci controller at d29:f1 shares ports 2 and 3 with the ehci controller. there is very little interaction between the usb ehci and the usb uhci controllers other than the muxing control which is provided as part of the ehci controller. figure 22 depicts the usb port connections at a conceptual level. the dashed rectangle indicates all of the logic that is part of the enhanced host controller cluster. 5.18.9.1 port-routing logic integrated into the ehc functionality is port-routing logic, which performs the muxing between the usb uhci and usb ehci host controllers. the intel ? 6300ESB ich conceptually implements this logic as described in section 4.2 of the ehci specification. when a device is connected that is not capable of usb 2.0?s high-speed signaling protocol or when the ehci software drivers are not present as indicated by the configured flag, the usb uhci controller owns the port. owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. the host controller that is not the owner of the port internally sees a disconnected port. note that the port-routing logic is the only block of logic within the intel ? 6300ESB ich that observes the physical (real) connect/disconnect information. the port status logic inside each of the host controllers observes the electrical connect/disconnect information that is generated by the port-routing logic. only the differential signal pairs are muxed/demuxed between the usb uhci and usb ehci host controllers. the other usb functional signals are handled as follows: the overcurrent inputs (oc#[3:0]) are directly routed to both controllers. an overcurrent event is recorded in both controllers? status registers. the port-routing logic is implemented in the suspend power well so that re- enumeration and remapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. figure 22. intel ? 6300ESB ich-usb port connections port 0 port 1 port 2 port 3 uhci #2 (d29:f1) uhci #1 (d29:f0) ehci (d29:f7) debug port
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 231 5?intel ? 6300ESB ich the intel ? 6300ESB ich also allows the usb debug port traffic to be routed in and out of port #0. when in this mode, the enhanced host controller is the owner of port #0. 5.18.9.2 device connects section 4.2 of the ehci specification describes the details of handling device connects. there are four general scenarios that are summarized below. see section 11.2.2.8, ?offset caplength + 40 - 43h: configflag?configure flag register? . 1. configure flag = 0 and a usb full-speed/low-speed -only device is connected in this case, the usb uhci controller is the owner of the port both before and after the connect occurs. the ehc (except for the port-routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. 2. configure flag = 0 and an usb high-speed-capable device is connected in this case, the usb uhci controller is the owner of the port both before and after the connect occurs. the ehc (except for the port-routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. since the usb uhci controller does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. configure flag = 1 and a usb full-speed/low-speed-only device is connected in this case, the usb ehci controller is the owner of the port before the connect occurs. the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehc hardware has cleared (not set) the port enable bit in the ehc?s portsc register. the ehci driver then writes a 1 to the port owner bit in the same register, causing the usb uhci controller to see a connect event and the ehc to see an ?electrical? disconnect event. the uhci driver and hardware handle the connection and initialization process from that point on. the ehci driver and hardware handle the perceived disconnect. 4. configure flag = 1 and an usb high-speed-capable device is connected in this case, the usb ehci controller is the owner of the port before, and remains the owner after, the connect occurs. the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehc hardware has set the port enable bit in the ehc?s portsc register. the port is functional at this point. the usb uhci controller continues to see an unconnected port. 5.18.9.3 device disconnects section 4.2 of the ehci specification describes the details of handling device connects. there are three general scenarios that are summarized below. see section 11.2.2.8, ?offset caplength + 40 - 43h: configflag?configure flag register? . 1. configure flag = 0 and the device is disconnected. in this case, the usb uhci controller is the owner of the port both before and after the disconnect occurs. the ehc (except for the port-routing logic) never sees a device attached. the uhci driver handles disconnection process. 2. configure flag = 1 and a usb full-speed/low-speed-capable device is disconnected. in this case, the usb uhci controller is the owner of the port before the disconnect occurs. the disconnect is reported by the usb uhci controller
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 232 order number: 300641-004us and serviced by the associated uhci driver. the port-routing logic in the ehc cluster forces the port owner bit to 0, indicating that the ehc owns the unconnected port. 3. configure flag = 1 and a usb high-speed-capable device is disconnected. in this case, the usb ehci controller is the owner of the port before, and remains the owner after, the disconnect occurs. the ehci hardware and driver handle the disconnection process. the usb uhci controller never sees a device attached. 5.18.9.4 effect of resets on port-routing logic as mentioned above, the port routing logic is implemented in the suspend power well so that reenumeration and remapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. 5.18.10 usb 2.0 legacy keyboard operation the intel ? 6300ESB ich must support the possibility of a keyboard downstream from either a usb uhci or a usb ehci port. the description of the legacy keyboard support is unchanged from usb uhci (see section 5.17.9, ?usb legacy keyboard operation? ). the ehc provides the basic ability to generate smis on an interrupt event, along with more sophisticated control of the generation of smis. 5.18.11 usb 2.0 ehci based debug port the intel ? 6300ESB ich supports the elimination of the legacy com ports by providing the ability for new debugger software to interact with devices on a usb ehci port. high-level restrictions and features are: ? must be operational before usb ehci drivers are loaded. ? must work even when the port is disabled. ? must work even though non-configured port is default-routed to the classic controller. note that the debug port cannot be used to debug an issue that requires a classic usb device on port #0 using the uhci drivers. ? must allow normal system usb ehci traffic in a system that may only have one usb port. ? debug port device (dpd) must be high-speed capable and connect to a high-speed port on intel ? 6300ESB ich systems. ? debug port fifo must always make forward progress (a bad status on usb is simply presented back to software) ? the debug port fifo is only given one usb access per microframe table 113. effect of resets on port-routing logic reset event effect on configure flag effect on port owner bits suspend well reset cleared (0) set (1) core well reset no effect no effect d3-to-d0 reset no effect no effect hcreset cleared (0) set (1)
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 233 5?intel ? 6300ESB ich 5.18.11.1overview the debug port facilitates os and device driver debug. it allows the software to communicate with an external console using a usb ehci connection. since the interface to this link does not go through the normal usb ehci stack, it allows communication with the external console during cases where the os is not loaded, the usb ehci software is broken, or where the usb ehci software is being debugged. specific features of this implementation of a debug port are: ? only works with an external usb 2.0 debug device (console) ? implemented for a specific port on the host controller ? operational anytime the port is not suspended and the host controller is in d0 power state. ? capability is interrupted when port is driving usb reset 5.18.11.2theory of operation there are two operational modes for the usb debug port: 1. mode 1 is when the usb port is in a disabled state from the viewpoint of a standard host controller driver. in mode 1, the debug port controller is required to generate a ?keepalive? packets less than 2 ms apart to keep the attached debug device from suspending. the keepalive packet should be a standalone 32-bit sync field. 2. mode 2 is when the host controller is running (i.e., host controller?s run/stop# bit is 1). in mode 2, the normal transmission of sof packets will keep the debug device from suspending. detail for the registers mentioned in the next sections can be found in section 11.2.3, ?usb 2.0-based debug port register? and in section 11.2, ?memory-mapped i/o registers? . behavioral rules: 1. in both modes 1 and 2, the debug port controller must check for software requested debug transactions at least every 125 microseconds. 2. when the debug port is enabled by the debug driver, and the standard host controller driver resets the usb port, usb debug transactions are held off for the duration of the reset and until after the first sof is sent. 3. when the standard host controller driver suspends the usb port, then usb debug transactions are held off for the duration of the suspend/resume sequence and until after the first sof is sent. 4. the enabled_cnt bit in the debug register space is independent of the similar port control bit in the associated port status and control register. table 114 describes the debug port behavior related to the state of bits in the debug registers as well as bits in the associated port status and control register. table 114. usb debug port behavior (sheet 1 of 2) owner_cn t enabled_c nt port enable run / stop suspen d debug port behavior 0xxxx debug port is not being used. normal operation. 10xxx debug port is not being used. normal operation. 1100x debug port in mode 1. sync keep alives sent plus debug traffic.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 234 order number: 300641-004us 5.18.11.2.1out transactions an out transaction sends data to the debug device. it may occur only when the following are true: 1. the debug port is enabled. 2. the debug software sets the go_cnt bit. 3. the write_read#_cnt bit is set. the sequence of the transaction is listed below. 1. software sets the appropriate values in these bits: ? usb_address_cnf ?usb_endpoint_cnf ? data_buffer[63:0] ? token_pid_cnt[7:0] ? send_pid_cnt[15:8] ?data_len_cnt ? write_read#_cnt ( note: this will always be 1 for out transactions.) ?go_cnt ( note: this will always be 1 to initiate the transaction.) 1101x debug port in mode 2. sof (and only sof) is sent as keepalive. debug traffic is also sent. note that no other normal traffic is sent out this port, because the port is not enabled. 11100 illegal. host controller driver should never put controller into this state (enabled, not running and not suspended). 11101 port is suspended. no debug traffic sent. 11110 debug port in mode 2. debug traffic is interspersed with normal traffic. 11111 port is suspended. no debug traffic sent. table 114. usb debug port behavior (sheet 2 of 2) owner_cn t enabled_c nt port enable run / stop suspen d debug port behavior
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 235 5?intel ? 6300ESB ich 2. the debug port controller sends a token packet consisting of: a. sync b. token_pid_cnt field c. usb_address_cnt field d. usb_endpoint_cnt field e. 5-bit crc field 3. after sending the token packet, the debug port controller sends a data packet consisting of a. sync b. send_pid_cnt field c. the number of data bytes indicated in data_len_cnt from the data_buffer d. 16-bit crc note: a data_len_cnt value of zero is valid in which case no data bytes would be included in the packet. 4. after sending the data packet, the controller waits for a handshake response from the debug device. ? when a handshake is received, the debug port controller: a. places the received pid in the received_pid_sts field b. resets the error_good#_sts bit c. sets the done_sts bit ? when no handshake pid is received, the debug port controller: a. sets the exception_sts field to 001b b. sets the error_good#_sts bit c. sets the done_sts bit 5.18.11.2.2in transactions an in transaction receives data from the debug device. it may occur only when the following are true: 1. the debug port is enabled 2. the debug software sets the go_cnt bit 3. the write_read#_cnt bit is reset the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ? usb_address_cnf ?usb_endpoint_cnf ? token_pid_cnt[7:0] ?data_len_cnt ? write_read#_cnt ( note: this will always be 0 for in transactions.) ?go_cnt ( note: this will always be 1 to initiate the transaction.) 2. the debug port controller sends a token packet consisting of: a. sync b. token_pid_cnt field
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 236 order number: 300641-004us c. usb_address_cnt field d. usb_endpoint_cnt field e. 5-bit crc field. 3. after sending the token packet, the debug port controller waits for a response from the debug device. when a response is received: a. the received pid is placed into the received_pid_sts field b. any subsequent bytes are placed into the data_buffer c. the data_len_cnt field is updated to show the number of bytes that were received after the pid. 4. when valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: a. resets the error_good#_sts bit b. sets the done_sts bit 5. when valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: a. transmits an ack handshake packet b. resets the error_good#_sts bit c. sets the done_sts bit 6. when no valid packet is received, then the debug port controller: a. sets the exception_sts field to 001b b. sets the error_good#_sts bit c. sets the done_sts bit. 5.18.11.2.3 debug software enabling the debug port there are two mutually exclusive conditions that debug software must address as part of its startup processing: 1. the ehci has been initialized by system software 2. the ehci has not been initialized by system software debug software may determine the current ?initialized? state of the ehci by examining the configure flag in the ehci usb 2.0 command register. see section 11.2.2.8, ?offset caplength + 40 - 43h: configflag?configure flag register? for information regarding offset 40h, bit 0. when this flag is set, then system software has initialized the ehci. otherwise, the ehci should not be considered initialized. debug software will initialize the debug port registers depending on the state the ehci. however, before this may be accomplished, debug software must determine which root usb port is designated as the debug port. determining the debug port debug software may determine which usb root port has been designated as the debug port by examining bits 20:23 of the ehci host controller structural parameters register. see section 11.2.1.3, ?offset 04 - 07h: hcsparams?host controller structural parameters? for information regarding offset 04h. this 4-bit field represents the numeric value assigned to the debug port (i.e., 0000=port 0). debug software startup with non-initialized ehci
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 237 5?intel ? 6300ESB ich debug software may attempt to use the debug port after setting the owner_cnt bit in the control/status register, section 11.2.3.1, ?offset 00h: control/status register? , offset 00h, bit 30, and the current connect status bit in the appropriate (see determining the debug port) portsc register is set. see section 11.2.2.9, ?portsc- port n status and control? for information regarding bit 0. when the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. when a device is connected to the port, then debug software must reset/enable the port. debug software does this by setting and then clearing the port reset bit the portsc register. to ensure a successful reset, debug software should wait at least 50 ms before clearing the port reset bit. due to possible delays, this bit may not change to zero immediately; reset is complete when this bit reads as zero. software must not continue until this bit reads zero. when a high-speed device is attached, the ehci will automatically set the port enabled/disabled bit in the portsc register and the debug software may proceed. debug software should set the enabled_cnt bit in the debug port control/status register, and then reset (clear) the port enabled/disabled bit in the portsc register (so that the system host controller driver doesn't see an enabled port when it is first loaded). debug software startup with initialized ehci debug software may attempt to use the debug port when the current connect status bit in the appropriate (see determining the debug port) portsc register is set. when the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. when a device is connected, then debug software must set the owner_cnt bit and then the enabled_cnt bit in the debug port control/status register. see section 11.2.3.1, ?offset 00h: control/status register? for information regarding offset 00h, bits 30 and 28. determining debug peripheral presence after enabling the debug port functionality, debug software may determine when a debug peripheral is attached by attempting to send data to the debug peripheral. when all attempts result in an error (exception bits in the debug port control/status register indicates a transaction error), the attached device is not a debug peripheral. see section 11.2.3.1, ?offset 00h: control/status register? for information regarding offset 00h, bits [9:7]. when the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected. 5.19 smbus controller functional description (d31:f3) 5.19.1 overview the intel ? 6300ESB ich provides an smbus 2.0 compliant host controller as well as an smbus slave interface. the host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves). the intel ? 6300ESB ich is also capable of operating in a mode in which it may communicate with i 2 c compatible devices.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 238 order number: 300641-004us the intel ? 6300ESB ich may perform smbus messages with either packet error checking (pec) enabled or disabled. the actual pec calculation and checking is performed in software.the smbus host controller logic may automatically append the crc byte when configured to do so. the slave interface allows an external master to read from or write to the intel ? 6300ESB ich. write cycles may be used to cause certain events or pass messages, and the read cycles may be used to determine the state of various status bits. the intel ? 6300ESB ich?s internal host controller cannot access the intel ? 6300ESB ich?s internal slave interface. the intel ? 6300ESB ich smbus logic exists in device 31:function 3 configuration space, and consists of a transmit data path, and host controller. the transmit data path provides the data flow logic needed to implement the seven different smbus command protocols and is controlled by the host controller. the intel ? 6300ESB ich smbus controller logic is clocked by rtc clock. the smbus address resolution protocol (arp) is supported by using the existing host controller commands through software, except for the new host notify command (which is actually a received message). the programming model of the host controller is combined into two portions: a pci configuration portion, and a system i/o mapped portion. all static configuration, such as the i/o base address, is done through the pci configuration space. real-time programming of the host interface is done in system i/o space. 5.19.2 host controller the smbus host controller is used to send commands to other smbus slave devices. software sets up the host controller with an address, command, and, for writes, data and optional pec; and then tells the controller to start. when the controller has finished transmitting data on writes, or receiving data on reads, it will generate an smi# or interrupt, when enabled. the host controller supports seven command protocols of the smbus interface (see the smbus specification): quick command, send byte, receive byte, write byte/word, read byte/word, processcall, block read, block write and block write-block read process call. the smbus host controller requires that the various data and command fields be setup for the type of command to be sent. when software sets the start bit, the smbus host controller will perform the requested transaction, and interrupt the processor (or generate an smi#) when the transaction is completed. once a start command has been issued, the values of the ?active registers? (host control, host command, transmit slave address, data 0, data 1) should not be changed or read until the interrupt status bit (intr) has been set (indicating the completion of the command). any register values needed for computation purposes should be saved prior to issuing of a new command, as the smbus host controller will update all registers while completing the new command. using the smbus host controller to send commands to the intel ? 6300ESB ich's smbus slave port is supported. the intel ? 6300ESB ich supports slave functionality, including the host notify protocol, on the smlink pins when in tco compatible mode. therefore, in order to be fully compliant with the smbus 2.0 specification (which requires the host notify cycle), the smlink and smbus signals must be tied together externally. however, this requirement to tie both smlink and smbus signals externally is not needed in advanced tco mode as the slave functionality is available on the smbus pins.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 239 5?intel ? 6300ESB ich 5.19.2.1 command protocols in all of the following commands, the host status register (offset 00h) is used to determine the progress of the command. while the command is in operation, the host_busy bit is set. when the command completes successfully, the intr bit will be set in the host status register. when the device does not respond with an acknowledge, and the transaction times out, the dev_err bit is set. when software sets the kill bit in the host control register while the command is running, the transaction will stop and the failed bit will be set. when the kill bit is set, the intel ? 6300ESB ich will abort current transaction by asserting smbclk low for greater than the timeout period, assert a stop condition and then releases smbclk and smbdata. however, setting the kill bit does not affect smlink or tco transactions or causes intel ? 6300ESB ich to force a timeout when it is not performing a transaction. quick command when programmed for a quick command, the transmit slave address register is sent. the pec byte is never appended to the quick protocol. software should force the pec_en bit to ?0? when performing the quick command. software must force the i2c_en bit to 0 when running this command. the format of the protocol is shown in table 115 . send byte/receive byte for the send byte command, the transmit slave address and device command registers are sent for the receive byte command, the transmit slave address register is sent. the data received is stored in the data0 register. software must force the i2c_en bit to 0 when running this command. the receive byte is similar to a send byte, the only difference is the direction of data transfer. the format of the protocol is shown in table 116 and tab le 11 7 . table 115. quick protocol bit description 1 start condition 2?8 slave address - 7 bits 9 read / write direction 10 acknowledge from slave 11 stop table 116. send/receive byte protocol without pec send byte protocol receive byte protocol bit description bit description 1 start 1 start 2?8 slave address - 7 bits 2?8 slave address - 7 bits 9write 9 read 10 acknowledge from slave 10 acknowledge from slave 11?18 command code - 8 bits 11?18 data byte from slave 19 acknowledge from slave 19 not acknowledge 20 stop 20 stop
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 240 order number: 300641-004us write byte/word the first byte of a write byte/word access is the command code. the next 1 or 2 bytes are the data to be written. when programmed for a write byte/word command, the transmit slave address, device command, and data0 registers are sent. in addition, the data1 register is sent on a write word command. software must force the i2c_en bit to 0 when running this command. the format of the protocol is shown in table 118 and ta b le 11 9 . table 117. send/receive byte protocol with pec send byte protocol receive byte protocol bit description bit description 1 start 1 start 2?8 slave address - 7 bits 2?8 slave address - 7 bits 9write 9read 10 acknowledge from slave 10 acknowledge from slave 11?18 command code - 8 bits 11?18 data byte from slave 19 acknowledge from slave 19 acknowledge 20?27 pec 20?27 pec from slave 28 acknowledge from slave 28 not acknowledge 29 stop 29 stop table 118. write byte/word protocol without pec write byte protocol write word protocol bit description bit description 1 start 1 start 2?8 slave address - 7 bits 2?8 slave address - 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11?18 command code - 8 bits 11?18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20?27 data byte - 8 bits 20?27 data byte low - 8 bits 28 acknowledge from slave 28 acknowledge from slave 29 stop 29?36 data byte high - 8 bits 37 acknowledge from slave 38 stop table 119. write byte/word protocol with pec write byte protocol write word protocol bit description bit description 1 start 1 start 2?8 slave address - 7 bits 2?8 slave address - 7 bits 9 write 9 write
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 241 5?intel ? 6300ESB ich read byte/word reading data is slightly more complicated than writing data. first the intel ? 6300ESB ich must write a command to the slave device. then it must follow that command with a repeated start condition to denote a read from that device's address. the slave then returns 1 or 2 bytes of data. software must force the i2c_en bit to 0 when running this command. when programmed for the read byte/word command, the transmit slave address and device command registers are sent. data is received into the data0 on the read byte, and the data0 and data1 registers on the read word. the format of the protocol is shown in ta b l e 1 2 0 and table 121 . 10 acknowledge from slave 10 acknowledge from slave 11?18 command code - 8 bits 11?18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20?27 data byte - 8 bits 20?27 data byte low - 8 bits 28 acknowledge from slave 28 acknowledge from slave 29?36 pec 29?36 data byte high - 8 bits 37 acknowledge from slave 37 acknowledge from slave 38 stop 38?45 pec 46 acknowledge from slave 47 stop table 119. write byte/word protocol with pec write byte protocol write word protocol bit description bit description
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 242 order number: 300641-004us table 120. read byte/word protocol without pec read byte protocol read word protocol bit description bit description 1start 1start 2?8 slave address - 7 bits 2?8 slave address - 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11?18 command code - 8 bits 11?18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 repeated start 20 repeated start 21?27 slave address - 7 bits 21?27 slave address - 7 bits 28 read 28 read 29 acknowledge from slave 29 acknowledge from slave 30?37 data from slave - 8 bits 30?37 data byte low from slave - 8 bits 38 not acknowledge 38 acknowledge 39 stop 39?46 data byte high from slave - 8 bits 47 not acknowledge 48 stop table 121. read byte/word protocol with pec read byte protocol read word protocol bit description bit description 1 start 1 start 2?8 slave address - 7 bits 2?8 slave address - 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11?18 command code - 8 bits 11?18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 repeated start 20 repeated start 21?27 slave address - 7 bits 21?27 slave address - 7 bits 28 read 28 read 29 acknowledge from slave 29 acknowledge from slave 30?37 data from slave - 8 bits 30?37 data byte low from slave - 8 bits 38 acknowledge 38 acknowledge 39?46 pec from slave 39?46 data byte high from slave - 8 bits 47 not acknowledge 47 acknowledge 48 stop 48?55 pec from slave 56 not acknowledge 57 stop
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 243 5?intel ? 6300ESB ich process call the process call is so named because a command sends data and waits for the slave to return a value dependent on that data. the protocol is simply a write word followed by a read word, but without a second command or stop condition. when programmed for the process call command, the intel ? 6300ESB ich transmits the transmit slave address, host command, data0 and data1 registers. data received from the device is stored in the data0 and data1 registers. the process call command with i2c_en set and the pec_en bit set produces undefined results. software must force either i2c_en or pec_en to 0 when running this command. the format of the protocol is shown in table 122 and tab le 12 3 . note: for process call command, the value written into bit 0 of the transmit slave address register (smbus i/o register, offset 04h) needs to be 0. table 122. process call protocol without pec bit description 1start 2?8 slave address - 7 bits 9write 10 acknowledge from slave 11?18 command code - 8 bits 19 acknowledge from slave 20?27 data byte low - 8 bits 28 acknowledge from slave 29?36 data byte high - 8 bits 37 acknowledge from slave 38 repeated start 39?45 slave address - 7 bits 46 read 47 acknowledge from slave 48?55 data byte low from slave - 8 bits 56 acknowledge 57?64 data byte high from slave - 8 bits 65 not acknowledge 66 stop table 123. process call protocol with pec (sheet 1 of 2) bit description 1start 2?8 slave address - 7 bits 9write 10 acknowledge from slave 11?18 command code - 8 bits
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 244 order number: 300641-004us block read/write the intel ? 6300ESB ich contains a 32-byte buffer for read and write data which may be enabled by setting bit ?1? of the auxiliary control register at offset 0dh in i/o space, as opposed to a single byte of buffering. this 32-byte buffer is filled with write data before transmission, and filled with read data on reception. in the intel ? 6300ESB ich, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. this requires the intel ? 6300ESB ich to check the byte count field. currently, the byte count field is transmitted but ignored by the hardware as software will end the transfer after all bytes it cares about have been sent or received. for a block write software must either force the i2c_en bit or both the pec_en and aac bits to 0 when running this command. smbus mode: the block write begins with a slave address and a write condition. after the command code the intel ? 6300ESB ich issues a byte count describing how many more bytes will follow in the message. when a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. the byte count may not be 0. a block read or write is allowed to transfer a maximum of 32 data bytes. when programmed for a block write command, the transmit slave address, device command, and data0 (count) registers are sent. data is then sent from the block data byte register; the total data sent being the value stored in the data0 register. on block read commands, the first byte received is stored in the data0 register, and the remaining bytes are stored in the block data byte register. the format of the block read/write protocol is shown in table 124 and ta b le 1 25 . 19 acknowledge from slave 20?27 data byte low - 8 bits 28 acknowledge from slave 29?36 data byte high - 8 bits 37 acknowledge from slave 38 repeated start 39?45 slave address - 7 bits 46 read 47 acknowledge from slave 48?55 data byte low from slave - 8 bits 56 acknowledge 57?64 data byte high from slave - 8 bits 65 acknowledge 66?73 pec from slave 74 not acknowledge 75 stop table 123. process call protocol with pec (sheet 2 of 2) bit description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 245 5?intel ? 6300ESB ich i 2 c mode: for block write, when the i 2 c_en bit is set, the format of the command changes slightly. the intel ? 6300ESB ich w ill still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the data0 register. however, it will not send the contents of the data0 register as part of the message. l table 124. block read/write protocol without pec block write protocol block read protocol bit description bit description 1 start 1 start 2?8 slave address - 7 bits 2?8 slave address - 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11?18 command code - 8 bits 11?18 command code - 8 bits 19 acknowledge from slave 19 acknowledge from slave 20?27 byte count - 8 bits (skip this step when i 2 c_en bit set) 20 repeated start 28 acknowledge from slave (skip this step when i2c_en bit set) 21?27 slave address - 7 bits 29?36 data byte 1 - 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38?45 data byte 2 - 8 bits 30?37 byte count from slave - 8 bits 46 acknowledge from slave 38 acknowledge ... data bytes / slave acknowledges... 39?46 data byte 1 from slave - 8 bits ... data byte n - 8 bits 47 acknowledge ... acknowledge from slave 48?55 data byte 2 from slave - 8 bits ... stop 56 acknowledge ... data bytes from slave/ acknowledge ... data byte n from slave - 8 bits ... not acknowledge ... stop table 125. block read/write protocol with pec (sheet 1 of 2) block write protocol block read protocol bit description bit description 1 start 1 start 2?8 slave address - 7 bits 2?8 slave address - 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11?18 command code - 8 bits 11?18 command code - 8 bits
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 246 order number: 300641-004us i 2 c block read this command allows the intel ? 6300ESB ich to perform block reads to certain i 2 c devices, such as serial e 2 proms. the smbus block read supports the 7-bit addressing mode only. however, this does not allow access to devices using the i 2 c ?combined format? that has data bytes after the address. typically these data bytes correspond to an offset (address) within the serial memory chips. note: this command is supported independent of the setting of the i2c_en bit. the i 2 c read command with the pec_en bit set produces undefined results. software must force both the pec_en and aac bit to 0 when running this command. for i 2 c read command, the value written into bit 0 of the transmit slave address register (smbus i/o register, offset 04h) needs to be 0. to support these devices, the intel ? 6300ESB ich implements an i 2 c read command with the format: shown in ta b l e 1 2 6 . 19 acknowledge from slave 19 acknowledge from slave 20?27 byte count - 8 bits (skip this step when i 2 c_en bit set) 20 repeated start 28 acknowledge from slave (skip this step when i 2 c_en bit set) 21?27 slave address - 7 bits 29?36 data byte 1 - 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38?45 data byte 2 - 8 bits 30?37 byte count from slave - 8 bits 46 acknowledge from slave 38 acknowledge ... data bytes/slave acknowledges 39?46 data byte 1 from slave - 8 bits ... data byte n - 8 bits 47 acknowledge ... acknowledge from slave 48?55 data byte 2 from slave - 8 bits ... pec - 8 bits 56 acknowledge ... acknowledge from slave ... data bytes from slave/acknowledge ... stop ... data byte n from slave - 8 bits ... acknowledge ... pec from slave - 8 bits ... not acknowledge ... stop table 125. block read/write protocol with pec (sheet 2 of 2) block write protocol block read protocol bit description bit description table 126. i 2 c block read protocol (sheet 1 of 2) bit description 1start 2-8 slave address - 7 bits 9write
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 247 5?intel ? 6300ESB ich the intel ? 6300ESB ich will continue reading data from the peripheral until the nak is received. block write-block read process call the block write-block read process call is a two-part message. the call begins with a slave address and a write condition. after the command code the host issues a write byte count (m) that describes how many more bytes will be written in the first part of the message. if a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. the write byte count (m) cannot be zero. the second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a read bit. the next byte is the read byte count (n), which may differ from the write byte count (m). the read byte count (n) cannot be zero. the combined data payload must not exceed 32 bytes. the byte length restrictions of this process call are summarized as follows: ? m 1 byte ? n 1 byte ? m + n 32 bytes the read byte count does not include the pec byte. the pec is computed on the total message beginning with the first slave address and using the normal pec computational rules. it is highly recommended that a pec byte be used with the block write-block read process call. software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. note: there is no stop condition before the repeated start condition, and a nack signifies the end of the read transfer. note: e32b bit in the auxiliary control register must be set when using this protocol. 10 acknowledge from slave 11-18 send data1 register 19 acknowledge from slave 20 repeated start 20-27 slave address - 7 bits 28 read 29 acknowledge from slave 30-38 data byte 1 from slave - 8 bits 39 acknowledge 39-46 data byte 2 from slave - 8 bits 47 acknowledge ... data bytes from slave/ acknowledge ... data byte n from slave - 8 bits ... not acknowledge ... stop table 126. i 2 c block read protocol (sheet 2 of 2) bit description
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 248 order number: 300641-004us table 127. block write-block read process call protocol with/without pec bit description 1start 2-8 slave address - 7 bits 9write 10 acknowledge from slave 11-18 command code - 8 bits 19 acknowledge from slave 20-27 data byte count (m) - 8 bits 28 acknowledge from slave 29-36 data byte (1) - 8 bits 37 acknowledge from slave 38-45 data byte (2) - 8 bits 46 acknowledge from slave ?? data byte (m) - 8 bits acknowledge from slave repeated start slave address - 7 bits read acknowledge from slave data byte count (n) from slave ? 8 bits acknowledge from master data byte (1) from slave ? 8 bits acknowledge from master data byte (2) from slave ? 8 bits acknowledge from master ?? data byte count (n) from slave ? 8 bits acknowledge from master (skip if no pec) pec from slave (skip if no pec) not acknowledge stop
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 249 5?intel ? 6300ESB ich 5.19.2.2 i 2 c behavior when the i 2 c_en bit is set, the intel ? 6300ESB ich smbus logic will instead be set to communicate with i 2 c devices. this forces the following changes: 1. the process call command will skip the command code (and its associated acknowledge). 2. the block write command will skip sending the byte count (data0). in addition, the intel ? 6300ESB ich will support the new i 2 c read command. this is independent of the i 2 c_en bit. note: when operating in i 2 c mode the intel ? 6300ESB ich will not use the 32-byte buffer for block commands. 5.19.2.3 heartbeat for use with the external lan controller the heartbeat method allows the intel ? 6300ESB ich to send messages to an external lan controller when the processor is otherwise unable to do so. it uses the smlink i/f between the intel ? 6300ESB ich and the external lan controller. the actual heartbeat message is a block write. only eight bytes are sent. 5.19.3 bus arbitration several masters may attempt to get on the bus at the same time by driving the smbdata line low to signal a start condition. the intel ? 6300ESB ich must continuously monitor the smbdata line. when the intel ? 6300ESB ich is attempting to drive the bus to a ?1? by letting go of the smbdata line, and it samples smbdata low, then some other master is driving the bus and the intel ? 6300ESB ich must stop transferring data. when the intel ? 6300ESB ich sees that it has lost arbitration, the condition is called a collision. the intel ? 6300ESB ich w ill set the bus_err bit in the host status register, and when enabled, generate an interrupt or smi#. the processor is responsible for restarting the transaction. when the intel ? 6300ESB ich is a smbus master, it will drive the clock. when the intel ? 6300ESB ich is sending address or command as an smbus master, or data bytes as a master on writes, it will drive data relative to the clock it is also driving. it will not start toggling the clock until the start or stop condition meets proper setup and hold time. the intel ? 6300ESB ich will also ensure minimum time between smbus transactions as a master. note: the intel ? 6300ESB ich supports the same arbitration protocol for both the smbus and the system management (smlink) interfaces. 5.19.4 bus timing 5.19.4.1 clock stretching some devices may not be able to handle their clock toggling at the rate that the intel ? 6300ESB ich as an smbus master would like. they have the capability of stretching the low time of the clock. when the intel ? 6300ESB ich attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 250 order number: 300641-004us the intel ? 6300ESB ich must monitor the smbus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. while the bus is still low, the high time counter must not be enabled. similarly, the low period of the clock may be stretched by an smbus master when it is not ready to send or receive data. 5.19.4.2 bus time out (intel ? 6300ESB ich as smbus master) when there is an error in the transaction, such that an smbus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. the intel ? 6300ESB ich will discard the cycle, and set the dev_err bit. the time out minimum is 25 ms. the time-out counter inside the intel ? 6300ESB ich will start after the last bit of data is transferred by the intel ? 6300ESB ich and it is waiting for a response. the 25 ms will be a count of 800 rtc clocks. 5.19.5 interrupts/smi# the intel ? 6300ESB ich smbus controller uses pirqb# as its interrupt pin. however, the system may alternatively be set up to generate smi# instead of an interrupt, by setting the smbus_smi_en bit. table 129 and tab le 13 0 specify how the various enable bits in the smbus function control the generation of the interrupt, host and slave smi, and wake internal signals. the rows in the tables are additive, which means that when more than one row is true for a particular scenario then the results for all of the activated rows will occur. table 128. enable for smbalert# event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit 1) smbalert_dis (slave command i/ o register, offset 11h, bit 2) result smbalert# asserted low (always reported in host status register, bit 5) xx xwake generated x1 0 slave smi# generated (smbus_smi_sts) 10 0 interrupt generated table 129. enables for smbus slave write and smbus host events event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit1) event slave write to wake/ smi# command xx wake generated when asleep. slave smi# generated when awake (smbus_smi_sts). slave write to smlink_slave_smi command xx slave smi# generated when in the s0 state (smbus_smi_sts) any combination of host status register [4:1] asserted 0xnone 1 0 interrupt generated 11host smi# generated
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 251 5?intel ? 6300ESB ich 5.19.6 smbalert# smbalert# is multiplexed with gpio[11]. when enabled and the signal is asserted, the intel ? 6300ESB ich may generate an interrupt, an smi# or a wake event from s1 ? s4. note: any event on smbalert# (regardless whether it is programmed as a gpio or not), causes the event message to be sent in ?heartbeat mode.? 5.19.7 smbus crc generation and checking when the aac bit is set in the auxiliary control register, the intel ? 6300ESB ich will automatically calculate and drive crc at the end of the transmitted packet for write cycles, and will check the crc for read cycles. it will not transmit the contents of the pec register for crc. the pec bit must not be set in the host control register when this bit is set, or unspecified behavior will result. when the read cycle results in a crc error, the dev_err bit and the crce bit in the auxiliary status register at offset 0ch will be set. 5.19.8 smbus slave interface the intel ? 6300ESB ich?s smbus slave interface is accessed through the smlink[1:0] signals. the smbus slave logic will not generate or handle receiving the pec byte and will only act as a legacy alerting protocol (alert on lan*) device. the slave interface allows the intel ? 6300ESB ich to decode cycles, and allows an external microcontroller to perform specific actions. key features and capabilities include: ? supports decode of three types of messages: byte write, byte read, and host notify ? receive slave address register: this is the address that the intel ? 6300ESB ich decodes. a default value is provided so that the slave interface may be used without the processor having to program this register. ? receive slave data register in the smbus i/o space that includes the data written by the external microcontroller ? registers that the external microcontroller may read to get the state of the intel ? 6300ESB ich. see table 135 . ? status bits to indicate that the smlink/smbus slave logic caused an interrupt or smi# due to the reception of a message that matched the slave address. ? bit 0 of the slave status register for the host notify command. table 130. enables for the host notify command host_notify_intren (slave control i/o register, offset 11h, bit 0) smb_smi_en (host config register, d31:f3:off40h, bit 1) host_notify_wken (slave control i/o register, offset 11h, bit 1) result 0x0none xx1wake generated 1 0 x interrupt generated 11x slave smi# generated (smbus_smi_sts)
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 252 order number: 300641-004us ? bit 16 of the smi status register ( section 8.8.3.10, ?smi_sts?smi status register? ) for all others. note: the external microcontroller should not attempt to access the intel ? 6300ESB ich?s smbus slave logic until 1 second after both: rtest# is high and rsmrst# is high. when a master leaves the clock and data bits of the smlink interface at ?1? for 50 s or more in the middle of a cycle, the intel ? 6300ESB ich slave logic?s behavior is undefined. this is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. note: when an external microcontroller accesses the smbus slave interface over the smlink a translation in the address is needed to accommodate the least significant bit used for read/write control. for example, when the intel ? 6300ESB ich slave address (rcv_slva) is left at 44h (default), the external microcontroller would use an address of 88h/89h (write/read). 5.19.8.1 format of slave write cycle the external master performs byte write commands to the intel ? 6300ESB ich smbus slave i/f. the ?command? field (bits 11 - 18) indicate which register is being accessed. the data field (bits 20 - 27) indicates the value that should be written to that register. the write cycle format is shown in table 131 . table 132 has the values associated with the registers. table 131. slave write cycle format bits description driven by comment 1 start condition external microcontroller 2?8 slave address - 7 bits external microcontroller must match value in receive slave address register. 9write external microcontroller always 0 10 ack intel ? 6300ESB ich 11?18 command external microcontroller this field indicates which register will be accessed. see table 132 below for the register definitions 19 ack intel ? 6300ESB ich 20?27 register data external microcontroller see table 132 below for the register definitions 28 ack intel ? 6300ESB ich 29 stop external microcontroller
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 253 5?intel ? 6300ESB ich . table 132. slave write registers register function 0 command register. see ta b le 1 3 3 for legal values written to this register. 1?3 reserved 4 data message byte 0 5 data message byte 1 6?7 reserved 8 frequency straps will be written on bits 3:0. bits 7:4 should be 0, but will be ignored. 9-ffh reserved note: the external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. the intel ? 6300ESB ich will overwrite the old value with any new value received. a race condition is possible where the new value is being written to the register just at the time it is being read. intel ? 6300ESB ich will not attempt to cover this race condition (i.e. unpredictable results in this case). table 133. command types (sheet 1 of 2) command type description 0reserved 1 wake/smi#: wake system if it is not already awake. if system is already awake, then an smi# will be generated. note: the smb_wak_sts bit will be set by this command, even when the system is already awake. the smi handler should then clear this bit. 2 unconditional powerdown: this command sets the pwrbtnor_sts bit, and has the same effect as the powerbutton override occurring. 3 hard reset without cycling: the will cause a hard reset of the system (does not include cycling of the power supply). this is equivalent to a write to the cf9h register with bits 2:1 set to 1, but bit 3 set to 0. 4 hard reset system: the will cause a hard reset of the system (including cycling of the power supply). this is equivalent to a write to the cf9h register with bits 3:1 set to 1. 5 disable the tco messages. this command will disable the intel ? 6300ESB ich from sending heartbeat and event messages (as described in section 5.12.4, ?heartbeat and event reporting through smlink/smbus? ). once this command has been executed, heartbeat and event message reporting may only be re enabled by assertion and deassertion of the rsmrst# signal. 6 wd reload: reload watchdog timer.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 254 order number: 300641-004us 5.19.8.2 format of read command the external master performs byte read commands to the intel ? 6300ESB ich smbus slave i/f. the ?command? field (bits 11-18) indicate which register is being accessed. the data field (bits 30-37) contains the value that should be read from that register. table 134 shows the read cycle format. table 135 shows the register mapping for the data byte. 7 reserved 8 smlink_slv_smi. when intel ? 6300ESB ich detects this command type while in the s0 state, it sets the smlink_slv_smi_sts bit (see section 8.9.8, ?tco1_cnt?tco1 control register? ). this command should only be used when the system is in an s0 state. when the message is received during s1-s5 states, the intel ? 6300ESB ich acknowledges it, but the smlink_slv_smi_sts bit does not get set. note: it is possible that the system transitions out of the s0 state at the same time that the smlink_slv_smi command is received. in this case, the smlink_slv_smi_sts bit may get set but not serviced before the system goes to sleep. once the system returns to s0, the smi associated with this bit would then be generated. software must be able to handle this scenario. 9-ffh reserved table 133. command types (sheet 2 of 2) command type description table 134. read cycle format (sheet 1 of 2) bit description driven by: comment: 1start external microcontroller 2-8 slave address - 7 bits external microcontroller must match value in receive slave address register. 9write external microcontroller always zero. 10 ack intel ? 6300ESB ich 11-18 command code ? 8 bits external microcontroller indicates which register is being accessed. see table 135 . 19 ack intel ? 6300ESB ich 20 repeated start external microcontroller 21-27 slave address - 7 bits external microcontroller must match value in receive slave address register. 28 read external microcontroller always one. 29 ack intel ? 6300ESB ich
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 255 5?intel ? 6300ESB ich 30-37 data byte intel ? 6300ESB ich value depends on register being accessed. see table 135 . 38 not ack external microcontroller 39 stop external microcontroller table 135. data values for slave read registers (sheet 1 of 2) registe r bit s description 07:0reserved. 12:0 system power state 000 = s0 001 = s1 010 = reserved 011 = s3 100 = s4 101 = s5 110 = reserved 111 = reserved 17:3reserved 2 3:0 frequency strap register 27:4reserved 3 5:0 watchdog timer current value 37:6reserved 40 1 = the intruder detect (intrd_det) bit is set. this indicates that the system cover has probably been opened. 41 1 = bti temperature event occurred. this bit will be set when the intel ? 6300ESB ich?s thrm# input signal is active. need to take after polarity control. 4 2 boot-status. this bit will be 1 when the processor does not fetch the first instruction. 43 this bit will be set after the tco timer times out a second time (both timeout and second_to_sts bits set). 46:4reserved. 47 the bit will reflect the state of the gpi[11]/smbalert# signal, and will depend on the gp_inv[11] bit. it does not matter if the pin is configured as gpi[11] or smbalert#. note: when the gp_inv[11] bit is 1 then the value of register 4 bit 7 will equal the level of the gpi[11]/smbalert# pin (high = 1, low = 0). note: when the gp_inv[11] bit is 0 then the value of register 4 bit 7 will equal the inverse of the level of the gpi[11]/smbalert# pin (high = 1, low = 0). 5 0 unprogrammed fwh bit. this bit will be 1 to indicate that the first bios fetch returned ffh, which indicates th at the fwh is probably blank. 51 battery low status. ?1? when the batlow# pin is a ?0?. 52 cpu power failure status: ?1? when the cpupwr_flr bit in the gen_pmcon_2 register is set. table 134. read cycle format (sheet 2 of 2) bit description driven by: comment:
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 256 order number: 300641-004us warning: the external microcontroller is responsible to make sure that it does not read the contents of the various message registers until they have been written by the system processor. the intel ? 6300ESB ich will overwrite the old value with any new value received. a race condition is possible where the new value is being written to the register just at the time it is being read. the intel ? 6300ESB ich will not attempt to cover this race condition (i.e., unpredictable results). 5.19.8.2.1 behavioral notes according to smbus protocol, read and write messages always begin with a start bit - address - write bit sequence. when the intel ? 6300ESB ich detects that the address matches the value in the receive slave address register, it will assume that the protocol is always followed and ignore the write bit (bit 9) and signal an acknowledge during bit 10 (see table 131 and ta b l e 1 3 4 ). in other words, when a start - address - read occurs (which is illegal for smbus read or write protocol), and the address matches the intel ? 6300ESB ich?s slave address, the intel ? 6300ESB ich will st ill grab the cycle. also according to smbus protocol, a read cycle contains a repeated start - address - read sequence beginning at bit 20 (see ta b le 13 4 ). once again, when the address matches the intel ? 6300ESB ich?s receive slave address, it will assume that the protocol is followed, ignore bit 28, and proceed with the slave read cycle. note: an external microcontroller must not attempt to access the intel ? 6300ESB ich?s smbus slave logic until at least 1 second after both rtcrst# and rsmrst# are deasserted (high). 5.19.8.3 format of host notify command the intel ? 6300ESB ich tracks and responds to the standard host notify command as specified in the smbus 2.0 specification. the host address for this command is fixed to 0001000b. when the intel ? 6300ESB ich already has data for a previously-received host notify command which has not been serviced yet by the host software (as indicated by the host_notify_sts bit), it will nack following the host address byte of the protocol. this allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. note: host software must always clear the host_notify_sts bit after completing any necessary reads of the address and data registers. table 136 shows the host notify format. 57:3reserved 67:0 contents of the message 1 register. see section 8.9.10, ?tco_message1 and tco_message2 registers? . 77:0 contents of the message 2 register. see section 8.9.10, ?tco_message1 and tco_message2 registers? . 87:0 contents of the wdstatus register. see section 8.9.11, ?offset tcobase + oeh: tco_wdstatus?tco2 control register? . 9 ? ffh 7:0 reserved table 135. data values for slave read registers (sheet 2 of 2) registe r bit s description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 257 5?intel ? 6300ESB ich 5.20 ac?97 controller functional description (audio d31:f5, modem d31:f6) 5.20.1 overview note: all references to ac?97 in this document refer to the audio codec?97 component specification, version 2.2 . for further information on the operation of the ac-link protocol, please see the ac ?97 specification. the intel ? 6300ESB ich ac?97 controller features include: ? independent (fdx) channels for mono line in and out. ? supports 16 bit samples. ? multiple sample rates up to 48 khz ? supports dual codec implementations for audio in dock ? supports read/write access to all primary and secondary ac'97 registers ? supports low latency access to 16 gpio and wake up event status bits. note: the ac?97 rev 2.0 spec. defines the following features which are not supported by the intel ? 6300ESB ich: ? support for optional double rate sampling (n+1 sample for pcm l, r and c) ? support for 18 and 20 bit sample lengths ? handset channels (in and out) ? dual audio codec support table 136. host notify format bit description driven by: comment 1 start external master 2?8 smbus host address - 7 bits external master always 0001_000 9 write external master always zero. 10 ack (or nack) intel ? 6300ESB ich intel ? 6300ESB ich nacks when host_notify_sts is 1. 11?17 device address ? 7 bits external master indicates the address of the master; loaded into the notify device address register. 18 unused - always 0 external master 7-bit-only address; this bit is inserted to complete the byte 19 ack intel ? 6300ESB ich 20?27 data byte low - 8 bits external master loaded into the notify data low byte register. 28 ack intel ? 6300ESB ich 29?36 data byte high - 8 bits external master loaded into the notify data high byte register. 37 ack intel ? 6300ESB ich 38 stop external master
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 258 order number: 300641-004us table 137 shows a detailed list of features supported by the intel ? 6300ESB ich ac?97 digital controller. . table 137. features supported by intel ? 6300ESB ich (sheet 1 of 2) feature description system interface ? isochronous low latency bus master memory interface ? scatter/gather support for word-aligned buffers in memory (all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types are supported) ? data buffer size in system memory from 3 to 65535 samples per input ? data buffer size in system memory from 0 to 65535 samples per output ? independent pci audio and modem functions with configuration and io spaces ? ac?97 codec registers are shadowed in system memory through driver. ? ac?97 codec register accesses are serialized through semaphore bit in pci io space (new accesses are not allowed while a prior access is still in progress). power management ? power management through pci power management pci audio function ? read/write access to audio codec registers 00h-3ah and vendor registers 5ah-7eh ? 20-bit stereo pcm output, up to 48 khz (l,r, center, sub-woofer, l-rear and r-rear channels on slots 3,4,6,7,8,9,10,11) ? 16-bit stereo pcm input, up to 48 khz (l,r channels on slots 3,4) ? 16-bit mono mic in w/ or w/o mono mix, up to 48 khz (l,r channel, slots 3,4) (mono mix supports mono hardware aec reference for speakerphone) ? 16-bit mono pcm input, up to 48 khz from dedicated mic adc (slot 6) (supports speech recognition or stereo hardware aec ref for speakerphone) ? during cold reset ac_rst# is held low until after post and software deassertion of ac_rst# (supports passive pc_beep to speaker connection during post).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 259 5?intel ? 6300ESB ich note: throughout this document, references to d31:f5 indicate that the audio function exists in pci device 31, function 5. references to d31:f6 indicate that the modem function exists in pci device 31, function 6. note: throughout this document, references to tertiary, third, or triple codecs refer to the third codec in the system connected to the ac_sdin[2] pin. the ac?97 2.2 specification refers to non-primary codecs as multiple secondary codecs. to avoid confusion and excess verbiage this eds refers to it as the third or tertiary codec. pci modem function ? read/write access to modem codec registers 3ch-58h and vendor registers 5ah-7eh ? 16-bit mono modem line1 output and input, up to 48 khz (slot 5) ? low latency gpio[15:0] via hardwired update between slot 12 and pci io register. ? programmable pci interrupt on modem gpio input changes via slot 12 gpio_int ? sci event generation on ac_sdin[2:0] wake-up signals ac-link ? ac?97 2.0 compliant ac-link interface ? variable sample rate output support through ac?97 slotreq protocol (slots 3,4,5,6,7,8,9,10,11) ? variable sample rate input support through monitoring of slot valid tag bits (slots 3,4,5,6) ? 3.3 v digital operation meets ac?97 2.2 dc switching levels ? ac-link io driver capability meets ac?97 2.2 triple codec specifications ? codec register status reads must be returned with data in the next ac-link frame, per ac?97 2.2 spec. multiple codec ? triple codec addressing: all ac?97 audio codec register accesses are addressable to codec id 00 (primary), codec id 01 (secondary), or codec id 10 (tertiary). ? modem codec addressing: all ac?97 modem codec register accesses are addressable to codec id 00 (primary) or codec id 01 (secondary). ? triple codec receive capability through ac_sdin[2:0] pins (ac_sdin[2:0] frames are internally validated, synch?d, and or?d depending on the steer enable bit status in the sdm register) ? ac_sdin mapping to dma engine mapping capability allows for simultaneous input from three different audio codecs. notes: 1. audio codec ids are remappable and not limited to 00,01,10 2. modem codec ids are remappable and limited to 00,01 3. when using multiple codecs, the modem codec must be id 01. table 137. features supported by intel ? 6300ESB ich (sheet 2 of 2) feature description
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 260 order number: 300641-004us 5.20.1.1 pci power management this power management section applies for all ac?97 controller functions. after a power management event is detected, the ac?97 controller will wake the host system. the sections below describe these events and the ac?97 controller power states. device power states the ac?97 controller supports d0 and d3 pci power management states. notes regarding the intel ? 6300ESB ich ac?97 controller implementation of the device states: 1. the ac?97 controller hardware does not inherently consume any more power when it is in the d0 state than it does in d3 state. however, software may halt the dma engine prior to entering these low power states such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ac?97 controller features are enabled. 3. in d3 state, accesses to the ac?97 controller memory-mapped or i/o range will result in master abort. 4. in d3 state, the ac?97 controller interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power state field is written from d3 hot to d0, an internal reset is generated. 6. ac?97 sts bit will be set only when the audio or modem resume events were detected and their respective pme enable bits were set. 7. gpio status change interrupt no longer has a direct path to ac?97 sts bit. this will cause a wake up event only when the modem controller was in d3. 8. resume events on ac_sdin[2:0] will cause resume interrupt status bits to be set only if their respective controllers are not in d3. 9. edge detect logic will prevent the interrupts from being asserted in case ac?97 controller is switched from d3 to d0 after a wake event. 10. once the interrupt status bits are set, they will cause pirqb# if their respective enable bits were set. one of the audio or the modem drivers will handle the interrupt. 5.20.2 ac-link overview figure 23. intel ? 6300ESB ich based ac?97 controller connection to companion codec(s) audio in (record) audio out (playback) modem handset mic. pc
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 261 5?intel ? 6300ESB ich the intel ? 6300ESB ich is an ac?97 2.0 compliant controller that communicates with companion codecs through a digital serial link called the ac-link. all digital audio/ modem streams and command/status information is communicated over the ac-link. the ac-link is a bi-directional, serial pcm digital stream. it handles multiple input and output data streams, as well as control register accesses, employing a time division multiplexed (tdm) scheme. the ac-link architecture provides for data transfer through individual frames transmitted in a serial fashion. each frame is divided into 12 outgoing and 12 incoming data streams, or slots. the architecture of the intel ? 6300ESB ich ac-link allows a maximum of three codecs to be connected. figure 24 shows a three codec topology of the ac-link for the intel ? 6300ESB ich. the ac'97 modem controller is a separate pci function. however, the ac'97 modem controller is implemented in the same logical unit as the ac'97 audio functions. there are registers declared in the audio function which contain modem information - these registers are also visible in the modem io space, but are implemented as a single register. the ac-link consists of a five signal interface between the controller and codec. table 138 indicates the ac-link signal pins on the intel ? 6300ESB ich and their associated power wells. figure 24. ac?97 2.2 controller-codec connection
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 262 order number: 300641-004us intel ? 6300ESB ich core well outputs may be used as strapping options for the intel ? 6300ESB ich, sampled during system reset. these signals may have weak pullups/ pulldowns on them, however this will not interfere with link operation. intel ? 6300ESB ich inputs integrate weak pulldowns to prevent floating traces when a secondary and/ or tertiary codec is not attached. when the shut off bit in the control register is set, all buffers will be turned off and the pins will be held in a steady state, based on these pullups/pulldowns. bit_clk is fixed at 12.288 mhz and is sourced by the primary codec. it provides the necessary clocking to support the twelve 20-bit time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data samples each serial bit on the falling edge of bit_clk. when bit_clk makes no transitions for four consecutive pci clocks, the intel ? 6300ESB ich assumes the primary codec is not present or not working. it sets bit 28 of the global status register (i/o offset 30h). all accesses to codec registers with this bit set will return data of ffh to prevent system hangs. synchronization of all ac-link data transactions is signaled by the ac?97 controller through the ac_sync signal, as shown in figure 25 . the primary codec drives the serial bit clock onto the ac-link, which the ac?97 controller then qualifies with the ac_sync signal to construct data frames. ac_sync, fixed at 48 khz, is derived by dividing down bit_clk. ac_sync remains high for a total duration of 16 bit_clks at the beginning of each frame. the portion of the frame where ac_sync is high is defined as the tag phase. the remainder of the frame where ac_sync is low is defined as the data phase. each data bit is sampled on the falling edge of bit_clk. the intel ? 6300ESB ich has three ac_sdin pins allowing a single, dual, or triple codec configuration. when multiple codecs are connected, the primary, secondary, and tertiary codecs may be connected to any ac_sdin line. the intel ? 6300ESB ich does table 138. ac?97 signals signal name type power well description ac_reset# output resume master hardware reset ac_sync output core 48 khz fixed rate sample sync ac_bit_clk input core 12.288 mhz serial data clock ac_sdout output core serial output data ac_sdin 0 input resume serial input data ac_sdin 1 input resume serial input data ac_sdin 2 input resume serial input data note: power well voltage levels are 3.3 v. figure 25. ac-link protocol sync bit_clk sdin slot(1) time slot "valid" bits 20.8us (48 khz) slot 1 slot 2 0 19 0 19 0 19 0 slot 3 slot 12 81.4 ns 12.288 mhz slot(2) "0" "0" "0" slot(12) ("1" = time slot contains valid pcm data) 19 codec ready end of previous audio frame tag phase data phase
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 263 5?intel ? 6300ESB ich not distinguish between codecs on its ac_sdin[2:0] pins, however the registers do distinguish between ac_sdin[0], ac_sdin[1], and ac_sdin[2] for wake events, etc. when using a modem codec it is recommended to connect it to ac_sdin[1]. see your platform design guide for a matrix of valid codec configurations. the intel ? 6300ESB ich does not support optional test modes as outlined in the ac?97 specification. 5.20.2.1 ac-link output frame (sdout) a new output frame begins with a low to high transition of ac_sync. ac_sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the codec samples the assertion of ac_sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new frame. on the next rising edge of bit_clk, the intel ? 6300ESB ich transitions sdout into the first bit position of slot 0, or the valid frame bit. each new bit position is presented to the ac- link on a rising edge of bit_clk, and subsequently sampled by the codec on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. the output frame data phase corresponds to the multiplexed bundles of all digital output data targeting codec dac inputs and control registers. each output frame supports up to twelve outgoing data time slots. the intel ? 6300ESB ich generates 16 or 20 bits and stuffs remaining bits with zeros. the output data stream is sent with the most significant bit first, and all invalid slots are stuffed with zeros. when mono audio sample streams are output from the intel ? 6300ESB ich, software must ensure both left and right sample stream time slots are filled with the same data. 5.20.2.2 output slot 0: tag phase slot 0 is considered the tag phase. the tag phase is a special 16 bit time slot wherein each bit conveys a valid tag for its corresponding time slot within the current frame. a one in a given bit position of slot 0 indicates that the corresponding time slot within the current frame has been assigned to a data stream and contains valid data. when a slot is tagged invalid with a zero in the corresponding bit position of slot 0, the intel ? 6300ESB ich stuffs the corresponding slot with zeros during that slot?s active time. within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of the entire frame. when the valid frame bit is set to one, this indicates that the current frame contains at least one slot with valid data. when there is no transaction in progress, the intel ? 6300ESB ich w ill deassert the frame valid bit. note that after a write to slot 12, that slot will always stay valid, and therefore the frame valid bit will remain set. the next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time slots contain valid data. bits [1:0] of slot 0 are used as codec id bits to distinguish between separate codecs on the link. using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted across the link at its fixed 48 khz frame rate. the codec may control the output sample rate of the intel ? 6300ESB ich using the slotreq bits as described in the ac?97 specification.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 264 order number: 300641-004us 5.20.2.3 output slot 1: command address port the command port is used to control features and monitor status of ac?97 functions including, but not limited to, mixer settings and power management. the control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid. output frame slot 1 communicates control register address, and write/read command information. in the case of the multiple codec implementation, accesses to the codecs are differentiated by the driver using address offsets 00h ? 7fh for the primary codec, address offsets 80h ? feh for the secondary codec, and address offsets 100h ? 17fh for the tertiary codec. the differentiation on the link, however, is done through the codec id bits. 5.20.2.4 output slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle as indicated in slot 1, bit 19. when the current command port operation is a read, the entire slot time stuffed with zeros by the intel ? 6300ESB ich. bits [19:4] contain the write data. bits [3:0] are reserved and are stuffed with zeros. 5.20.2.5 output slot 3: pcm playback left channel output frame slot 3 is the composite digital audio left playback stream. typically this slot is composed of standard pcm (.wav) output samples digitally mixed by the host processor. the intel ? 6300ESB ich transmits sample streams of 16 bits or 20 bits and stuffs remaining bits with zeros. data in output slots 3 and 4 from the intel ? 6300ESB ich should be duplicated by software when there is only a single channel out. 5.20.2.6 output slot 4: pcm playback right channel output frame slot 4 is the composite digital audio right playback stream. typically this slot is composed of standard pcm (.wav) output samples digitally mixed by the host processor. the intel ? 6300ESB ich transmits sample streams of 16 or 20 bits and stuffs remaining bits with zeros. data in output slots 3 and 4 from the intel ? 6300ESB ich should be duplicated by software when there is only a single channel out. 5.20.2.7 output slot 5: modem codec output frame slot 5 contains modem dac data. the modem dac output supports 16-bit resolution. at boot time, when the modem codec is supported, the ac?97 controller driver determines the dac resolution. during normal runtime operation the intel ? 6300ESB ich stuffs trailing bit positions within this time slot with zeros.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 265 5?intel ? 6300ESB ich 5.20.2.8 output slot 6: pcm playback center front channel when set up for 6-channel mode, this slot is used for the front center channel. the format is the same as slots 3 and 4. when not set up for 6-channel mode, this channel will always be stuffed with zeros by intel ? 6300ESB ich. 5.20.2.9 output slots 7-8: pcm playback left and right rear channels when set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear left and right channels. the format for these two channels are the same as slots 3 and 4. 5.20.2.10output slot 9: playback sub woofer channel when set for 6-channel mode, this slot is used for the sub woofer. the format is the same as slot three. when not set up for 6-channel mode, this channel will always be stuffed with zeros by intel ? 6300ESB ich. 5.20.2.11output slots 10-11: reserved output frame slots 10-11 are reserved and are always stuffed with 0s by the intel ? 6300ESB ich ac?97 controller. 5.20.2.12output slot 12: i/o control sixteen bits of daa and gpio control (output) and status (input) have been directly assigned to bits on slot 12 in order to minimize latency of access to changing conditions. the value of the bits in this slot are the values written to the gpio control register at offset 54h and d4h (in the case of a secondary codec) in the modem codec i/o space. the following rules govern the usage of slot 12. 1. slot 12 is marked invalid by default on coming out of ac-link reset, and will remain invalid until a register write to 54h/d4h. 2. a write to offset 54h/d4h in codec i/o space will cause the write data to be transmitted on slot 12 in the next frame, with slot 12 marked valid, and the address/data information to also be transmitted on slots 1 and 2. 3. after the first write to offset 54h/d4h, slot 12 remains valid for all following frames. the data transmitted on slot 12 is the data last written to offset 54h/d4h. any subsequent write to the register will cause the new data to be sent out on the next frame. 4. slot 12 will get invalidated after the following events: ? pci reset, ac'97 cold reset, warm reset, and hence a wake from s3, s4, or s5. ? slot 12 will remain invalid until the next write to offset 54h/d4h. 5.20.2.13ac-link input frame (sdin) there are three ac_sdin lines on the intel ? 6300ESB ich for use with up to three codecs. each ac_sdin pin may have a codec attached. the input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac?97 controller. as in the case for the output frame, each ac-link input frame consists of twelve time slots.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 266 order number: 300641-004us a new audio input frame begins with a low to high transition of ac_sync. ac_sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the receiver samples the assertion of ac_sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_clk, the codec transitions ac_sdin into the first bit position of slot 0 (codec ready bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the intel ? 6300ESB ich on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. sdin data stream must follow the ac?97 specification and be msb justified with all non- valid bit positions (for assigned and/or unassigned time slots) stuffed with zeros. ac_sdin data is sampled by the intel ? 6300ESB ich on the falling edge of bit_clk.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 267 5?intel ? 6300ESB ich 5.20.2.14input slot 0: tag phase input slot 0 consists of a codec ready bit (bit 15), and slot valid bits for each subsequent slot in the frame (bits [14:3]). the codec ready bit within slot 0 (bit 15) indicates whether the codec on the ac-link is ready for register access (digital domain). when the codec ready bit in slot 0 is a zero, the codec is not ready for register access. when the ac-link codec ready bit is a 1, it indicates that the ac-link and codec control and status registers are in a fully operational state. the codec ready bits are visible through the global status register of the intel ? 6300ESB ich. software must further probe the powerdown control/status register in the codec to determine exactly which subsections, when any, are ready. bits [14:3] in slot 0 indicate which slots of the input stream to the intel ? 6300ESB ich contain valid data, just as in the output frame. the remaining bits in this slot are stuffed with zeros. 5.20.2.15input slot 1: status address port/slot request bits the status port is used to monitor status of codec functions including, but not limited to, mixer settings and power management. slot 1 must echo the control register index, for historical reference, for the data to be returned in slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in slot 0. for variable sample rate output, the codec examines its sample rate control registers, the state of its fifos, and the incoming sdout tag bits at the beginning of each audio output frame to determine which slotreq bits to set active (low). slotreq bits asserted during the current audio input frame signal which output slots require data from the controller in the next audio output frame. for fixed 48 khz operation the slotreq bits are always set active (low) and a sample is transferred each frame. for variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. table 139. input slot 1 bit definitions bit description 19 reserved (set to zero) 18:1 2 control register index (stuffed with zeros when tagged as invalid) 11 slot 3 request: pcm left channel (1) 10 slot 4 request: pcm right channel (1) 9 slot 5 request: modem line 1 [8:2 } slot 6-12 request: not implemented 1:0 reserved (stuffed with zeros) note: slot 3 request and slot 4 request bits must be the same value, i.e. set or cleared in tandem. this is also true for the slot 7 and slot 8 request bits, as well as the slot 6 and slot 9 request bits.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 268 order number: 300641-004us as shown in table 139 , slot 1 delivers codec control register read address and multiple sample rate slot request flags for all output slots of the controller. when a slot request bit is set by the codec, the controller will return data in that slot in the next output frame. slot request bits for slots 3 and 4 are always set or cleared in tandem, i.e. both are set or cleared. when set, the input slot 1 tag bit only pertains to status address port data from a previous read. slotreq bits are always valid independent of the slot 1 tag bit. 5.20.2.16input slot 2: status data port the status data port receives 16-bit control register read data. bit [19:4]: control register read data bit [3:0]: reserved. 5.20.2.17input slot 3: pcm record left channel input slot 3 is the left channel input of the codec. the intel ? 6300ESB ich supports 16-bit sample resolution. samples transmitted to the intel ? 6300ESB ich must be in left/right channel order. 5.20.2.18input slot 4: pcm record right channel input slot 4 is the right channel input of the codec. the intel ? 6300ESB ich supports 16-bit sample resolution. samples transmitted to the intel ? 6300ESB ich must be in left/right channel order. 5.20.2.19input slot 5: modem line input slot 5 contains msb justified modem data. the intel ? 6300ESB ich supports 16- bit sample resolution. 5.20.2.20input slot 6: optional dedicated microphone record data input slot 6 is a third pcm system input channel available for dedicated use by a microphone. this input channel supplements a true stereo output which enables more precise echo cancellation algorithm for speakerphone applications. the intel ? 6300ESB ich supports 16-bit resolution for slot 6 input. 5.20.2.21input slots 7-11: reserved input frame slots 7-11 are reserved for future use and should be stuffed with zeros by the codec, per the ac?97 specification. 5.20.2.22input slot 12: i/o status the status of the gpios configured as inputs are to be returned on this slot in every frame. the data returned on the latest frame is accessible to software by reading the register at offset 54h/d4h in the codec i/o space. only the 16 msbs are used to return gpi status. in order for gpi events to cause an interrupt, both the 'sticky' and 'interrupt' bits must be set for that particular gpio pin in regs 50h and 52h. therefore, the interrupt will be signalled until it has been cleared by the controller, which may be much longer than one frame.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 269 5?intel ? 6300ESB ich reads from 54h/d4h will not be transmitted across the link in slot 1 and 2. the data from the most recent slot 12 is returned on reads from offset 54h/d4h. 5.20.2.23register access in the intel ? 6300ESB ich implementation of the ac-link, up to three codecs may be connected to the sdout pin. the following mechanism is used to address the primary, secondary, and tertiary codecs individually. the primary device uses bit 19 of slot 1 as the direction bit to specify read or write. bits [18:12] of slot 1 are used for the register index. for i/o writes to the primary codec, the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in ta b le 1 40 . slot 1 is used to transmit the register address, and slot 2 is used to transmit data. for i/o reads to the primary codec, only slot 1 should be valid since only an address is transmitted. for i/o reads only slot 1 valid bit is set, while for i/o writes both slots 1 and 2 valid bits are set. the secondary and tertiary codec registers are accessed using slots 1 and 2 as described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec id bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non zero value. this allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and bits [1:0] of slot 0 to determine when the access is directed to the secondary or tertiary codec. when the register access is targeted to the secondary or tertiary codec, slot 1 and 2 will contain the address and data for the register access. since slots 1 and 2 are marked invalid, the primary codec will ignore these accesses. when accessing the codec registers, only one i/o cycle may be pending across the ac- link at any time. the intel ? 6300ESB ich implements write posting on i/o writes across the ac-link (i.e., writes across the link are indicated as complete before they are actually sent across the link). in order to prevent a second i/o write from occurring before the first one is complete, software must monitor the cas bit in the codec access semaphore register which indicates that a codec access is pending. once the cas bit is cleared, then another codec access (read or write) may go through. the exception to this being reads to offset 54h/d4h/154h (slot 12) which are returned immediately with the most recently received slot 12 data. writes to offset 54h, d4h, and 154h (primary, secondary and tertiary codecs), get transmitted across the ac-link in slots 1 and 2 as a normal register access. slot 12 is also updated immediately to reflect the data being written. the controller will not issue back to back reads. it must get a response to the first read before issuing a second. in addition, codec reads and writes are only executed once across the link, and are not repeated. table 140. output tag slot 0 bit primary access example secondary access example description 15 1 1 frame valid 14 1 0 slot 1 valid, command address bit (primary codec only) 13 1 0 slot 2 valid, command data bit (primary codec only) 12: 3 x x slot 3-12 valid 2 0 0 reserved 1:0 00 01 codec id (00 reserved for primary; 01 indicate secondary; 10 indicate tertiary).
5? intel ? 6300ESB ich intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 270 5.20.3 ac-link low power mode the ac-link signals may be placed in a low-power mode. when the ac?97 powerdown register (26h), is programmed to the appropriate value, both bit_clk and ac_sdin will be brought to, and held at a logic low voltage level. bit_clk and ac_sdin transition low immediately, within the maximum specified time, after a write to the powerdown register (26h) with pr4 enabled. when the ac?97 controller driver is at the point where it is ready to program the ac-link into its low- power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. at this point in time it is assumed that all sources of audio input have been neutralized. the ac?97 controller also drives ac_sync, and sdout low after programming ac?97 to this low power, halted mode. once the codec has been instructed to halt bit_clk, a special wake up protocol must be used to bring the ac-link to the active mode since normal output and input frames cannot be communicated in the absence of bit_clk. once in a low-power mode, the intel ? 6300ESB ich provides three methods for waking up the ac-link; external wake event, cold reset and warm reset. note: before entering any low-power mode where the link interface to the codec is expected to be powered down while the rest of the system is awake, the software must set the ?shut off? bit in the control register to ensure that the intel ? 6300ESB ich controller does not drive the output pins of the link. 5.20.3.1 external wake event codecs may signal the controller to wake the ac-link, and wake the system using ac_sdin. figure 26. ac-link powerdown timing sd o u t tag sync bit_clk write to 0x20 data pr4 slot 12 prev. frame tag slot 12 prev. frame sd in note: bit _clk not to scale
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 271 5?intel ? 6300ESB ich the minimum ac_sdin wake up pulse width is 1 us. the rising edge of sdata_in (sdata_in(0) or sdata)in(1) for split partitioned implementation) causes the audio controller to sequence through its ac-link ?warm reset? and signal pme# to the system?s acpi controller. the primary codec must wait to sample ac_sync high and low before restarting bit_clk as diagrammed in figure 6-24. the codec that signaled the wake event must keep its ac_sdin high until it has sampled ac_sync having gone high, and then low. the ac-link protocol provides for a cold reset and a warm reset. the type of reset used depends on the system?s current power down state. unless a cold or register reset (a write to the reset register in the codec) is performed, wherein the ac?97 codec registers are initialized to their default values, registers are required to keep state during all power down modes. once powered down, activation of the ac-link through re-assertion of the ac_sync signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. when ac-link powers up, it indicates readiness via the codec ready bit. 5.20.4 ac?97 cold reset a cold reset is achieved by asserting ac_rst# for 1 us. by driving ac_rst# low, bit_clk, and sdout will be activated and all codec registers will be initialized to their default power on reset values. ac_rst# is an asynchronous ac?97 input to the codec. 5.20.5 ac?97 warm reset a warm reset will re-activate the ac-link without altering the current codec register values. a warm reset is signaled by driving ac_sync high for a minimum of 1us in the absence of bit_clk. within normal frames, ac_sync is a synchronous ac?97 input to the codec. however, in the absence of bit_clk, ac_sync is treated as an asynchronous input to the codec used in the generation of a warm reset. the codec must not respond with the activation of bit_clk until ac_sync has been sampled low again by the codec. this will prevent the false detection of a new frame. figure 27. sdin wake signaling sdout tag sync bit_clk write to 0x20 data pr4 slot 12 prev. frame tag slot 12 prev. frame sdin tag slot 1 slot 2 power down frame wake event sleep state new audio frame tag slot 1 slot 2
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 272 order number: 300641-004us note: on receipt of wake up signalling from the codec, the digital controller will issue an interrupt when enabled. software will then have to issue a warm or cold reset to the codec by setting the appropriate bit in the global control register.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 273 5?intel ? 6300ESB ich 5.20.6 system reset table 141 indicates the states of the link during various system reset and sleep conditions. the transition of ac_rst# to the deasserted state will only occur under driver control. in the s1 sleep state, the state of the ac_rst# signal is controlled by the ac?97 cold reset# bit (bit 1) in the global control register. ac_rst# will be asserted (low) by the intel ? 6300ESB ich under the following conditions: ? rsmrst# (system reset, including the reset of the resume well and pxpcirst#) ? mechanical power up (causes pxpcirst#) ? write to cf9h hard reset (causes pxpcirst#) ? transition to s3/s4/s5 sleep states (causes pxpcirst#) ? write to ac?97 cold reset# bit in the global control register. hardware will never deassert ac_rst# (i.e., never deasserts the cold reset# bit) automatically. only software may deassert the cold reset# bit, and hence the ac_rst# signal. this bit, while it resides in the core well, will remain cleared upon return from s3/s4/s5 sleep states. the ac_rst# pin will remain actively driven from the resume well as indicated. 5.20.7 hardware assist to determine ac_sdin used per codec software first performs a read to one of the audio codecs. the read request goes out on ac_sdout. since under our micro-architecture only one read may be performed at a time on the link, eventually the read data will come back on one of the ac_sdin[2:0] lines. table 141. ac-link state during pxpcirst# signal power plane i/o during pxpcirst#/ after pxpcirst#/ s1 s3 s4/s5 ac_rst# resume 3 outpu t low low cold reset bit (hub interface) low low ac_sdout core 1 outpu t low running low low low ac_sync core outpu t low running low low low bit_clk core input driven by codec running low 2 , 4 low 2 , 4 low 2 , 4 ac_sdin[2:0] resume input driven by codec running low 2 , 4 low 2 , 4 low 2 , 4 notes: 1. intel ? 6300ESB ich core well outputs are used as strapping options for the intel ? 6300ESB ich, sampled during system reset. these signals may have weak pullups/pulldowns on them. the intel ? 6300ESB ich outputs will be driven to the appropriate level prior to ac_rst# being deasserted, preventing a codec from entering test mode. straps are tied to the core well to prevent leakage during a suspend state. 2. the pull-down resistors on these signals are only enabled when the ac-link shut off bit in the ac?97 global control register is set to 1. all other times, the pull-down resistor is disabled. 3. ac_rst# will be held low during s3-s5. it cannot be programmed high during a suspend state. 4. bit_clk and ac_sdin[2:0] are driven low by the codecs during normal states. when the codec is powered during suspend states, it will hold these signals low. however, when the codec is not present, or not powered in suspend, external pull-down resistors are required.
intel ? 6300ESB ich?5 intel ? 6300ESB i/o controller hub ds november 2007 274 order number: 300641-004us the codec will do this by indicating that status data is valid in its tag, then echo the read address in slot 1 followed by the read data in slot 2. the new function of the intel ? 6300ESB ich hardware is to notice which ac_sdin line contains the read return data, and to set new bits in the new register indicating which ac_sdin line the register read data returned on. when it returned on ac_sdin0, bits [1:0] contain the value ?00?. when it returned on ac_sdin1, the bits contain the value ?01?, etc. intel ? 6300ESB ich hardware may set these bits every time register read data is returned from a function 5 read. no special command is necessary to cause the bits to be set. the new driver/bios software will read the bits from this register when it cares to, and may ignore it otherwise. when software is attempting to establish the codec-to- ac_sdin mapping, it will single feed the read request and not pipeline to ensure it gets the right mapping, hardware cannot ensure the serialization of the access. 5.20.8 software mapping of ac_sdin to dma engine once software has performed the register read to determine codec-to-ac_sdin mapping, it will then either set bits [5:4] or [7:6] in the sdata_in map register to map this codec to the dma engine. after it maps the audio codecs, it will set the ?se? (steer enable) bit, which now lets the hardware know to no longer or the ac_sdin lines, and to use the mappings in the register to steer the appropriate ac_sdin line to the correct dma engines.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 275 6?intel ? 6300ESB ich register and memory mapping 6 the intel ? 6300ESB ich contains registers that are located in the processor?s i/o space, memory space and sets of pci configuration registers that are located in pci configuration space. this chapter details the intel ? 6300ESB ich i/o and memory maps. register access is also described. register-level address maps and individual register bit descriptions are provided in the following chapters. the following notations are used in the chapters that follow. ro read only: writes to this register location generally have no effect. however, in some cases, two separate registers are located at the same location where a read will access one register and a write will access the other register. see the i/o and memory map tables for details. wo write only: reads to this register location generally have no effect. however, in some cases, two separate registers are located at the same location where a read will access one register and a write will access the other register. see the i/o and memory map tables for details. r/w read/write: a register with this attribute may be read and written. r/wc read/write clear: a register bit with this attribute may be read and written. however, writing a 1 will clear (sets to zero) the corresponding bit, and writing a 0 will have no effect. default when coming out of reset, the registers are set to predetermined default states. it is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the intel ? 6300ESB ich registers accordingly. 6.1 pci devices and functions the intel ? 6300ESB ich incorporates multiple pci functions as shown in table 142 . these functions are divided into four pci devices. the first is the hub interface link-to- pci bridge, d: 30 f:0. the second device, d31:f1, contains most of the standard pci functions present in most ichs, as well as some new related intel ? 6300ESB ich features; sata and smbus controller. the third device, d29 fx, is the usb host controller device which includes new features specific to the intel ? 6300ESB ich; watchdog timer and an additional ioxapic. the fourth pci device, d28:f0, is also a new intel ? 6300ESB ich feature; a hub interface-to-pci-x bridge. when a particular system does not want to support any one of device 31?s, 29?s or 28?s functions, they may individually be disabled. when a function is disabled, it does not appear at all to the software. a disabled function will not respond to any register reads or writes.
intel ? 6300ESB ich?6 intel ? 6300ESB i/o controller hub ds november 2007 276 order number: 300641-004us table 142. pci devices and functions bus:device:function function description bus 0: device 30: function 0 hub interface to pci bridge bus 0: device 31: function 0 pci to lpc bridge bus 0: device 31: function 1 ide controller bus 0: device 31: function 2 sata controller bus 0: device 31: function 3 smbus controller bus 0: device 31: function 5 ac?97 audio controller bus 0: device 31: function 6 ac?97 modem controller bus 0: device 29: function 0 usb controller #1 bus 0: device 29: function 1 usb controller #2 bus 0: device 29: function 4 new: watchdog timer bus 0: device 29: function 5 new: ioxapic bus 0: device 29: function 7 usb 2.0 controller bus 0: device 28: function 0 new: hub interface to pci-x bridge note: the pci to lpc bridge contains registers that control lpc, power management, system management, gpio, cpu interface, rtc, interrupts, timers, dma.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 277 6?intel ? 6300ESB ich 6.2 pci configuration map each pci function on the intel ? 6300ESB ich has a set of pci configuration registers. the register map tables for each function are included at the beginning of each respective chapter. configuration space registers are accessed through configuration cycles on the pci bus by the host bridge using configuration mechanism #1 detailed in the pci local bus specification, revision 2.2. some pci registers contain ?reserved? bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, write operation for the configuration address register (0xcf8h). figure 28. intel ? 6300ESB ich device diagram hublink bus 0 ac?97 modem bus0:dev31:f6 ac?97 audio bus0:dev31:f5 ide bus0:dev31:f1 usb2 host bus0:dev29:f7 physical and logical connection logical connection only physical connection only usb classic host bus0:dev29:f0,1 hublink to pci bridge bus 0 ? dev30:f0 legacy pci bus smbus cntrl bus0:dev31:f3 pci - lpc bridge bus0:dev31:f0 lpc bus hublink to pci - x bridge bus 0 ? dev28:f0 pci - x bu s watch dog timer bus0:dev29:f4 sata bus0:dev31:f2 ioxapic bus0:dev29:f5
intel ? 6300ESB ich?6 intel ? 6300ESB i/o controller hub ds november 2007 278 order number: 300641-004us in addition to reserved bits within a register, the configuration space contains reserved locations. software should not write to reserved pci configuration locations in the device-specific region (above address offset 3fh). 6.3 i/o map the i/o map is divided into fixed and variable address ranges. fixed ranges cannot be moved, but in some cases may be disabled. variable ranges may be moved and may also be disabled. 6.3.1 fixed i/o address ranges table 143 shows the fixed i/o decode ranges from the cpu perspective. note that for each i/o range, there may be separate behavior for reads and writes. the hub interface cycles that go to target ranges that are marked as ?reserved? will not be decoded by the intel ? 6300ESB ich, and will be passed to pci. when a pci master targets one of the fixed i/o target ranges, it will be positively decoded by the intel ? 6300ESB ich in medium speed. note: unclaimed pci cycles will be subtractively decoded and forwarded to the lpc. address ranges that are not listed or marked ?reserved? are not decoded by the intel ? 6300ESB ich (unless assigned to one of the variable ranges). table 143. fixed i/o ranges decoded by intel ? 6300ESB i/o controller hub (sheet 1 of 3) i/o address read target write target internal unit 00h - 08h dma controller dma controller dma 09h - 0eh reserved dma controller dma 0fh dma controller dma controller dma 10h - 18h dma controller dma controller dma 19h - 1eh reserved dma controller dma 1fh dma controller dma controller dma 20h - 21h interrupt controller interrupt controller interrupt 24h - 25h interrupt controller interrupt controller interrupt 28h - 29h interrupt controller interrupt controller interrupt 2ch - 2dh interrupt controller interrupt controller interrupt 2e-2f lpc sio lpc sio forwarded to lpc 30h - 31h interrupt controller interrupt controller interrupt 34h - 35h interrupt controller interrupt controller interrupt notes: 1. only when the port 61 alias enable bit (device 31:function 0, offset d0, bit 4) bit is set. otherwise, the target is pci. 2. only when ide standard i/o space is enabled for secondary channel and the ide controller is in legacy mode. otherwise, the target is pci. 3. only when ide standard i/o space is enabled for primary channel and the ide controller is in legacy mode. otherwise, the target is pci. 4. should forward read cycles to this address to lpc variable i/o decode ranges.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 279 6?intel ? 6300ESB ich 38h - 39h interrupt controller interrupt controller interrupt 3ch - 3dh interrupt controller interrupt controller interrupt 40h - 42h timer/counter timer/counter pit (8254) 43h reserved timer/counter pit 4e-4f lpc siu lpc siu forwarded to lpc 50h - 52h timer/counter timer/counter pit 53h reserved timer/counter pit 60h microcontroller/emulation microcontroller/emulation forwarded to lpc 61h nmi controller nmi controller cpu i/f 62h microcontroller microcontroller forwarded to lpc 63h nmi controller nmi controller cpu i/f 64h microcontroller/emulation microcontroller/emulation forwarded to lpc 65h nmi controller nmi controller cpu i/f 66h microcontroller microcontroller forwarded to lpc 67h nmi controller nmi controller cpu i/f 70h reserved nmi and rtc controller rtc 71h rtc controller rtc controller rtc 72h rtc controller nmi and rtc controller rtc 73h rtc controller rtc controller rtc 74h rtc controller nmi and rtc controller rtc 75h rtc controller rtc controller rtc 76h rtc controller nmi and rtc controller rtc 77h rtc controller rtc controller rtc 80h dma controller dma controller and lpc or pci dma 81h - 83h dma controller dma controller dma 84h - 86h dma controller dma controller and lpc or pci dma 87h dma controller dma controller dma 88h dma controller dma controller and lpc or pci dma 89h - 8bh dma controller dma controller dma table 143. fixed i/o ranges decoded by intel ? 6300ESB i/o controller hub (sheet 2 of 3) i/o address read target write target internal unit notes: 1. only when the port 61 alias enable bit (device 31:function 0, offset d0, bit 4) bit is set. otherwise, the target is pci. 2. only when ide standard i/o space is enabled for secondary channel and the ide controller is in legacy mode. otherwise, the target is pci. 3. only when ide standard i/o space is enabled for primary channel and the ide controller is in legacy mode. otherwise, the target is pci. 4. should forward read cycles to this address to lpc variable i/o decode ranges.
intel ? 6300ESB ich?6 intel ? 6300ESB i/o controller hub ds november 2007 280 order number: 300641-004us 8ch - 8eh dma controller dma controller and lpc or pci dma 08fh dma controller dma controller dma 90h - 91h dma controller dma controller dma 92h reset generator reset generator cpu i/f 93h - 9fh dma controller dma controller dma a0h - a1h interrupt controller interrupt controller interrupt a4h - a5h interrupt controller interrupt controller interrupt a8h - a9h interrupt controller interrupt controller interrupt ach - adh interrupt controller interrupt controller interrupt b0h - b1h interrupt controller interrupt controller interrupt b2h - b3h power management power management power management b4h - b5h interrupt controller interrupt controller interrupt b8h - b9h interrupt controller interrupt controller interrupt bch - bdh interrupt controller interrupt controller interrupt c0h - d1h dma controller dma controller dma d2h - ddh reserved dma controller dma deh - dfh dma controller dma controller dma f0h see note 2 ferr#/ignne# / interrupt controller cpu i/f 170h - 177h ide controller 2 ide controller 2 forwarded to ide 1f0h - 1f7h ide controller 1 ide controller 1 forwarded to ide 376h ide controller 2 ide controller 2 forwarded to ide 200-207h gameport low gameport low forwarded to lpc 208-20fh gameport high gameport high forwarded to lpc 376h ide controller 2 ide controller 2 forwarded to ide 388-38bh adlib adlib forwarded to lpc 3f6h ide controller 1 ide controller 1 forwarded ide 4d0h - 4d1h interrupt controller interrupt controller interrupt cf9h reset generator reset generator cpu i/f table 143. fixed i/o ranges decoded by intel ? 6300ESB i/o controller hub (sheet 3 of 3) i/o address read target write target internal unit notes: 1. only when the port 61 alias enable bit (device 31:function 0, offset d0, bit 4) bit is set. otherwise, the target is pci. 2. only when ide standard i/o space is enabled for secondary channel and the ide controller is in legacy mode. otherwise, the target is pci. 3. only when ide standard i/o space is enabled for primary channel and the ide controller is in legacy mode. otherwise, the target is pci. 4. should forward read cycles to this address to lpc variable i/o decode ranges.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 281 6?intel ? 6300ESB ich 6.3.2 variable i/o decode ranges table 144 shows the variable i/o decode ranges. they are set using base address registers (bars) or other configuration bits in the various pci configuration spaces. the pnp software (pci or acpi) may use their configuration mechanisms to set and adjust these values. when a cycle is detected on the hub interface, the intel ? 6300ESB ich will positively decode the cycle. when the response is on the behalf of an lpc device, the intel ? 6300ESB ich will forward the cycle to the lpc. refer to table 144 for a complete list of all variable i/o registers. warning: the variable i/o ranges should not be set to conflict with the fixed i/o ranges. there may be unpredictable results when the configuration software allows conflicts to occur. the intel ? 6300ESB ich does not perform any checks for conflicts. table 144. variable i/o decode ranges range name mappable size (bytes) target acpi anywhere in 64k i/o space 64 power management ide bus master anywhere in 64k i/o space 16 ide unit usb #1 anywhere in 64k i/o space 32 usb 1.0 host controller 1 smbus anywhere in 64k i/o space 32 smb unit ac?97 audio mixer anywhere in 64k i/o space 256 ac?97 unit ac?97 bus master anywhere in 64k i/o space 64 ac?97 unit ac?97 modem mixer anywhere in 64k i/o space 256 ac?97 unit tco 96 bytes above acpi base 32 tco unit gpio anywhere in 64k i/o space 64 gpio unit parallel port 3 ranges in 64k i/o space 8 lpc peripheral serial port 1 8 ranges in 64k i/o space 8 lpc peripheral serial port 2 8 ranges in 64k i/o space 8 lpc peripheral floppy disk controller 2 ranges in 64k i/o space 8 lpc peripheral midi 4 ranges in 64k i/o space 2 lpc peripheral mss 4 ranges in 64k i/o space 8 lpc peripheral soundblaster 2 ranges in 64k i/o space 32 lpc peripheral
intel ? 6300ESB ich?6 intel ? 6300ESB i/o controller hub ds november 2007 282 order number: 300641-004us usb #2 anywhere in 64k i/o space 32 usb 1.0 host controller 2 lpc generic 1 anywhere in 64k i/o space 128 lpc peripheral lpc generic 2 anywhere in 64k i/o space 16 lpc peripheral monitors 4:7 anywhere in 64k i/o space 16 lpc peripheral or trap on pci native ide primary command anywhere in 64k i/o space 8ide unit native ide primary control anywhere in 64k i/o space 4ide unit native ide secondary command anywhere in 64k i/o space 8ide unit native ide secondary control anywhere in 64k i/o space 4ide unit table 144. variable i/o decode ranges
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 283 6?intel ? 6300ESB ich 6.4 memory map table 145 shows, from the cpu perspective, the memory ranges that the intel ? 6300ESB ich will decode. cycles that arrive from the hub interface that are not directed to any of the internal memory targets that decode directly from hub interface will be driven out on pci. the intel ? 6300ESB ich may then claim the cycle for it to be forwarded to lpc or claimed by the internal i/o apic or subtractive decode the cycle. when subtractive decode is enabled, the subtractive decoded cycle may be forwarded to the lpc i/f or to the fwh. pci cycles generated by an external pci master will be positively decoded unless it falls in the pci-pci bridge forwarding range (those addresses are reserved for pci peer-to- peer traffic). when the cycle is not in the i/o apic or fwh/lpc ranges, it will be forwarded up the hub interface to the host controller. pci masters cannot access the memory ranges for functions that decode directly from hub interface. table 145. memory decode ranges from cpu perspective (sheet 1 of 2) memory range target dependency/comments 0000 0000 - 000d ffff 0010 0000 - tom (top of memory) main memory tom registers in host controller 000e 0000 - 000f ffff fwh bit 7 in fwh decode enable register is set fec0 0000 - fec0 0043 i/o apic inside the intel ? 6300ESB ich downstream memory writes to fec0 0020 are also decoded by d29:f5 apic to support eoi. fec1 0000 - fec1 0043 i/o apic (d29:f5) d29:f5 apic also supports fec00000-fec00043 range of message signaled interrupts from the pci-x interface (see note 1) ffc0 0000 - ffc7 ffff ff80 0000 - ff87 ffff fwh bit 0 in fwh decode enable register ffc8 0000 - ffcf ffff ff88 0000 - ff8f ffff fwh bit 1 in fwh decode enable register ffd0 0000 - ffd7 ffff ff90 0000 - ff97 ffff fwh bit 2 in fwh decode enable register is set ffd8 0000 - ffdf ffff ff98 0000 - ff9f ffff fwh bit 3 in fwh decode enable register is set ffe0 000 - ffe7 ffff ffa0 0000 - ffa7 ffff fwh bit 4 in fwh decode enable register is set ffe8 0000 - ffef ffff ffa8 0000 - ffaf ffff fwh bit 5 in fwh decode enable register is set fff0 0000 - fff7 ffff ffb0 0000 - ffb7 ffff fwh bit 6 in fwh decode enable register is set. fff8 0000 - ffff ffff ffb8 0000 - ffbf ffff fwh always enabled. the top two 64k-byte blocks of this range may be swapped, as described in section 6.4.1, ?boot- block update scheme? . notes: 1. these ranges are decoded directly from hub interface. the memory cycles will not be seen on pci. 2. software must not attempt locks to memory mapped i/o ranges for usb ehci, high performance event timers, and ide expansion. when attempted, the lock is not honored, which means potential deadlock conditions may occur.
intel ? 6300ESB ich?6 intel ? 6300ESB i/o controller hub ds november 2007 284 order number: 300641-004us ff70 0000 - ff7f ffff ff30 0000 - ff3f ffff fwh bit 3 in fwh decode enable 2 register is set ff60 0000 - ff6f ffff ff20 0000 - ff2f ffff fwh bit 2 in fwh decode enable 2 register is set ff50 0000 - ff5f ffff ff10 0000 - ff1f ffff fwh bit 1 in fwh decode enable 2 register is set ff40 0000 - ff4f ffff ff00 0000 - ff0f ffff fwh bit 0 in fwh decode enable 2 register is set 1 kbyte anywhere in 4 gbyte range ide expansion 2 enable through standard pci mechanism and bits in ide i/o configuration register (device 31, function 1) 512b anywhere in 4 gbyte range ac?97 host controller (mixer) 1 enable via standard pci mechanism (device 31, function 5) 256b anywhere in 4 gbyte range ac?97 host controller (bus master) 1 enable via standard pci mechanism (device 31, function 5) 1 kbyte anywhere in 4 gbyte range usb ehci controller 1 , 2 enable through standard pci mechanism (device 29, function 7). fed0 x000 - fed0 x3ff multimedia timers 1 , 2 bios determines the ?fixed? location which is one of four, 1-kbyte ranges where x (in the first column) is 0h, 1h, 2h, or 3h. 1 kbyte anywhere in 4 gbyte range sata 1 enable via standard pci mechanism (device 31, function 2) 1 kbyte anywhere in 4 gbyte range wdt enable via standard pci mechanism (device 29, function 4) 1 mbyte to 4 gbyte anywhere in 4 gbyte range pci-x 1 enable via standard pci mechanism (device 28, function 0) all other pci none/ if the address is below 16m, is not in one of the above bios ranges, and positive decode is disabled; then the cycle will be forwarded to lpc as a standard lpc memory cycle. if the address is above 16m, if the cycle is not claimed by a device on pci and neither by the intel ? 6300ESB ich, then the cycle will master- abort on pci table 145. memory decode ranges from cpu perspective (sheet 2 of 2) memory range target dependency/comments notes: 1. these ranges are decoded directly from hub interface. the memory cycles will not be seen on pci. 2. software must not attempt locks to memory mapped i/o ranges for usb ehci, high performance event timers, and ide expansion. when attempted, the lock is not honored, which means potential deadlock conditions may occur.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 285 6?intel ? 6300ESB ich 6.4.1 boot-block update scheme the intel ? 6300ESB ich supports a ?top-block swap? mode that has the intel ? 6300ESB ich swap the top block in the fwh (the boot block) with another location. this allows for safe update of the boot block (even if a power failure occurs). when the ?top_swap? enable bit is set, the intel ? 6300ESB ich w ill invert a16 for cycles targeting fwh bios space. when this bit is zero, the intel ? 6300ESB ich will not invert a16. this bit is automatically set to zero by rtcrst#, but not by pxpcirst#. the scheme is based on the concept that the top block is reserved as the ?boot? block, and the block immediately below the top block is reserved for doing boot-block updates. the algorithm is: 1. software copies the top block to the block immediately below the top. 2. software checks that the copied block is correct. this could be done by performing a checksum calculation. 3. software sets the top_swap bit. this will invert a16 for cycles going to the fwh. processor access to ffff_0000 through ffff_ffff will be directed to fffe_0000 through fffe_ffff in the fwh, and processor accesses to fffe_0000 through fffe_ffff will be directed to ffff_0000 through ffff_ffff. 4. software erases the top block. 5. software writes the new top block. 6. software checks the new top block. 7. software clears the top_swap bit. if a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. this is because the top_swap bit is backed in the rtc well. note: the top-block swap mode may be forced by an external strapping option (see section 3.21.1, ?functional straps? ). when top-block swap mode is forced in this manner, the top_swap bit cannot be cleared by software. a re-boot with the strap removed will be required to exit a forced top-block swap mode. note: top-block swap mode only affects accesses to the fwh bios space, not feature space. note: the top-block swap mode has no effect on accesses below fffe_0000.
intel ? 6300ESB ich?6 intel ? 6300ESB i/o controller hub ds november 2007 286 order number: 300641-004us
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 287 7?intel ? 6300ESB ich hub interface to pci bridge registers (d30:f0) 7 the hub interface to pci bridge resides in pci device 30, function 0 on bus #0. this portion of the intel ? 6300ESB ich implements the buffering and control logic between pci and the hub interface. the arbitration for the pci bus is handled by this pci device. the pci decoder in this device must decode the ranges for the hub interface. all register contents will be lost when core well power is removed. 7.1 pci configuration registers (d30:f0) note: registers that are not shown should be treated as reserved (see section 6.2, ?pci configuration map? for details). . table 146. pci configuration registers (d30:f0) (sheet 1 of 2) offset mnemonic register name/function default type 00-01h vid vendor id 8086h ro 02-03h did device id 244eh ro 04-05h cmd pci device command register 0001h r/w 06-07h pd_sts pci device status register 0080h r/w 08h rid revision id see note: ro 0ah scc sub class code 04h ro 0bh bcc base class code 06h ro 0dh pmlt primary master latency timer 00h ro 0eh headtyp header type 01h ro 18h pbus_num primary bus number 00h ro 19h sbus_num secondary bus number 00h r/w 1ah sub_bus_num subordinate bus number 00h r/w 1bh smlt secondary master latency timer 00h r/w 1ch iobase io base register f0h r/w 1dh iolim io limit register 00h r/w 1e-1fh secsts secondary status register 0280h r/w 20-21h membase memory base fff0h r/w 22-23h memlim memory limit 0000h r/w 24-25h pref_mem_base prefetchable memory base 0000h ro 26-27h pref_mem_mlt prefetchable memory limit 0000h ro 30-31h iobase_hi i/o base upper 16 bits 0000h ro 32-33h iolimit_hi i/o limit upper 16 bits 0000h ro note: refer to the intel ? 6300ESB ich specification update for the most up-to-date value of the revision id register.
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 288 order number: 300641-004us 7.1.1 offset 00 - 01h: vid?vendor id register (hub- pci?d30:f0) 7.1.2 offset 02 - 03h: did?device id register (hub- pci?d30:f0) 3ch int_line interrupt line 00h ro 3e-3fh bridge_cnt bridge control 0000h r/w 40-43h hi1_cmd hub interface 1 command control 20202802h r/w 44-45h device_hide secondary pci device hiding register 00 r/w 50-51h cnf intel ? 6300ESB ich configuration register 1400h r/w 70h mtt multi-transaction timer 20h r/w 82h pci_mast_sts pci master status 00h r/w 90h err_cmd error command register 00h r/w 92h err_sts error status register 00h r/w f8h manid manufacturer?s id 0f66h ro table 147. offset 00 - 01h: vid?vendor id register (hub-pci?d30:f0) bits name description access 15:0 vendor identification number this is a 16-bit value assigned to intel. intel vid = 8086h. ro table 148. offset 02 - 03h: did?device id register (hub-pci?d30:f0) bits name description access 15:0 device identification number this is a 16-bit value assigned to the intel ? 6300ESB ich hub interface to pci bridge. ro table 146. pci configuration registers (d30:f0) (sheet 2 of 2) offset mnemonic register name/function default type note: refer to the intel ? 6300ESB ich specification update for the most up-to-date value of the revision id register. device: 30 function: 0 offset: 00-01h attribute: read-only default value: 8086h size: 16-bit device: 30 function: 0 offset: 02-03h attribute: read-only default value: 244eh size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 289 7?intel ? 6300ESB ich 7.1.3 offset 04 - 05h: cmd?command register (hub- pci?d30:f0) table 149. offset 04 - 05h: cmd?command register (hub-pci?d30:f0) bits name description access 15:1 0 reserved reserved. 9 fast back to back enable (fbe) hardwired to?0?. the intel ? 6300ESB ich does not support this capability. ro 8 serr# enable (serr_en) 0 = disable. 1 = enable the intel ? 6300ESB ich to generate an nmi (or smi# if nmi routed to smi#) when the d30:f0 sse bit (offset 06h, bit 14) is set. r/w 7 wait cycle control hardwired to ?0? ro 6 parity error response 0 = the intel ? 6300ESB ich will ignore parity errors on the hub interface. 1 = the intel ? 6300ESB ich is allowed to report parity errors detected on the hub interface. note: the hub interface parity unsupported bit (d30:f0:40h:bit20) must be cleared for the per bit to have any effect. r/w 5 vga palette snoop hardwired to ?0?. ro 4 memory write and invalidate enable (mwe) hardwired to ?0?. ro 3 special cycle enable (sce) hardwired to ?0? by p2p bridge spec. ro 2 bus master enable (bme) 0 = disable 1 = allows the hub interface-to-pci bridge to accept cycles from pci to run on the hub interface. note: this bit does not affect the cf8h and cfch i/o accesses. note: cycles that generated from the intel ? 6300ESB ich?s device 31 functionality are not blocked by clearing this bit. r/w 1 memory space enable (mse) the intel ? 6300ESB ich provides this bit as read/writable for software only. however, the intel ? 6300ESB ich ignores the programming of this bit, and runs hub interface memory cycles to pci. r/w 0 i/o space enable (ioe) the intel ? 6300ESB ich provides this bit as read/writable for software only. however, the intel ? 6300ESB ich ignores the programming of this bit and runs hub interface i/o cycles to pci that are not intended for usb, ide, or ac?97. r/w device: 30 function: 0 offset: 04-05h attribute: read/write default value: 0001h size: 16-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 290 order number: 300641-004us 7.1.4 offset 06 - 07h: pd_sts?primary device status register (hub-pci?d30:f0) note: for the writable bits in this register, writing a 1 will clear the bit. writing a 0 to the bit will have no effect. table 150. offset 06 - 07h: pd_sts?primary device status register (hub-pci? d30:f0) bits name description access 15 detected parity error (dpe) 0 = software clears this bit by writing a ?1? to the bit location. 1 = indicates that the intel ? 6300ESB ich detected a parity error on the hub interface and the hub interface parity unsupported bit is cleared (d30:f0:40h:bit20). this bit gets set even when the parity error response bit (offset 04, bit 6) is not set. r/wc 14 signaled system error (sse) 0 = software clears this bit by writing a ?1? to the bit location. 1 = an address, or command parity error, or special cycles data parity error has been detected on the pci bus, and the parity error response bit (d30:f0, offset 04h, bit 6) is set. when this bit is set because of parity error and the d30:f0 serr_en bit (offset 04h, bit 8) is also set, the intel ? 6300ESB ich will generate an nmi (or smi# if nmi routed to smi#). r/wc 13 received master abort (rma) 0 = software clears this bit by writing a ?1? to the bit location. 1 = the intel ? 6300ESB ich received a master abort from the hub interface device. r/wc 12 received target abort (rta) 0 = software clears this bit by writing a ?1? to the bit location. 1 = the intel ? 6300ESB ich received a target abort from the hub interface device. the setting of this bit can be enabled to cause an internal serr#. r/wc 11 signaled target abort (sta) 0 = software clears this bit by writing a ?1? to the bit location. 1 = the intel ? 6300ESB ich signals a target abort condition on the hub interface. r/wc 10:9 devsel# timing status 00h = fast timing. this register applies to the hub interface. ro 8 master data parity error detected (mdpd) since this register applies to the hub interface, the intel ? 6300ESB ich must interpret this bi t differently than it is in the pci spec. 0 = software clears this bit by writing a ?1? to the bit location. 1 = the intel ? 6300ESB ich detects a parity error on the hub interface and the parity error response bit in the command register (offset 04h, bit 6) is set. r/wc 7 fast back to back hardwired to ?1?. ro 6 user definable features (udf) hardwired to ?0?. ro 5 66 mhz capable hardwired to ?0?. ro 4:0 reserved reserved. device: 30 function: 0 offset: 06-07h attribute: read/write clear default value: 0080h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 291 7?intel ? 6300ESB ich 7.1.5 offset 08h: rid?revision identification register (hub-pci?d30:f0) 7.1.6 offset 0ah: scc?sub-class code register (hub- pci?d30:f0) 7.1.7 offset 0bh: bcc?base-class code register (hub-pci?d30:f0) table 151. offset 08h: rid?revision identification register (hub-pci?d30:f0) bits name description access 7:0 revision id value 8-bit value that indicates the revision number for the intel ? 6300ESB ich ich hub interface-to-pci bridge. ro table 152. offset 0ah: scc?sub-class code register (hub-pci?d30:f0) bits name description access 7:0 sub-class code 8-bit value that indicates the category of bridge for the intel ? 6300ESB ich hub interface to pci bridge. the code is 04h indicating a pci-to-pci bridge. ro table 153. offset 0bh: bcc?base-class code register (hub-pci?d30:f0) bits name description access 7:0 base class code 8-bit value that indicates the type of device for the intel ? 6300ESB ich hub interface to pci bridge. the code is 06h indicating a bridge device. ro device: 30 function: 0 offset: 08h attribute: read-only default value: 08h size: 8-bit device: 30 function: 0 offset: 0ah attribute: read-only default value: 04h size: 8-bit device: 30 function: 0 offset: 0bh attribute: read-only default value: 06h size: 8-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 292 order number: 300641-004us 7.1.8 offset 0dh: pmlt?primary master latency timer register (hub-pci?d30:f0) note: this register does not apply to hub interface. 7.1.9 offset 0eh: headtyp?header type register (hub-pci?d30:f0) 7.1.10 offset 18h: pbus_num?primary bus number register (hub-pci?d30:f0) table 154. offset 0dh: pmlt?primary master latency timer register (hub-pci? d30:f0) bits name description access 7:3 master latency count not implemented. 2:0 reserved reserved. table 155. offset 0eh: headtyp?header type register (hub-pci?d30:f0) bits name description access 7 multi-function device this bit is ?0? to indicate a single function device. ro 6:0 header type 8-bit field identifies the header layout of the configuration space, which is a pci-to-pci bridge in this case. ro table 156. offset 18h: pbus_num?primary bus number register (hub-pci? d30:f0) bits name description access 7:0 primary bus number this field indicates the bus number of the hub interface and is hardwired to 00h. ro device: 30 function: 0 offset: 0dh attribute: read-only default value: 00h size: 8-bit device: 30 function: 0 offset: 0eh attribute: read-only default value: 01h size: 8-bit device: 30 function: 0 offset: 18h attribute: read-only default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 293 7?intel ? 6300ESB ich 7.1.11 offset 19h: sbus_num?secondary bus number register (hub-pci?d30:f0) 7.1.12 offset 1a: sub_bus_num?subordinate bus number register (hub-pci?d30:f0) 7.1.13 offset 1bh: smlt?secondary master latency timer register (hub-pci?d30:f0) this master latency timer (mlt) controls the amount of time that the intel ? 6300ESB ich will continue to burst data as a master on the pci bus. when the intel ? 6300ESB ich starts the cycle after being granted the bus, the counter is loaded and starts counting down from the assertion of frame#. when the internal grant to this device is removed, the expiration of the mlt counter will result in the deassertion of frame#. when the internal grant has not been removed, the intel ? 6300ESB ich may continue to own the bus. when the secondary master latency timer in device 30 (offset 1bh) is programmed to 00h (the default value), the north pci initiator logic operates as though the timer never expires. therefore, with this programming, constant consecutive writes from the hub interface to pci are capable of occupying the pci bus indefinitely without releasing frame#. table 157. offset 19h: sbus_num?secondary bus number register (hub-pci? d30:f0) bits name description access 7:0 secondary bus number this field indicates the bus number of pci. when this number is equal to the primary bus number (i.e., bus #0), the intel ? 6300ESB ich will run hub interface configuration cycles to this bus number as type 1 configuration cycles on pci. r/w table 158. offset 1a: sub_bus_num?subordinate bus number register (hub- pci?d30:f0) bits name description access 7:0 subordinate bus number this field specifies the highest pci bus number below the hub interface to pci bridge. when a type 1 configuration cycle from the hub interface does not fall in the secondary-to- subordinate bus ranges of device 30, the intel ? 6300ESB ich will indicate a master abort back to the hub interface. r/w device: 30 function: 0 offset: 19h attribute: read/write default value: 00h size: 8-bit device: 30 function: 0 offset: 1a attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 294 order number: 300641-004us a value of 00h disables the timer such that the north pci initiator logic is never forced to end a burst prematurely due to a timeout. 7.1.14 offset 1ch: iobase?i/o base register (hub- pci?d30:f0) table 159. offset 1bh: smlt?secondary master latency timer register (hub- pci?d30:f0) bits name description access 7:3 master latency count 5-bit value that indicates the number of pci clocks, in 8-clock increments, that the intel ? 6300ESB ich will remain as master of the bus. r/w 2:0 reserved reserved. table 160. offset 1ch: iobase?i/o base register (hub-pci?d30:f0) bits name description access 7:4 i/o address base bits [15:12] i/o base bits corresponding to address lines 15:12 for 4- kbyte alignment. bits 11:0 are assumed to be padded to 000h. r/w 3:0 i/o addressing capability this is hardwired to 0h, indicating that the hub interface to pci bridge does not support 32-bit i/o addressing. this means that the i/o base and limit upper address registers must be read only. ro device: 30 function: 0 offset: 1bh attribute: read/write default value: 00h size: 8-bit device: 30 function: 0 offset: 1ch attribute: read/write default value: f0h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 295 7?intel ? 6300ESB ich 7.1.15 offset 1dh: iolim?i/o limit register (hub-pci? d30:f0) 7.1.16 offset 1e - 1fh: secsts?secondary status register (hub-pci?d30:f0) note: for the writable bits in this register, writing a 1 will clear the bit. writing a 0 to the bit will have no effect. table 161. offset 1dh: iolim?i/o limit register (hub-pci?d30:f0) bits name description access 7:4 i/o address limit bits [15:12] i/o base bits corresponding to address lines 15:12 for 4 kbyte alignment. bits 11:0 are assumed to be padded to fffh. r/w 3:0 i/o addressing capability this is hardwired to 0h, indicating that the hub interface-to- pci bridge does not support 32-bit i/o addressing. this means that the i/o base and limit upper address registers must be read only. ro table 162. offset 1e - 1fh: secsts?secondary status register (hub-pci? d30:f0) bits name description access 15 detected parity error (dpe) 0 = this bit is cleared by software writing a 1. 1 = the intel ? 6300ESB ich detected a parity error on the pci bus. r/wc 14 received system error (sse) 0 = software clears this bit by writing a?1? to the bit position. 1 = serr# assertion is received on pci. r/wc 13 received master abort (rma) 0 = software clears this bit by writing a?1? to the bit position. 1 = hub interface to pci cycle was master-aborted on pci. r/wc 12 received target abort (rta) 0 = software clears this bit by writing a?1? to the bit position. 1 = hub interface to pci cycle was target-aborted on pci. for ?completion required? cycles from the hub interface, this event should also set the signaled target abort in the primary status register in this device, and the intel ? 6300ESB ich must send the ?target abort? status back to the hub interface. r/wc 11 signaled target abort (sta) intel ? 6300ESB ich does not generate target aborts. ro 10:9 devsel# timing status 01h = medium timing. ro device: 30 function: 0 offset: 1dh attribute: read/write default value: 00h size: 8-bit device: 30 function: 0 offset: 1e-1fh attribute: read/write default value: 0280h size: 16-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 296 order number: 300641-004us 7.1.17 offset 20 - 21h: membase?memory base register (hub-pci?d30:f0) this register defines the base of the hub interface to pci non-prefetchable memory range. since the intel ? 6300ESB ich will forward all hub interface memory accesses to pci, the intel ? 6300ESB ich w ill only use this information for determining when not to accept cycles as a target. this register must be initialized by the configuration software. for the purpose of address decode, address bits ad[19:0] are assumed to be zero. thus, the bottom of the defined memory address range will be aligned to a 1 mbyte boundary. 8 master data parity error detected (mdpd) 0 = software clears this bit by writing a?1? to the bit position. 1 = the intel ? 6300ESB ich sets this bit when all of the following three conditions are met: - the parity error response enable bit in the bridge control register (bit 0, offset 3eh) is set - usb, ac?97 or ide is a master - perr# asserts during a write cycle or a parity error is detected internally during a read cycle r/wc 7 fast back to back hardwired to ?1? to indicate that the pci to hub interface target logic is capable of receiving fast back-to-back cycles. ro 6 user definable features (udf) hardwired to ?0?. ro 5 66 mhz capable hardwired to ?0?. ro 4 perr# assertion detect this bit is set by hardware whenever the perr# pin is asserted on the rising edge of pci clock. this includes cases in which the chipset is the agent driving perr#. it remains asserted until cleared by software writing a ?1? to this location. when enabled by the perr#-to-serr# enable bit (in the bridge control register), a ?1? in this bit can generate an internal serr# and be a source for the nmi logic. r/wc 3:0 reserved reserved. table 162. offset 1e - 1fh: secsts?secondary status register (hub-pci? d30:f0) bits name description access device: 30 function: 0 offset: 1e-1fh attribute: read/write default value: 0280h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 297 7?intel ? 6300ESB ich 7.1.18 offset 22 - 23h: memlim?memory limit register (hub-pci?d30:f0) this register defines the upper limit of the hub interface to pci non-prefetchable memory range. since the intel ? 6300ESB ich will forward all hub interface memory accesses to pci, the intel ? 6300ESB ich will only use this information for determining when not to accept cycles as a target. this register must be initialized by the configuration software. for the purpose of address decode, address bits ad[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be aligned to a 1 mbyte boundary. table 163. offset 20 - 21h: membase?memory base register (hub-pci?d30:f0) bits name description access 15:4 memory address base defines the base of the memory range for pci. these 12 bits correspond to address bits 31:20. r/w 3:0 reserved reserved. device: 30 function: 0 offset: 20-21h attribute: read/write default value: fff0h size: 16-bit table 164. offset 22 - 23h: memlim?memory limit register (hub-pci?d30:f0) bits name description access 15:4 memory address limit defines the top of the memory range for pci. these 12 bits correspond to address bits 31:20. r/w 3:0 reserved reserved. device: 30 function: 0 offset: 22-23h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 298 order number: 300641-004us 7.1.19 offset 24h - 25h: pref_mem_base?prefetchable memory base register (hub-pci?d30:f0) offset address: 24h-25h attribute: r/w default value: 0000fff0h size: 16-bit this register defines the base address of the hub interface-to-pci prefetchable memory range. since the intel ? 6300ESB ich w ill forward all hub interface memory accesses to pci, the intel ? 6300ESB ich will only use this information for determining when not to accept cycles as a target. note: when the hub interface is acting as the initiator, it will not respond as a target. this register must be initialized by the config software. for the purpose of address decode, address bits ad[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be aligned to a 1 mbyte boundary. table 165. offset 24h - 25h: pref_mem_base?prefetchable memory base register (hub-pci?d30:f0) bits name description access 15:4 prefetchable memory address base defines the base address of the prefetchable memory address range for pci. these 12 bits correspond to address bits 31:20. r/w 3:0 reserved reserved. ro device: 30 function: 0 offset: 24h-25h attribute: read/write default value: 0000fff0h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 299 7?intel ? 6300ESB ich 7.1.20 offset 26h-27h: pref_mem_mlt?prefetchable memory limit register (hub-pci?d30:f0) this register defines the upper limit of the hub interface-to-pci non-prefetchable memory range. since the intel ? 6300ESB ich will forward all hub interface memory accesses to pci, the intel ? 6300ESB ich will only use this information for determining when not to accept cycles as a target. note: when the hub interface is acting as the initiator, it will not respond as a target. note: this register must be initialized by the config software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be aligned to a 1 mbyte boundary. 7.1.21 offset 30 - 31h: iobase_hi?i/o base upper 16 bits register (hub-pci?d30:f0) table 166. offset 26h-27h: pref_mem_mlt?prefetchable memory limit register (hub-pci?d30:f0) bits name description access 15:4 prefetchable memory address limit defines the limit address of the prefetchable memory address range for pci. these 12 bits correspond to address bits 31:20. rw 3:0 reserved reserved. ro table 167. offset 30 - 31h: iobase_hi?i/o base upper 16 bits register (hub- pci?d30:f0) bits name description access 15:0 i/o address base upper 16 bits [31:16] not supported; hardwired to 0. ro device: 30 function: 0 offset: 26h-27h attribute: read/write default value: 00000000h size: 16-bit device: 30 function: 0 offset: 30-31h attribute: read-only default value: 0000h size: 16-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 300 order number: 300641-004us 7.1.22 offset 32 - 33h: iolim_hi?i/o limit upper 16 bits register (hub-pci?d30:f0) 7.1.23 offset 3ch: int_line?interrupt line register (hub-pci?d30:f0) table 168. offset 32 - 33h: iolim_hi?i/o limit upper 16 bits register (hub- pci?d30:f0) bits name description access 15:0 i/o address limit upper 16 bits [31:16] not supported; hardwired to 0. ro table 169. offset 3ch: int_line?interrupt line register (hub-pci?d30:f0) bits name description access 7:0 interrupt line routing hardwired to 00h. the bridge does not generate interrupts, and interrupts from downstream devices are routed around the bridge. ro device: 30 function: 0 offset: 32-33h attribute: read-only default value: 0000h size: 16-bit device: 30 function: 0 offset: 3ch attribute: read-only default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 301 7?intel ? 6300ESB ich 7.1.24 offset 3e - 3fh: bridge_cnt?bridge control register (hub-pci?d30:f0) table 170. offset 3e - 3fh: bridge_cnt?bridge control register (hub-pci? d30:f0) (sheet 1 of 3) bits name description access 15:1 1 reserved reserved. 12 perr# to serr# enable when this bit is set to ?1? pci perr nmi reporting is enabled. in addition to setting this bit, you also must set bit 1 of d30_f0 pne register. section 7.1.28 when this bit is set to a ?1? and perr# is asserted on pci, the perr# assertion detect status bit (in the secondary status register) will indicate a perr# internal serr# assertion. the serr# can be a s source on nmi. rw 11 discard timer serr# enable (dtse) controls the generation of serr# on the primary interface in response to a timer discard on the secondary interface: ? when ?0?: do not generate serr# on a secondary timer discard ? when ?1?: generate serr# in response to a secondary timer discard. this bit replaces bit 1 of offset 90h, which held this function in ich3. r/w 10 discard timer status (dts) this bit is set to a ?1? when the secondary discard timer expires (there is no discard timer for the primary interface). this bit replaces bit 1 of offset 92h, which held this function in ich3. r/w 9 secondary discard timer (sdt) sets the maximum number of pci clock cycles that the intel ? 6300ESB ich waits for an initiator on pci to repeat a delayed transaction request. the counter starts once the delayed transaction completion is at the head of the queue. when the master has not repeated the transaction at least once before the counter expires, the intel ? 6300ESB ich discards the transaction from its queue. ? when ?0?: the pci master timeout value is between 2 15 and 2 16 pci clocks ? when ?1?: the pci master timeout value is between 2 10 and 2 11 pci clocks r/w 8 primary discard timer (pdt ) this bit is rw for software compatibility only. r/w 7 fast back to back enable hardwired to ?0?. the pci logic will not generate fast back-to- back cycles on the pci bus. device: 30 function: 0 offset: 3e-3fh attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 302 order number: 300641-004us 6secondary bus reset controls pxpcirst# assertion on pci(x). 1 = the intel ? 6300ESB ich asserts pcixsbrst#. when pcixsbrst# is asserted, the data buffers between the hub interface and pci(x) and the pci(x) bus are initialized back to reset conditions. the hub interface and the configuration registers are not affected. 0 = the intel ? 6300ESB ich deasserts pcixsbrst# r/w 5master abort mode this bit controls the behavior of the intel ? 6300ESB ich when a master abort occurs on a transaction that crosses the hub interface-pci bridge in either direction. the default is 0. when set to 0, the intel ? 6300ESB ich behaves in the following manner: ? hub interface completion-required requests to pci: when these master abort on pci, the intel ? 6300ESB ich returns a master abort status. for reads, ffffh is returned for each dword. ? hub interface posted writes to pci: when these master abort on pci, the intel ? 6300ESB ich discards the data. ? pci reads to hub interface: when these master abort on hub interface, the intel ? 6300ESB ich returns the data provided with the hub interface master abort packet to the pci requestor. ? pci writes to hub interface: intel ? 6300ESB ich has no idea when these ?master-abort.? when set to 1, the intel ? 6300ESB ich treats the master abort as an error: ? hub interface completion-required requests to pci: when these master abort on pci, the intel ? 6300ESB ich returns a target abort status. for reads, ffffh is returned for each dword. ? hub interface posted writes to pci: when these master abort on pci, the intel ? 6300ESB ich discards the data and sets the primary signaled serr# bit (when the corresponding serr_en bit is set). ? pci reads to hub interface: when these master abort on hub interface, the intel ? 6300ESB ich terminates the cycle with a target abort and flushes the remainder of the prefetched data. ? pci writes to hub interface: the intel ? 6300ESB ich has no idea when these ?master-abort.? r/w vga 16-bit decode this bit does not have any functionality relative to address decodes because the intel ? 6300ESB ich will forward the cycles to pci, independent of the decode. writes of one have no impact other than to force the bit to one. writes of zero have no impact other than to force the bit to zero. reads to this bit will return the previously written value (or zero when no writes since reset). table 170. offset 3e - 3fh: bridge_cnt?bridge control register (hub-pci? d30:f0) (sheet 2 of 3) bits name description access device: 30 function: 0 offset: 3e-3fh attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 303 7?intel ? 6300ESB ich 3vga enable 0 = no vga device on pci. 1 = indicates that the vga device is on pci. therefore, the pci to hub interface decoder will not accept memory cycles in the range a0000h-bffffh. note that the intel ? 6300ESB ich will never take i/o cycles in the vga range from pci. if vga is enabled on pci-x bridge device 28 function 0, offset 3eh, bit 3. pci-x will claim memory cycles in the vga range before the legacy pci bridge. r/w 2isa enable the intel ? 6300ESB ich ignores this bit. however, this bit is read/write for software compatibility. since the intel ? 6300ESB ich forwards all i/o cycles that are not in the usb, ac?97, or ide ranges to pci, this bit would have no effect. isa should be enabled on the legacy pci or the pci/pci-x bridge, but not both. if both are enabled, unpredictable results will occur. r/w 1 serr# enable 0 = disable 1 = when this bit is set and bit 8 in cmd register (d30:f0 offset 04h) is also set, the intel ? 6300ESB ich will set the sse bit in pd_sts register (d30:f0, offset 06h, bit 14) and also generate an nmi (or smi# if nmi routed to smi) when the serr# signal is asserted. the internal serr# will be generated only if the serr_en bit is also set in offset 04h. note: see section 5.1.4, ?serr# functionality? for more details on this bit. r/w 0 parity error response enable 0 = disable 1 = enable the hub interface to pci bridge for parity error detection and reporting on the pci bus. r/w table 170. offset 3e - 3fh: bridge_cnt?bridge control register (hub-pci? d30:f0) (sheet 3 of 3) bits name description access device: 30 function: 0 offset: 3e-3fh attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 304 order number: 300641-004us 7.1.25 offset 40 - 43h: hi_cmd?hub interface command control register (hub-pci?d30:f0) table 171. offset 40 - 43h: hi_cmd?hub interface command control register (hub-pci?d30:f0) bits name description access 31:2 0 reserved reserved. 30:2 8 sata hub id this field identifies the hub interface id number for the serial ata requests on the hub interface. default=111b ro 27 reserved reserved. ro 26:2 4 second hub id this field identifies the hub interface id number for integrated requesters. default=110b ro 23:2 1 first hub id this field identifies the hub interface id number for integrated requesters. hardwired to 001b ro 20 hub interface parity unsupported when set to 1, the intel ? 6300ESB ich will not check parity on the hub interface even if enabled to do so according to the parity error response bit in d30.f0.04h bit 6 or if the parity error response bit of d28.f0.04h bit 6 is set. r/w 19:1 6 hub interface timeslice this field sets the hub interface arbiter time-slice value with four base-clock granularity. a value of 0h means that the time-slice is immediately expired and that the intel ? 6300ESB ich will allow the other master?s request to be serviced after every message. r/w 15:1 4 hi width this field is hardwired to 00b, indicating that the hub interface is eight bits wide. ro 13 hi rate_valid hardwired to ?1?. ro 12:1 0 hi rate encoded value representing the clock-to-transfer rate of the hub interface: 1:4 = 010b the value is loaded at reset by sampling the capability of the device connected to the hub interface port. the value for this field is fixed for 4x mode only. ro 9:4 reserved reserved. 3:1 max data (maxd) hardwired to 001b. this field specifies the maximum amount of data that the intel ? 6300ESB ich is allowed to burst in one packet on the hub interface. the intel ? 6300ESB ich will always do 64 byte bursts. ro 0 reserved reserved. device: 30 function: 0 offset: 40-43h attribute: read/write default value: 76202802h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 305 7?intel ? 6300ESB ich 7.1.26 offset 44 - 45h: device_hide?secondary pci device hiding register (hub-pci?d30:f0) this register allows software to ?hide? pci devices. specifically, when pci devices are hidden, the configuration space is not accessible because the pci idsel pin does not assert. the intel ? 6300ESB ich supports the ability to hide four external devices (0 through 3). hiding a pci device may be useful for debugging, bug work-arounds, and system management support. devices should only be hidden during initialization before any configuration cycles are run. this ensures that the device is not in a semi-enable state. table 172. offset 44 - 45h: device_hide?secondary pci device hiding register (hub-pci?d30:f0) bits name description access 15:9 reserved reserved. 8 reserved reserved. 7:6 reserved reserved. 5 reserved reserved. 4 reserved reserved. 3 hide_dev3 same as bit 0 of this register, except for device 3 (ad{19]). 2 hide_dev2 same as bit 0 of this register, except for device 2 (ad{18]). 1 hide_dev1 same as bit 0 of this register, except for device 1 (ad[17]) 0hide_dev0 when this bit is set, it hides device 0 on the pci bus. this is done by masking the idsel (keeping it low) for configuration cycles to that device. since the device will not see its idsel go active, it will not respond to pci configuration cycles and the processor will think the device is not present. ad[16] is used as idsel for device 0. when this bit is a 0, the pci configuration cycles for this slot are not affected. device: 30 function: 0 offset: 44-45h attribute: read/write default value: 00h size: 16-bit power well: 00h
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 306 order number: 300641-004us 7.1.27 offset 50 - 51h: cnf?intel ? 6300ESB ich configuration register (hub-pci?d30:f0) note: refer to the latest revision of the intel ? 6300ESB ich bios specification for the recommended configuration of this register. table 173. offset 50 - 51h: cnf?intel? 6300ESB ich configuration register (hub-pci?d30:f0) bits name description access 15:1 4 reserved reserved. 13 prefetch flush enable prefetch flush enable . 0 = prefetch flush disable 1 = causes cpu to pci logic to only deliver ?demand? data for a delayed transaction if a processor-to-pci write has occurred since the delayed transaction was initiated. (default) note: this bit must be set by system bios. r/w 12:1 0 reserved reserved. 9 hp_pci_en high priority pci enable 0 = all pci req#/gnt pairs have the same arbitration priority. 1 = enables a mode where the req[0]#/gnt[0]# signal pair has a higher arbitration priority. r/w 8 hole enable (15 mb-16 mb) 0 = disable 1 = enables the 15 mbyte to 16 mbyte hole in the dram. r/w 7 reserved reserved. 6 hi-pci write combining enable hi-pci write combining enable 1 = disables hub interface to pci write combining r/w 5:3 reserved reserved. 2 delayed transaction discard timer delayed transaction discard timer when set to 1 this bit shortens all delayed transaction discard timers to 128 pci clocks. r/w 1:0 reserved reserved. device: 30 function: 0 offset: 50-51h attribute: read/write default value: 1400h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 307 7?intel ? 6300ESB ich 7.1.28 offset 58 - 5bh: d30_pne ? perr#_nmi_enable register (hub-pci?d30:f0) table 174. offset 58 - 5bh: d30_pne ? perr#_nmi_enable register (hub- pci?d30:f0) bits name description access 31:2 2 reserved reserved. 21:2 0 outstanding sata mem read acceptance indicate the number of outstanding (not completed) memory read requests from sata that are accepted. the value of the bits is decoded as follows: 00 = disable this feature by allowing stunit to accept any number of outstanding memory reads from sata until its buffer resources are full. 11 accepts four outstanding reads from sata. default note: default value is 11b, bios must write 00 to this register r/w 19:8 reserved reserved. 7sata request enable 0 = the arbiter will block s-ata requests when there is a lock transaction targeting pcix. 1 = the arbiter will allow s-ata requests even when there is a lock transaction targeting pcix. note: default value should be 0b, bios must write 1 to this register 6:3 reserved reserved. 2 pci-x perr nmi reporting this bit enables pci-x perr nmi reporting. when this bit is set to ?1? pci-x perr nmi reporting is enabled. once enabled, this bit should not change. in addition to setting this bit, you also must set bit 12 of d30_f0 bridge control register. see section section 18.6.1.21 . default = 0 r/w 1pci perr nmi reporting this bit enables pci perr nmi reporting. when this bit is set to ?1? pci perr nmi reporting is enabled. once enabled, this bit should not change. in addition to setting this bit, you also must set bit 12 of d30_f0 bridge control register. see section section 18.6.1.21 . default = 0 r/w 0 reserved reserved. device: 30 function: 0 offset: 58-5bh attribute: read/write default value: 01341150h size: 32-bit
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 308 order number: 300641-004us 7.1.29 offset 70h: mtt?multi-transaction timer register (hub-pci?d30:f0) mtt is an 8-bit register that controls the amount of time that the intel ? 6300ESB ich?s arbiter allows a pci initiator to perform multiple back-to-back transactions on the pci bus. the intel ? 6300ESB ich?s mtt mechanism is used to ensure a fair share of the primary pci bandwidth to an initiator that performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence it may not use long burst transfers). the number of clocks programmed in the mtt represents the ensured time slice (measured in pci clocks) allotted to the current agent, after which the arbiter will grant another agent that is requesting the bus. the mtt value must be programmed with 8- clock granularity in the same manner as mlt. for example, if the mtt is programmed to 18h, then the selected value corresponds to the time period of 24 pci clocks.the default value of mtt is 20h (32 pci clocks). note: programming the mtt to a value of 00h disables this function, which could cause starvation problems for some pci master devices. programming of the mtt to anything less than 16 clocks will not allow the grant-to-frame# latency to be 16 clocks. the mtt timer will timeout before the grant-to-frame# trigger causing a rearbitration. table 175. offset 70h: mtt?multi-transaction timer register (hub-pci? d30:f0) bits name description access 7:3 multi-transaction timer count value this field specifies the amount of time that grant will remain asserted to a master continuously asserting its request for multiple transfers. this field specifies the count in an 8-clock (pci clock) granularity. r/w 2:0 reserved reserved. device: 30 function: 0 offset: 70h attribute: read/write default value: 20h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 309 7?intel ? 6300ESB ich 7.1.30 offset 82h: pci_mast_sts?pci master status register (hub-pci?d30:f0) 7.1.31 offset 90h: err_cmd?error command register (hub-pci?d30:f0) note: this register configures the intel ? 6300ESB ich?s device 30 responses to various system errors. the actual assertion of the internal serr# (routed to cause nmi# or smi#) is enabled through the pci command register. table 176. offset 82h: pci_mast_sts?pci master status register (hub-pci? d30:f0) bits name description access 7 internal south pci master request status (int_mreq_sts) allows software to see if the internal dma controller or lpc has requested use of the pci bus. 0 = software clears this bit by writing a?1?to the bit position. 1 = the intel ? 6300ESB ich?s internal dma controller or lpc has requested use of the pci bus. r/wc 6:4 reserved reserved. 3:0 pci master request status (pci_mreq_sts) allows software to see if a particular bus master has requested use of the pci bus. 0 = software clears these bits by writing a 1 to the bit position. 1 = the associated pci master has requested use of the pci bus. r/wc table 177. offset 90h: err_cmd?error command register (hub-pci?d30:f0) bits name description access 7:3 reserved reserved. 2 serr# enable on receiving target abort (serr_rta_en) 0 = disable. 1 = enable. when serr_en is set, the intel ? 6300ESB ich will report serr# when serr_rta is set. r/w 1:0 reserved reserved. bit 1 was the serr# enabled for delayed transaction timeout, see section 7.1.24, ?offset 3e - 3fh: bridge_cnt?bridge control register (hub-pci?d30:f0)? . device: 30 function: 0 offset: 82h attribute: read/write clear default value: 00h size: 8-bit device: 30 function: 0 offset: 90h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?7 intel ? 6300ESB i/o controller hub ds november 2007 310 order number: 300641-004us 7.1.32 offset 92h: err_sts?error status register (hub-pci?d30:f0) note: this register records the cause of system errors in device 30. the actual assertion of serr# is enabled through the pci command register. 7.1.33 offset f8h - fbh: manid? manufacturer?s id table 178. offset 92h: err_sts?error status register (hub-pci?d30:f0) bits name description access 7:3 reserved reserved. 2 serr# due to received ta rg e t ab o r t (serr_rta) 0 = this bit is cleared by writing a 1. 1 = intel ? 6300ESB ich sets this bit when the intel ? 6300ESB ich receives a target abort. when serr_en, the intel ? 6300ESB ich will also generate an serr# when serr_rta is set. r/w 1:0 reserved reserved. bit 1 was the serr# enabled for delayed transaction timeout, see section 7.1.24, ?offset 3e - 3fh: bridge_cnt?bridge control register (hub-pci?d30:f0)? . table 179. offset f8h - fbh: manid? manufacturer?s id bits name description access 31:1 6 reserved reserved. 15:8 manufacturer 0fh = intel ro 7:0 process/dot 66h = process 859.6 ro device: 30 function: 0 offset: 92h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 30 function: 0 offset: f8h-fbh attribute: read-only default value: 0000 0f66h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 311 8?intel ? 6300ESB ich lpc i/f bridge registers (d31:f0) 8 the lpc bridge function of the intel ? 6300ESB ich resides in pci device 31:function 0. this function contains many other functional units, such as dma and interrupt controllers, timers, power management, system management, gpio rtc and lpc. registers and functions associated with other functional units (usb uhci, usb ehci, ide, etc.) are described in their respective sections. 8.1 pci configuration registers (d31:f0) note: registers that are not shown should be treated as reserved. (see section 6.2, ?pci configuration map? for details). . table 180. pci configuration registers (d31:f0) (sheet 1 of 2) offset mnemonic register name default type 00-01h vid vendor id 8086h ro 02-03h did device id 25a1h ro 04-05h pcicmd pci command register 000fh r/w 06-07h pcista pci device status 0280h r/w 08h rid revision id see note: ro 09h pi programming interface 00h ro 0ah scc sub class code 01h ro 0bh bcc base class code 06h ro 0eh headtyp header type 80h ro 40-43h pmbase acpi base address 00000001h r/w 44h acpi_cntl acpi control 00h r/w 4e-4fh bios_cntl bios control 0000h r/w 54h tco_cntl tco control 00h r/w 58-5bh gpio_base gpio base address 00000001h r/w 5ch gpio_cntl gpio control 00h r/w 60-63h pirq[ n ]_rout pirq[a-d] routing control 80808080h r/w 64h serirq serial irq control 50h r/w 68-6bh pirq[ n ]_rout pirq[e-h] routing control 80808080h r/w 88h d31_err_cfg device 31 error config 00h r/w 8ah d31_err_sts device 31 error status 00h r/w 90-91h pci_dma_cfg pci dma configuration 0000h r/w note: refer to the intel ? 6300ESB ich specification update for the most up-to-date value of the revision id register.
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 312 order number: 300641-004us 8.1.1 offset 00 - 01h: vid?vendor id register (lpc i/ f?d31:f0) a0-cfh power management d0-d3h gen_cntl general control 00000080h r/w d4h gen_sta general status 0xh r/w d5h back_cntl backed up control 00f r/w d8h rtc_conf real time clock configuration 00h r/w e0h com_dec lpc i/f com port decode ranges 00h r/w e1h fdd/lpt_dec lpc i/f fdd and lpt decode ranges 00h r/w e2h snd_dec lpc i/f sound decode ranges 00h r/w e3h fwh_dec_en1 fwh decode enable 1 ffh r/w e4-e5h gen1_dec lpc i/f general 1 decode range 0000h r/w e6-e7h lpc_en lpc i/f enables 00h r/w e8-ebh fwh_sel1 fwh select 1 00112233h r/w ec-edh gen2_dec lpc i/f general 2 decode range 0000h r/w ee-efh fwh_sel2 fwh select 2 5678h r/w f0h fwh_dec_en2 fwh decode enable 2 0fh r/w f2h func_dis function disable register 0080h r/w f4-f7h etr1 pci-x extended features 00000000h r/w f8h-fbh manufacturer?s id 000s0f66 ro table 181. offset 00 - 01h: vid?vendor id register (lpc i/f?d31:f0) bits name description access 15:0 vendor id value this is a 16-bit value assigned to intel. intel vid = 8086h ro table 180. pci configuration registers (d31:f0) (sheet 2 of 2) offset mnemonic register name default type note: refer to the intel ? 6300ESB ich specification update for the most up-to-date value of the revision id register. device: 31 function: 0 offset: 00-01h attribute: read-only default value: 8086h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 313 8?intel ? 6300ESB ich 8.1.2 offset 02 - 03h: did?device id register (lpc i/ f?d31:f0) 8.1.3 offset 04 - 05h: pcicmd?pci command register (lpc i/f?d31:f0) table 182. offset 02 - 03h: did?device id register (lpc i/f?d31:f0) bits name description access 15:0 device id value this is a 16-bit value assigned to the intel ? 6300ESB ich lpc bridge. table 183. offset 04 - 05h: pcicmd?pci command register (lpc i/f?d31:f0) bits name description access 15:1 0 reserved reserved. 9 fbe: fast back to back enable hardwired to 0. ro 8 serr_en: serr# enable 0 = disable. 1 = enable. allow serr# to be generated. 7 wcc: wait cycle control hardwired to 0. ro 6 per: parity error response 0 = no action is taken when detecting a parity error. 1 = the processor will take normal action when a parity error is detected. 5 vps: vga palette snoop hardwired to 0 ro 4 pmwe: postable memory write enable hardwired to 0 ro 3 sce: special cycle enable hardwired to 1. 2 bme: bus master enable hardwired to 1 to indicate that bus mastering cannot be disabled for function 0 (dma/isa master) ro 1 mse: memory space enable hardwired to 1 to indicate that memory space cannot be disabled for function 0 (lpc i/f) ro 0 ioe: i/o space enable hardwired to 1 to indicate that the i/o space cannot be disabled for function 0 (lpc i/f) ro device: 31 function: 0 offset: 02-03h attribute: read-only default value: 25a1h size: 16-bit lockable: no power well: core device: 31 function: 0 offset: 04-05h attribute: read/write default value: 000fh size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 314 order number: 300641-004us 8.1.4 offset 06 - 07h: pcista?pci device status (lpc i/f?d31:f0) table 184. offset 06 - 07h: pcista?pci device status (lpc i/f?d31:f0) bits name description access 15 dpe: detected parity error 0 = this bit is cleared by software writing a 1 to the bit position. 1 = perr# signal goes active. set even when the per bit is 0. r/w 14 sse: signaled system error 0 = this bit is cleared by software writing a 1 to the bit position. 1 = set by the intel ? 6300ESB ich n the serr_en bit is set and the intel ? 6300ESB ich generates an serr# on function 0. the err_sts register may be read to determine the cause of the serr#. the serr# may be routed to cause smi#, nmi, or interrupt. r/w 13 rma: received master abort 0 = this bit is cleared by software writing a 1 to the bit position. 1 = the intel ? 6300ESB ich generated a master abort on pci due to lpc i/f master or dma cycles. r/w 12 rta: received target abort 0 = this bit is cleared by software writing a 1 to the bit position. 1 = the intel ? 6300ESB ich received a target abort during lpc i/f master or dma cycles to pci. r/w 11 sta: signaled target abort 0 = this bit is cleared by software writing a 1 to the bit position. 1 = the intel ? 6300ESB ich generated a target abort condition on pci cycles claimed by the intel ? 6300ESB ich for intel ? 6300ESB ich internal registers or for going to lpc i/f. r/w 10:9 dev_sts: devsel# timing status 01 = medium timing. ro 8 dped: data parity error detected 0 = this bit is cleared by software writing a 1 to the bit position. 1 = set when all three of the following conditions are true: - the intel ? 6300ESB ich is the initiator of the cycle, - the intel ? 6300ESB ich asserted perr# (for reads) or observed perr# (for writes), and - the per bit is set. r/wc 7 fb2b: fast back to back always 1. indicates the intel ? 6300ESB ich as a target may accept fast back-to-back transactions. ro 6 udf: user definable features hardwired to 0 5 66mhz_cap: 66 mhz capable hardwired to 0 ro 4:0 reserved reserved. device: 31 function: 0 offset: 06-07h attribute: read/write clear default value: 0280h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 315 8?intel ? 6300ESB ich 8.1.5 offset 08h: rid?revision id register (lpc i/f? d31:f0) 8.1.6 offset 09h: pi?programming interface (lpc i/f? d31:f0) 8.1.7 offset 0ah: scc?sub-class code register (lpc i/f?d31:f0) table 185. offset 08h: rid?revision id register (lpc i/f?d31:f0) bits name description access 7:0 revision id value refer to the intel ? 6300ESB ich specification update for the most up-to-date value of the revision id register. ro table 186. offset 09h: pi?programming interface (lpc i/f?d31:f0) bits name description access 7:0 programming interface value programming interface value. ro table 187. offset 0ah: scc?sub-class code register (lpc i/f?d31:f0) bits name description access 7:0 sub-class code 8-bit value that indicates the category of bridge for the lpc pci bridge. ro device: 31 function: 0 offset: 08h attribute: read-only default value: see bit description size: 8-bit device: 31 function: 0 offset: 09h attribute: read-only default value: 00h size: 8-bit device: 31 function: 0 offset: 0ah attribute: read-only default value: 01h size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 316 order number: 300641-004us 8.1.8 offset 0bh: bcc?base-class code register (lpc i/f?d31:f0) 8.1.9 offset 0eh: headtyp?header type register (lpc i/f?d31:f0) table 188. offset 0bh: bcc?base-class code register (lpc i/f?d31:f0) bits name description access 7:0 base class code 8-bit value that indicates the type of device for the lpc bridge. the code is 06h indicating a bridge device. ro table 189. offset 0eh: headtyp?header type register (lpc i/f?d31:f0) bits name description access 7 multi-function device this bit is 1 to indicate a multi-function device. ro 6:0 header type 7-bit field identifies the header layout of the configuration space. ro device: 31 function: 0 offset: 0bh attribute: read-only default value: 06h size: 8-bit device: 31 function: 0 offset: 0eh attribute: read-only default value: 0eh size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 317 8?intel ? 6300ESB ich 8.1.10 offset 40 - 43h: pmbase?acpi base address (lpc i/f?d31:f0) note: usage: acpi or legacy. note: sets base address for acpi i/o registers and tco i/o registers. may be mapped anywhere in the 64k i/o space on 128-byte boundaries. 8.1.11 offset 44h: acpi_cntl?acpi control (lpc i/f? d31:f0) note: usage: acpi or legacy. table 190. offset 40 - 43h: pmbase?acpi base address (lpc i/f?d31:f0) bits name description access 31:1 6 reserved reserved. 15:7 base address provides 128 bytes of i/o space for acpi, gpio, and tco logic. this is placed on a 128-byte boundary. r/w 6:1 reserved reserved. 0 resource indicator tied to 1 to indicate i/o space. ro table 191. offset 44h: acpi_cntl?acpi control (lpc i/f?d31:f0) (sheet 1 of 2) bits name description access 7:5 reserved reserved. device: 31 function: 0 offset: 40-43h attribute: read/write default value: 00000001h size: 32-bit lockable: no power well: core device: 31 function: 0 offset: 44h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 318 order number: 300641-004us 4 acpi_en: acpi enable 0 = disable. 1 = decode of the i/o range pointed to by the acpi base register is enabled, and the acpi power management function is enabled. note that the apm power management ranges (b2/b3h) are always enabled and are not affected by this bit. r/w 3 reserved reserved. 2:0 sci_irq_sel: sci irq select specifies on which irq the sci will internally appear. when not using the apic, the sci must be routed to irq9-11, and that interrupt is not shared with the serirq stream, but may be shared with other pci interrupts. when using the apic, the sci may also be mapped to irq20-23, and may be shared with other interrupts. bits sci map 000 irq9 001 irq10 010 irq11 011 reserved 100 irq20 (only available when apic enabled) 101 irq21 (only available when apic enabled) 110 irq22 (only available when apic enabled) 111 irq23 (only available when apic enabled) note: when the interrupt is mapped to apic interrupts 9, 10, or 11, the apic should be programmed for active- high reception. when the interrupt is mapped to apic interrupts 20 through 23, the apic should be programmed for active-low reception. r/w table 191. offset 44h: acpi_cntl?acpi control (lpc i/f?d31:f0) (sheet 2 of 2) bits name description access device: 31 function: 0 offset: 44h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 319 8?intel ? 6300ESB ich 8.1.12 offset 4e - 4fh: bios_cntl (lpc i/f?d31:f0) table 192. offset 4e - 4fh: bios_cntl (lpc i/f?d31:f0) bits name description access 15:2 reserved reserved. 1 ble: bios lock enable 0 = setting the bioswe will not cause smis. once set, this bit may only be cleared by a pxpcirst#. 1 = enables setting the bioswe bit to cause smis. r/w 0 bioswe: bios write enable 0 = only read cycles result in fwh i/f cycles. 1 = access to the bios space is enabled for both read and write cycles. when this bit is written from a 0 to a 1 and bios lock enable (ble) is also set, an smi# is generated. this ensures that only smi code may update bios. r/w device: 31 function: 0 offset: 4e-4fh attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 320 order number: 300641-004us 8.1.13 offset 54h: tco_cntl?tco control (lpc i/f? d31:f0) table 193. offset 54h: tco_cntl?tco control (lpc i/f?d31:f0) bits name description access 7:4 reserved reserved. 3 tco_int_en: tco interrupt enable this bit enables/disables the tco interrupt. 0 = disables tco interrupt. 1 = enables tco interrupt, as selected by the tco_int_sel field. r/w 2:0 tco_int_sel: tco interrupt select specifies on which irq the tco will internally appear. when not using the apic, the tco interrupt must be routed to irq9-11, and that interrupt is not shared with the serirq stream, but may be shared with other pci interrupts. when using the apic, the tco interrupt may also be mapped to irq20-23, and may be shared with other interrupt. note that when the tcosci_en bit is set (bit 6 of the gpeo_en register), the tco interrupt will be sent to the same interrupt as the sci, and the tco_int_sel bits will have no meaning. when the tco interrupt is mapped to apic interrupts 9, 10 or 11, the signal is in fact active high. when the tco interrupt is mapped to irq 20, 21, 22, or 23 the signal is active low and may be shared with pci interrupts that may be mapped to those same signals (irqs). bits sci map 000 irq9 001 irq10 010 irq11 011 reserved 100 irq20 (only available when apic enabled) 101 irq21 (only available when apic enabled) 110 irq22 (only available when apic enabled) 111 irq23 (only available when apic enabled) r/w device: 31 function: 0 offset: 54h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 321 8?intel ? 6300ESB ich 8.1.14 offset 58h - 5bh: gpio_base?gpio base address (lpc i/f?d31:f0) note: sets base address for gpio registers. may be mapped anywhere in the 64k i/o space on 128-byte boundaries. 8.1.15 offset 5ch: gpio_cntl?gpio control (lpc i/f? d31:f0) table 194. offset 58h - 5bh: gpio_base?gpio base address (lpc i/f?d31:f0) bits name description access 31:1 6 reserved reserved. 15:6 base address provides the 64 bytes of i/o space for gpio. r/w 5:1 reserved reserved. 0 resource indicator tied to 1 to indicate i/o space. ro table 195. offset 5ch: gpio_cntl?gpio control (lpc i/f?d31:f0) bits name description access 7:5 reserved reserved. 4 gpio_en: gpio enable this bit enables/disables decode of the i/o range pointed to by the gpio base register and enables/disables the gpio function. 0 = disable. 1 = enable. r/w 3:0 reserved reserved. device: 31 function: 0 offset: 58h-5bh attribute: read/write default value: 00000001h size: 32-bit lockable: no power well: core device: 31 function: 0 offset: 5ch attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 322 order number: 300641-004us 8.1.16 offset pirqa - 60h: pirq[n]_rout? pirq[a,b,c,d] routing control (lpc i/f?d31:f0) table 196. offset pirqa - 60h: pirq[n]_rout?pirq[a,b,c,d] routing control (lpc i/f?d31:f0) bits name description access 7 irqen: interrupt routing enable 0 = the corresponding pirq is routed to one of the isa- compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to ?0? during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. r/w 6:4 reserved reserved. 3:0 irq routing (isa compatible) bits mapping bits mapping 0000 = reserved 1000 = reserved 0001 = reserved 1001 = irq9 0010 = reserved 1010 = irq10 0011 = irq3 1011 = irq11 0100 = irq4 1100 = irq12 0101 = irq5 1101 = reserved 0110 = irq6 1110 = irq14 0111 = irq7 1111 = irq15 r/w device: 31 function: 0 offset: pirqa - 60h, pirqb - 61h, pirqc - 62h, pirqd - 63h attribute: read/write default value: 80h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 323 8?intel ? 6300ESB ich 8.1.17 offset 64h: serirq_cntl?serial irq control (lpc i/f?d31:f0) table 197. offset 64h: serirq_cntl?serial irq control (lpc i/f?d31:f0) bits name description access 7 sirqen: serial irq enable 0 = the buffer is input only and internally serirq will be a 1. 1 = serial irqs will be recognized. the serirq pin will be configured as serirq. r/w 6 sirqmd: serial irq mode select 0 = the serial irq machine will be in quiet mode. 1 = the serial irq machine will be in continuous mode. note: for systems using quiet mode, this bit should be set to 1 (continuous mode) for at least one frame after coming out of reset before switching back to quiet mode. failure to do so will result in the intel ? 6300ESB ich not recognizing serirq interrupts. in order to enable uarts, the lpc master should be programmed to be in continuous mode. uart by default will be programmed to be in continuous mode. r/w 5:2 sirqsz: serial irq frame size fixed field that indicates the size of the serirq frame. in the intel ? 6300ESB ich, this field needs to be programmed to 21 frames (0100). this is an offset from a base of 17 which is the smallest data frame size. r/w 1:0 sfpw: start frame pulse width this is the number of pci clocks that the serirq pin will be driven low by the serial irq machine to signal a start frame. in continuous mode, the intel ? 6300ESB ich will drive the start frame for the number of clocks specified. in quiet mode, the intel ? 6300ESB ich will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = reserved r/w device: 31 function: 0 offset: 64h attribute: read/write default value: 10h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 324 order number: 300641-004us 8.1.18 offset pirqe - 68h: pirq[n]_rout? pirq[e,f,g,h] routing control (lpc i/f?d31:f0) table 198. offset pirqe - 68h: pirq[n]_rout?pirq[e,f,g,h] routing control (lpc i/f?d31:f0) bits name description access 7irqen interrupt routing enable 0 = the corresponding pirq is routed to one of the isa- compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to ?0? during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. r/w 6:4 reserved reserved. 3:0 irq routing (isa compatible) 0000 = reserved1000 = reserved 0001 = reserved1001 = irq9 0010 = reserved1010 = irq10 0011 = irq31011 = irq11 0100 = irq41100 = irq12 0101 = irq51101 = reserved 0110 = irq61110 = irq14 0111 = irq71111 = irq15 r/w device: 31 function: 0 offset: pirqe - 68h, pirqf - 69h, pirqg - 6ah, pirqh - 6bh attribute: read/write default value: 80h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 325 8?intel ? 6300ESB ich 8.1.19 offset 88h: d31_err_cfg?device 31 error config register (lpc i/f?d31:f0) note: this register configures the intel ? 6300ESB ich?s device 31 responses to various system errors. the actual assertion of serr# is enabled through the pci command register. 8.1.20 offset 8ah: d31_err_sts?device 31 error status register (lpc i/f?d31:f0) note: this register configures the intel ? 6300ESB ich?s device 31 responses to various system errors. the actual assertion of serr# is enabled through the pci command register. table 199. offset 88h: d31_err_cfg?device 31 error config register (lpc i/f? d31:f0) bits name description access 7:3 reserved reserved. 2 serr_rta_en: serr# on received target abort enable 0 = disable. no serr# assertion on received target abort. 1 = the intel ? 6300ESB ich will generate serr# if the serr_rta is set and if serr_en is set. r/w 1 serr_dtt_en: serr# on delayed transaction timeout enable 0 = disable. no serr# assertion on delayed transaction timeout. 1 = the intel ? 6300ESB ich will generate serr# if the serr_dtt bit is set and if serr_en is set. r/w 0 reserved reserved. device: 31 function: 0 offset: 88h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 326 order number: 300641-004us 8.1.21 offset 90h - 91h: pci_dma_cfg?pci dma configuration (lpc i/f?d31:f0) note: since there is no isa bus, the default is for dma to be disabled. bios must set particular channels for lpc dma. when isa is present (through moonisa), channels not assigned to lpc should be assigned as disabled. table 200. offset 8ah: d31_err_sts?device 31 error status register (lpc i/f? d31:f0) bits name description access 7:3 reserved reserved. 2 serr_rta: serr# due to received target abort 0 = software clears this bit by writing a 1 to the bit location. 1 = the intel ? 6300ESB ich sets this bit when it receives a target abort. when serr_en, the intel ? 6300ESB ich will also generate an serr# when serr_rta is set. r/wc 1 serr_dtt: serr# due to delayed transaction timeout 0 = software clears this bit by writing a 1 to the bit location. 1 = when a pci master does not return for the data within 1 ms of the cycle?s completion, the intel ? 6300ESB ich clears the delayed transaction and sets this bit. when both serr_dtt_en and serr_en are set, then intel ? 6300ESB ich will also generate an serr# when serr_dtt is set. r/wc 0 reserved reserved. table 201. offset 90h - 91h: pci_dma_cfg?pci dma configuration (lpc i/f? d31:f0) (sheet 1 of 2) bits name description access 15:1 4 channel 7 select 00 = reserved 01 = reserved 10 = reserved 11 = lpc i/f dma r/w 13:1 2 channel 6 select same bit decode as for channel 7. r/w 11:1 0 channel 5 select same bit decode as for channel 7. r/w 9:8 reserved reserved. 7:6 channel 3 select same bit decode as for channel 7. r/w device: 31 function: 0 offset: 8ah attribute: read/write clear default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 0 offset: 90h-91h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 327 8?intel ? 6300ESB ich 8.1.22 offset d0h - d3h: gen_cntl?general control register (lpc i/f?d31:f0) 5:4 channel 2 select same bit decode as for channel 7. r/w 3:2 channel 1 select same bit decode as for channel 7. r/w 1:0 channel 0 select same bit decode as for channel 7. r/w table 202. offset d0h - d3h: gen_cntl?general control register (lpc i/f? d31:f0) (sheet 1 of 3) bits name description access 31:2 5 reserved reserved. 24 hide_isa: hide isa bridge 0 = the intel ? 6300ESB ich will not prevent ad22 from asserting during config cycles to the pci-to-isa bridge. 1 = software sets this bit to 1 to disable config cycle from being claimed by a pci-to-isa bridge. this will prevent the os pci pnp from getting confused by seeing two isa bridges. it is required for the intel ? 6300ESB ich pci address line ad22 to connect to the pci-to-isa bridge?s idsel input. when this bit is set, the intel ? 6300ESB ich will not assert ad22 during config cycles to the pci-to-isa bridge. r/w 23:2 2 reserved reserved. 21 ferr#-mux-en: cpu break event indication enable 0 = (default) the intel ? 6300ESB ich will not examine the ferr# signal during c2, c3 or c4. 1 = software sets this bit to 1 to enable the intel ? 6300ESB ich to examine the ferr# signal during a c2, c3 or c4 state as a break event. (see section 5.11.6, ?dynamic processor clock control? for details.) r/w 20 reserved reserved. table 201. offset 90h - 91h: pci_dma_cfg?pci dma configuration (lpc i/f? d31:f0) (sheet 2 of 2) bits name description access device: 31 function: 0 offset: 90h-91h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core device: 31 function: 0 offset: d0h - d3h attribute: read/write default value: 00000080h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 328 order number: 300641-004us 19:1 8 scratchpad these bits are provided for possible future use. 17 mmt_addr_en when set to 1, this bit enables the intel ? 6300ESB ich to decode the high performance event timer memory address range selected by bits 16:15 below. 16:1 5 mmt_addr_sel this 2-bit field selects 1 of 4 possible memory address ranges for the high performance event timer functionality. the encodings are: bits [16:15] memory address range 00 fed0_0000h - fed0_03ffh 01 fed0_1000h - fed0_13ffh 10 fed0_2000h - fed0_23ffh 11 fed0_3000h - fed0_33ffh 14 reserved reserved. 13 copr_err_en: coprocessor error enable 0 = ferr# will not generate irq13 nor ignne#. 1 = when ferr# is low, the intel ? 6300ESB ich generates irq13 internally and holds it until an i/o write to port f0h. it will also drive ignne# active. r/w 12 irq1len: keyboard irq1 latch enable 0 = irq1 will bypass the latch. 1 = the active edge of irq1 will be latched and held until a port 60h read. r/w 11 irq12len: mouse irq12 latch enable 0 = irq12 will bypass the latch. 1 = the active edge of irq12 will be latched and held until a port 60h read. r/w 10:9 reserved reserved. 8 apic_en: apic enable 0 = disables internal i/o (x) apic. 1 = enables the internal i/o (x) apic and its address decode. r/w 7 reserved reserved. 6 altacc_en: alternate access mode enable 0 = alt access mode disabled (default). alt access mode allows reads to otherwise unreadable registers and writes otherwise unwritable registers. 1 = alt access mode enable. r/w 5:3 reserved reserved. table 202. offset d0h - d3h: gen_cntl?general control register (lpc i/f? d31:f0) (sheet 2 of 3) bits name description access device: 31 function: 0 offset: d0h - d3h attribute: read/write default value: 00000080h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 329 8?intel ? 6300ESB ich 8.1.23 offset d4h: gen_sta?general status (lpc i/f? d31:f0) 2 dcb_en: dma collection buffer enable 0 = dcb disabled. 1 = enables dma collection buffer (dcb) for lpc i/f and pc/ pci dma. r/w 1 dte: delayed transaction enable 0 = delayed transactions disabled. 1 = the intel ? 6300ESB ich enables delayed transactions for internal register, fwh and lpc i/f accesses. r/w 0 pos_dec_en 0 = the intel ? 6300ESB ich will perform subtractive decode on the pci bus and forward the cycles to lpc if not to an internal register or other known target on lpc. accesses to internal registers and to known lpc devices will still be positively decoded. 1 = enables intel ? 6300ESB ich to only perform positive decode on the pci bus. this must be selected when the pci to isa (subtractive docking bridge) is used. table 203. offset d4h: gen_sta?general status (lpc i/f?d31:f0) bits name description access 7:3 reserved reserved. 2safe_mode 0 = the intel ? 6300ESB ich sampled ac_sdout low on the rising edge of pwrok. 1 = the intel ? 6300ESB ich sampled ac_sdout high on the rising edge of pwrok. ro 1 no_reboot 0 = normal tco timer reboot functionality (reboot after 2nd tco timeout). this bit cannot be set to 0 by software when the strap is set to no reboot. 1 = the intel ? 6300ESB ich will disable the tco timer system reboot feature. this bit is set either by hardware when spkr is sampled high on the rising edge of pwrok, or by software writing a 1 to the bit. r/w (special) 0 reserved reserved. table 202. offset d0h - d3h: gen_cntl?general control register (lpc i/f? d31:f0) (sheet 3 of 3) bits name description access device: 31 function: 0 offset: d0h - d3h attribute: read/write default value: 00000080h size: 32-bit lockable: no power well: core device: 31 function: 0 offset: d4h attribute: read/write default value: 0xh size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 330 order number: 300641-004us 8.1.24 offset d5h: back_cntl?backed up control (lpc i/f?d31:f0) table 204. offset d5h: back_cntl?backed up control (lpc i/f?d31:f0) bits name description access 7 reserved reserved. ro 6 reserved reserved. ro 5 top_swap: top-block swap mode 0 = the intel ? 6300ESB ich will not invert a16. this bit is automatically set to 0 by rtcrst#, but not by any other type of reset. 1 = the intel ? 6300ESB ich will invert a16 for cycles going to the bios space in the fwh (but not for cycles to the feature space in the fwh). note: if the intel ? 6300ESB ich is strapped for top-swap (siu0_dtr# is low at rising edge of pwrok), then this bit cannot be cleared by software. the strap jumper should be removed and the system rebooted. r/w 4 cpu_bist_en: enables cpu bist 0 = disable. 1 = the init# signal will be driven active when cpurst# is active. init# will go inactive with the same timings as the other cpu i/f signals (hold time after cpurst# inactive). note that cpurst# is generated by the memory controller hub, but the intel ? 6300ESB ich has a hub interface special cycle that allows the intel ? 6300ESB ich to control the assertion/deassertion of cpurst#. note: this bit is in the resume well and is reset by rsmrst#, but not by pxpcirst# nor cf9h writes. r/w 3:0 freq_strap[3:0]: cpu frequency strap these bits determine the internal frequency multiplier of the processor. these bits may be reset to 1111 based on an external pin strap or through the rtcrst# input signal. software must program this field based on the processor?s specified frequency. note that this field is only writable when the safe_mode bit is cleared to zero, and safe_mode is only cleared by pwrok rising edge. these bits are in the rtc well. r/w device: 31 function: 0 offset: d5h attribute: read/write default value: 0fh (upon rtcrst# assertion low) 2fh (top_swap strap active) size: 8-bit lockable: no power well: rtc
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 331 8?intel ? 6300ESB ich 8.1.25 offset d8h: rtc_conf?rtc configuration register (lpc i/f?d31:f0) table 205. offset d8h: rtc_conf?rtc configuration register (lpc i/f? d31:f0) bits name description access 7:5 reserved reserved. 4 u128lock: upper 128- byte lock 0 = access to these bytes in the upper cmos ram range have not been locked. 1 = locks reads and writes to bytes 38h-3fh in the upper 128-byte bank of the rtc cmos ram. write cycles to this range will have no effect and read cycles will not return any particular ensured value. this is a write once register that may only be reset by a hardware reset. r/w (special) 3 l128lock: lower 128- byte lock 0 = access to these bytes in the lower cmos ram range have not been locked. 1 = locks reads and writes to bytes 38h-3fh in the lower 128-byte bank of the rtc cmos ram. write cycles to this range will have no effect and read cycles will not return any particular ensured value. this is a write once register that may only be reset by a hardware reset. r/w (special) 2 u128e: upper 128-byte enable 0 = disable. 1 = enables access to the upper 128-byte bank of rtc cmos ram. r/w 1:0 reserved reserved. device: 31 function: 0 offset: d8h attribute: read/write default value: 00h size: 8-bit lockable: yes power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 332 order number: 300641-004us 8.1.26 offset e0h: com_dec?lpc i/f communication port decode ranges (lpc i/f?d31:f0) table 206. offset e0h: com_dec?lpc i/f communication port decode ranges (lpc i/f?d31:f0) bits name description access 7 reserved reserved. 6:4 comb decode range this field determines which range to decode for the comb port. bits decode range 000 3f8h - 3ffh (com1) 001 2f8h - 2ffh (com2) 010 220h - 227h 011 228h - 22fh 100 238h - 23fh 101 2e8h - 2efh (com4) 110 338h - 33fh 111 3e8h - 3efh (com3) r/w 3 reserved reserved. 2:0 coma decode range this field determines which range to decode for the coma port. bits decode range 000 3f8h - 3ffh (com1) 001 2f8h - 2ffh (com2) 010 220h - 227h 011 228h - 22fh 100 238h - 23fh 101 2e8h - 2efh (com4) 110 338h - 33fh 111 3e8h - 3efh (com3) r/w device: 31 function: 0 offset: e0h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 333 8?intel ? 6300ESB ich 8.1.27 offset e1h: fdd/lpt_dec?lpc i/f fdd and lpt decode ranges (lpc i/f?d31:f0) table 207. offset e1h: fdd/lpt_dec?lpc i/f fdd and lpt decode ranges (lpc i/f?d31:f0) bits name description access 7:5 reserved reserved. 4 fdd decode range determines which range to decode for the fdd port 0 = 3f0h - 3f5h, 3f7h (primary) 1 = 370h - 2ffh (secondary) r/w 3:2 reserved reserved. 1:0 lpt decode range this field determines which range to decode for the lptport. 00 = 378h - 37fh and 778h - 77fh 01 = 278h - 27fh (port 279h is read only) and 678h - 67fh 10 = 3bch -3beh and 7bch - 7beh 11 = reserved r/w device: 31 function: 0 offset: e1h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 334 order number: 300641-004us 8.1.28 offset e2h: snd_dec?lpc i/f sound decode ranges (lpc i/f?d31:f0) note: this register is no longer supported and will not be validated. table 208. offset e2h: snd_dec?lpc i/f sound decode ranges (lpc i/f? d31:f0) bits name description access 7:6 reserved reserved. 5:4 mss decode range this field determines which range to decode for the microsoft* sound system (mss) 00 = 530h - 537h 01 = 604h - 60bh 10 = e80h - e87h 11 = f40h - f47h r/w 3midi decode range this bit determines which range to decode for the midi port. 0 = 330h - 331h 1 = 300h - 301h r/w 2 reserved reserved. 1:0 sb16 decode range this field determines which range to decode for the sound blaster 16 (sb16) port. 00 = 220h - 233h 01 = 240h - 253h 10 = 260h - 273h 11 = 280h - 293h r/w device: 31 function: 0 offset: e2h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 335 8?intel ? 6300ESB ich 8.1.29 offset e3h: fwh_dec_en1?fwh decode enable 1 register (lpc i/f?d31:f0) note: this register determines which memory ranges will be decoded on the pci bus and forwarded to the fwh. the intel ? 6300ESB ich will subtractively decode cycles on pci unless pos_dec_en is set to 1. table 209. offset e3h: fwh_dec_en1?fwh decode enable 1 register (lpc i/f? d31:f0) (sheet 1 of 2) bits name description access 7 fwh_f8_en enables decoding two 512 kbyte fwh memory ranges, and one 128 kbyte memory range. 0 = disable 1 = enable the following ranges for the fwh fff80000h - ffffffffh ffb80000h - ffbfffffh 000e0000h - 000fffffh ro 6 fwh_f0_en enables decoding two 512 kbyte fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh: fff00000h - fff7ffffh ffb00000h - ffb7ffffh r/w 5 fwh_e8_en enables decoding two 512 kbyte fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh: ffe80000h - ffeffffh ffa80000h - ffafffffh r/w 4 fwh_e0_en enables decoding two 512 kbyte fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh: ffe00000h - ffe7ffffh ffa00000h - ffa7ffffh r/w 3 fwh_d8_en enables decoding two 512 kbyte fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh ffd80000h - ffdfffffh ff980000h - ff9fffffh r/w device: 31 function: 0 offset: e3h attribute: read/write default value: ffh size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 336 order number: 300641-004us 8.1.30 offset e4h - e5h: gen1_dec?lpc i/f generic decode range 1 (lpc i/f?d31:f0) 2 fwh_d0_en enables decoding two 512 kbyte fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh ffd00000h - ffd7ffffh ff900000h - ff97ffffh r/w 1 fwh_c8_en enables decoding two 512 kbyte fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh ffc80000h - ffcfffffh ff880000h - ff8fffffh r/w 0 fwh_c0_en enables decoding two 512 kbyte fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh ffc00000h - ffc7ffffh ff800000h - ff87ffffh r/w table 210. offset e4h - e5h: gen1_dec?lpc i/f generic decode range 1 (lpc i/ f?d31:f0) bits name description access 15:7 gen1_base: generic i/ o decode range 1 base address this address is aligned on a 128-byte boundary, and must have address lines 31:16 as 0. note that this generic decode is for i/o addresses only, not memory addresses. the size of this range is 128 bytes. r/w 6:1 reserved reserved. 0 gen1_en: generic decode range 1 enable 0 = disable. 1 = enable the gen1 i/o range to be forwarded to the lpc i/ f. r/w table 209. offset e3h: fwh_dec_en1?fwh decode enable 1 register (lpc i/f? d31:f0) (sheet 2 of 2) bits name description access device: 31 function: 0 offset: e3h attribute: read/write default value: ffh size: 8-bit lockable: no power well: core device: 31 function: 0 offset: e4h - e5h attribute: read/write default value: 00h size: 16-bit lockable: yes power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 337 8?intel ? 6300ESB ich 8.1.31 offset e6h - e7h: lpc_en?lpc i/f enables (lpc i/f?d31:f0) table 211. offset e6h - e7h: lpc_en?lpc i/f enables (lpc i/f?d31:f0) (sheet 1 of 2) bits name description access 15:1 4 reserved reserved. 13 cnf2_lpc_en 0 = disable. 1 = enables the decoding of the i/o locations 4eh and 4fh to the lpc interface. this is used for the internal siu. r/w 12 cnf1_lpc_en 0 = disable. 1 = enables the decoding of the i/o locations 2eh and 2fh to the lpc interface. this range is used for super i/o devices. r/w 11 mc_lpc_en 0 = disable. 1 = enables the decoding of the i/o locations 62h and 66h to the lpc interface. this range is used for a microcontroller. r/w 10 kbc_lpc_en 0 = disable. 1 = enables the decoding of the i/o locations 60h and 64h to the lpc interface. this range is used for a microcontroller. r/w 9 gameh_lpc_en 0 = disable. 1 = enables the decoding of the i/o locations 208h to 20fh to the lpc interface. this range is used for a gameport. r/w 8 gamel_lpc_en 0 = disable. 1 = enables the decoding of the i/o locations 200h to 207h to the lpc interface. this range is used for a gameport. r/w 7 adlib_lpc_en 0 = disable. 1 = enables the decoding of the i/o locations 388h - 38bh to the lpc interface. note: this bit is no longer supported and will not be validated. r/w 6 mss_lpc_en 0 = disable. 1 = enables the decoding of the mss range to the lpc interface. this range is selected in the lpc_sound decode range register. note: this bit is no longer supported and will not be validated. r/w 5 midi_lpc_en 0 = disable. 1 = enables the decoding of the midi range to the lpc interface. this range is selected in the lpc_sound decode range register. note: this bit is no longer supported and will not be validated. r/w device: 31 function: 0 offset: e6h - e7h attribute: read/write default value: 0000h size: 16-bit lockable: yes power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 338 order number: 300641-004us 4 sb16_lpc_en 0 = disable. 1 = enables the decoding of the sb16 range to the lpc interface. this range is selected in the lpc_sound decode range register. note: this bit is no longer supported and will not be validated. r/w 3 fdd_lpc_en 0 = disable. 1 = enables the decoding of the fdd range to the lpc interface. this range is selected in the lpc_fdd/lpt decode range register. r/w 2 lpt_lpc_en 0 = disable. 1 = enables the decoding of the lptrange to the lpc interface. this range is selected in the lpc_fdd/lpt decode range register. r/w 1comb_lpc_en 0 = disable. 1 = enables the decoding of the comb range to the lpc interface. this range is selected in the lpc_com decode range register. r/w 0coma_lpc_en 0 = disable. 1 = enables the decoding of the coma range to the lpc interface. this range is selected in the lpc_com decode range register. r/w table 211. offset e6h - e7h: lpc_en?lpc i/f enables (lpc i/f?d31:f0) (sheet 2 of 2) bits name description access device: 31 function: 0 offset: e6h - e7h attribute: read/write default value: 0000h size: 16-bit lockable: yes power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 339 8?intel ? 6300ESB ich 8.1.32 offset e8h: fwh_sel1?fwh select 1 register (lpc i/f?d31:f0) table 212. offset e8h: fwh_sel1?fwh select 1 register (lpc i/f?d31:f0) bits name description access 31:2 8 fwh_f8_idsel idsel for two 512 kbyte fwh memory ranges and one 128 kbyte memory range. this field is fixed at 0000. the idsel programmed in this field addresses the following memory ranges: fff8 0000h - ffff ffffh ffb8 0000h - ffbf ffffh 000e 0000h - 000f ffffh ro 27:2 4 fwh_f0_idsel idsel for two 512 kbyte fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: fff0 0000h - fff7 ffffh ffb0 0000h - ffb7 ffffh r/w 23:2 0 fwh_e8_idsel idsel for two 512 kbyte fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ffe8 0000h - ffef ffffh ffa8 0000h - ffaf ffffh r/w 19:1 6 fwh_e0_idsel idsel for two 512 kbyte fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ffe0 0000h - ffe7 ffffh ffa0 0000h - ffa7 ffffh r/w 15:1 2 fwh_d8_idsel idsel for two 512 kbyte fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ffd8 0000h - ffdf ffffh ff98 0000h - ff9f ffffh r/w 11:8 fwh_d0_idsel idsel for two 512 kbyte fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ffd0 0000h - ffd7 ffffh ff90 0000h - ff97 ffffh r/w 7:4 fwh_c8_idsel idsel for two 512 kbyte fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ffc8 0000h - ffcf ffffh ff88 0000h - ff8f ffffh r/w 3:0 fwh_c0_idsel idsel for two 512 kbyte fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ffc0 0000h - ffc7 ffffh ff80 0000h - ff87 ffffh r/w device: 31 function: 0 offset: e8h attribute: read/write default value: 00112233h size: 32-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 340 order number: 300641-004us 8.1.33 offset ech - edh: gen2_dec?lpc i/f generic decode range 2 (lpc i/f?d31:f0) table 213. offset ech - edh: gen2_dec?lpc i/f generic decode range 2 (lpc i/ f?d31:f0) bits name description access 15:4 gen2_base generic i/o decode range 2 base address. this address is aligned on a 64-byte boundary, and must have address lines 31:16 as 0. note that this generic decode is for i/o addresses only, not memory addresses. the size of this range is 16 bytes. r/w 3:1 reserved reserved. read as 0. 0 gen2_en generic i/o decode range 2 enable 0 = disable. 1 = accesses to the gen2 i/o range will be forwarded to the lpc i/f. r/w device: 31 function: 0 offset: ech - edh attribute: read/write default value: 00h size: 16-bit lockable: yes power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 341 8?intel ? 6300ESB ich 8.1.34 offset eeh - efh: fwh_sel2?fwh select 2 register (lpc i/f?d31:f0) table 214. offset eeh - efh: fwh_sel2?fwh select 2 register (lpc i/f? d31:f0) bits name description access 15:1 2 fwh_70_idsel idsel for two 1m fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ff70 0000h - ff7f ffffh ff30 0000h - ff3f ffffh r/w 11:8 fwh_60_idsel idsel for two 1m fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ff60 0000h - ff6f ffffh ff20 0000h - ff2f ffffh r/w 7:4 fwh_50_idsel idsel for two 1m fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ff50 0000h - ff5f ffffh ff10 0000h - ff1f ffffh r/w 3:0 fwh_40_idsel idsel for two 1m fwh memory ranges. the idsel programmed in this field addresses the following memory ranges: ff40 0000h - ff4f ffffh ff00 0000h - ff0f ffffh r/w device: 31 function: 0 offset: eeh-efh attribute: read/write default value: 4567h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 342 order number: 300641-004us 8.1.35 offset f0h: fwh_dec_en2?fwh decode enable 2 register (lpc i/f?d31:f0) note: this register determines which memory ranges will be decoded on the pci bus and forwarded to the fwh. the intel ? 6300ESB ich will subtractively decode cycles on pci unless pos_dec_en is set to 1. table 215. offset f0h: fwh_dec_en2?fwh decode enable 2 register (lpc i/f? d31:f0) bits name description access 7:4 reserved reserved. 3 fwh_70_en enables decoding two 1m fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh ff70 0000h - ff7f ffffh ff30 0000h - ff3f ffffh r/w 2 fwh_60_en enables decoding two 1m fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh ff60 0000h - ff6f ffffh ff20 0000h - ff2f ffffh r/w 1 fwh_50_en enables decoding two 1m fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh ff50 0000h - ff5f ffffh ff10 0000h - ff1f ffffh r/w 0 fwh_40_en enables decoding two 1m fwh memory ranges. 0 = disable. 1 = enable the following ranges for the fwh ff40 0000h - ff4f ffffh ff00 0000h - ff0f ffffh r/w device: 31 function: 0 offset: f0h attribute: read/write default value: 0fh size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 343 8?intel ? 6300ESB ich 8.1.36 offset f2h: func_dis?function disable register (lpc i/f?d31:f0) note: the usb functions must be disabled from highest function number to lowest. for example, if only 2 usb host controllers are wanted, software must disable function #2. usb functions are expected to only be disabled by bios during system initialization. table 216. offset f2h: func_dis?function disable register (lpc i/f?d31:f0) (sheet 1 of 2) bits name description access 15 d29_f7_disable software sets this bit to disable the usb ehci controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = usb ehci controller is enabled 1 = usb ehci controller is disabled r/w 14:1 0 reserved reserved. 9 d29_f1_disable software sets this bit to disable the usb uhci controller #2 function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = usb uhci controller #2 is enabled 1 = usb uhci controller #2 is disabled r/w 8 d29_f0_disable software sets this bit to disable the usb uhci controller #1 function.bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = usb uhci controller #1 is enabled 1 = usb uhci controller #1 is disabled r/w 7 reserved reserved 6 d31_f6_disable software sets this bit to disable the ac?97 modem controller function. when disabled, the pci config space registers for that function are not decoded by the intel ? 6300ESB ich. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = ac?97 modem is enabled 1 = ac?97 modem is disabled r/w 5 d31_f5_disable software sets this bit to disable the ac?97 audio controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = ac?97 audio controller is enabled 1 = ac?97 audio controller is disabled r/w 4 reserved reserved. device: 31 function: 0 offset: f2h attribute: read/write default value: 0080h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 344 order number: 300641-004us 3 d31_f3_disable software sets this bit to disable the smbus host controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = smbus controller is enabled 1 = smbus controller is disabled r/w 2 d31_f2_disable software sets this bit to disable the sata controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = sata controller is enabled 1 = sata controller is disabled r/w 1 d31_f1_disable software sets this bit to disable the ide controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = ide controller is enabled 1 = ide controller is disabled r/w 0smb_for_bios this bit is used in conjunction with bit 3 in this register. 0 = no effect. 1 = allows the smbus i/o space to be accessible by software when bit 3 in this register is set. the pci configuration space is hidden in this case. note that when bit 3 is set alone, the decode of both smbus pci configuration and i/ o space will be disabled. r/w note: software must always disable all functionality within the function before disabling the configuration space. table 216. offset f2h: func_dis?function disable register (lpc i/f?d31:f0) (sheet 2 of 2) bits name description access device: 31 function: 0 offset: f2h attribute: read/write default value: 0080h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 345 8?intel ? 6300ESB ich 8.1.37 offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0) warning: make sure that reserved bits values are not modified to avoid indeterminate behavior. 8.1.38 offset f8h: manufacturer?s id table 217. offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0) bits name description access 31:8 reserved reserved. 7 trapping disable default = 0. 0 = trapping is enabled for all access to these ports. see section 5.17.9, ?usb legacy keyboard operation? for details on usb legacy keyboard operation. 1 = disable the usb legacy trapping to ports 60h and 64h when an external pci master is accessing these ports. r/w 6pxirq routing default = 0. 0 = apic1 boot interrupt is routed to irq9#. see section 5.7.3, ?boot interrupt? for details on boot interrupt. 1 = routes the apic1 boot interrupt to the pirqg# output. r/w 5:0 reserved reserved. table 218. offset f8h: manufacturer?s id bits name description access 31:1 6 reserved reserved. 15:8 manufacturer 0fh = intel 7:0 process/dot process 859.6 device: 31 function: 0 offset: f4-f7h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core device: 31 function: 0 offset: f8h-fbh attribute: read-only default value: 000s 0f66 size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 346 order number: 300641-004us 8.2 dma i/o registers table 219. dmabase_ca?dma base and current address registers (sheet 1 of 2) port alias register name/function default type 00h 10h channel 0 dma base and current address register undefined r/w 01h 11h channel 0 dma base and current count register undefined r/w 02h 12h channel 1 dma base and current address register undefined r/w 03h 13h channel 1 dma base and current count register undefined r/w 04h 14h channel 2 dma base and current address register undefined r/w 05h 15h channel 2 dma base and current count register undefined r/w 06h 16h channel 3 dma base and current address register undefined r/w 07h 17h channel 3 dma base and current count register undefined r/w 08h 18h channel 0-3 dma command register undefined wo channel 0-3 dma status register undefined ro 0ah 1ah channel 0-3 dma write single mask register 000001xxb wo 0bh 1bh channel 0-3 dma channel mode register 000000xxb wo 0ch 1ch channel 0-3 dma clear byte pointer register undefined wo 0dh 1dh channel 0-3 dma master clear register undefined wo 0eh 1eh channel 0-3 dma clear mask register undefined wo 0fh 1fh channel 0-3 dma write all mask register 0fh r/w 80h 90h reserved page register undefined r/w 81h 91h channel 2 dma memory low page register undefined r/w 82h - channel 3 dma memory low page register undefined r/w 83h 93h channel 1 dma memory low page register undefined r/w 84h - 86h 94h - 96h reserved page registers undefined r/w 87h 97h channel 0 dma memory low page register undefined r/w 88h 98h reserved page register undefined r/w 89h 99h channel 6 dma memory low page register undefined r/w 8ah 9ah channel 7 dma memory low page register undefined r/w 8bh 9bh channel 5 dma memory low page register undefined r/w 8ch - 8eh 9ch - 9eh reserved page registers undefined r/w 8fh 9fh refresh low page register undefined r/w c0h c1h channel 4 dma base and current address register undefined r/w
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 347 8?intel ? 6300ESB ich c2h c3h channel 4 dma base and current count register undefined r/w c4h c5h channel 5 dma base and current address register undefined r/w c6h c7h channel 5 dma base and current count register undefined r/w c8h c9h channel 6 dma base and current address register undefined r/w cah cbh channel 6 dma base and current count register undefined r/w cch cdh channel 7 dma base and current address register undefined r/w ceh cfh channel 7 dma base and current count register undefined r/w d0h d1h channel 4-7 dma command register undefined wo channel 4-7 dma status register undefined ro d4h d5h channel 4-7 dma write single mask register 000001xxb wo d6h d7h channel 4-7 dma channel mode register 000000xxb wo d8h d9h channel 4-7 dma clear byte pointer register undefined wo dah dbh channel 4-7 dma master clear register undefined wo dch ddh channel 4-7 dma clear mask register undefined wo deh dfh channel 4-7 dma write all mask register 0fh r/w table 219. dmabase_ca?dma base and current address registers (sheet 2 of 2) port alias register name/function default type
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 348 order number: 300641-004us 8.2.1 dmabase_ca?dma base and current address registers table 220. dmabase_ca?dma base and current address registers bits name description access 15:0 base and current address this register determines the address for the transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base address register and copied to the current address register. on reads, the value is returned from the current address register. the address increments/decrements in the current address register after each transfer, depending on the mode of the transfer. when the channel is in auto-initialize mode, the current address register will be reloaded from the base address register after a terminal count is generated. for transfers to/from a 16-bit slave (channel?s 5-7), the address is shifted left one bit location. bit 15 will be shifted into bit 16. the register is accessed in 8 bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first r/w device: 31 function: 0 i/o address: ch. #0 = 00h; ch. #1 = 02h, ch. #2 = 04h; ch. #3 = 06h, ch. #5 = c4h ch. #6 = c8h, ch. #7 = cch attribute: read-only default value: undefined size: 16-bit, accessed in two 8-bit quantities lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 349 8?intel ? 6300ESB ich 8.2.2 dmabase_cc?dma base and current count registers table 221. dmabase_cc?dma base and current count registers bits name description access 15:0 base and current count this register determines the number of transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base count register and copied to the current count register. on reads, the value is returned from the current count register. the actual number of transfers is one more than the number programmed in the base count register (i.e., programming a count of 4h results in 5 transfers). the count is decrements in the current count register after each transfer. when the value in the register rolls from zero to ffffh, a terminal count is generated. when the channel is in auto-initialize mode, the current count register will be reloaded from the base count register after a terminal count is generated. for transfers to/from an 8-bit slave (channels 0-3), the count register indicates the number of bytes to be transferred. for transfers to/from a 16-bit slave (channels 5-7), the count register indicates the number of words to be transferred. the register is accessed in 8 bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first. r/w device: 31 function: 0 i/o address: ch. #0 = 01h; ch. #1 = 03h, ch. #2 = 05h; ch. #3 = 07h, ch. #5 = c6h ch. #6 = cah, ch. #7 = ceh attribute: read/write default value: undefined size: 16-bit, accessed in two 8-bit quantities lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 350 order number: 300641-004us 8.2.3 dmamem_lp?dma memory low page registers 8.2.4 dmacmd?dma command register table 222. dmabase_cc?dma base and current count registers bits name description access 7:0 dma low page (isa address bits [23:16] this register works in conjunction with the dma controller's current address register to define the complete 24-bit address for the dma channel. this register remains static throughout the dma transfer. bit 16 of this register is ignored when in 16 bit i/o count by words mode as it is replaced by the bit 15 shifted out from the current address register. r/w table 223. dmacmd?dma command register bits name description access 7:5 reserved reserved. must be 0. 4 dma group arbitration priority each channel group is individually assigned either fixed or rotating arbitration priority. at part reset, each group is initialized in fixed priority. 0 = fixed priority to the channel group 1 = rotating priority to the group. wo 3 reserved reserved. must be zero. 2 dma channel group enable both channel groups are enabled following part reset. 0 = enable the dma channel group. 1 = disable. disabling channel group 4-7 also disables channel group 0-3, which is cascaded through channel 4. wo 1:0 reserved reserved. must be zero. device: 31 function: 0 i/o address: ch. #0 = 87h; ch. #1 = 83h, ch. #2 = 81h; ch. #3 = 82h, ch. #5 = 8bh ch. #6 = 89h, ch. #7 = 8ah attribute: read/write default value: undefined size: 8-bit lockable: no power well: core device: 31 function: 0 i/o address: ch. #0-3 = 08h ch. #4-7 = d0h attribute: write-only default value: undefined size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 351 8?intel ? 6300ESB ich 8.2.5 dmasta?dma status register table 224. dmasta?dma status register bits name description access 7:4 channel request status when a valid dma request is pending for a channel, the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware or a software request. note that channel 4 is the cascade channel, so the request status of channel 4 is a logical or of the request status for channels 0 through 3. 4 = channel 0 5 = channel 1 (5) 6 = channel 2 (6) 7 = channel 3 (7) ro 3:0 channel terminal count status when a channel reaches terminal count (tc), its status bit is set to 1. when tc has not been reached, the status bit is set to 0. channel 4 is programmed for cascade, so the tc bit response for channel 4 is irrelevant: 0 = channel 0 1 = channel 1 (5) 2 = channel 2 (6) 3 = channel 3 (7) ro device: 31 function: 0 i/o address: ch. #0-3 = 08h ch. #4-7 = d0h attribute: read-only default value: undefined size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 352 order number: 300641-004us 8.2.6 dma_wrsmsk?dma write single mask register 8.2.7 dmach_mode?dma channel mode register table 225. dma_wrsmsk?dma write single mask register bits name description access 7:3 reserved reserved. must be zero. 2 channel mask select 0 = enable dreq for the selected channel. the channel is selected through bits [1:0]. therefore, only one channel may be masked / unmasked at a time. 1 = disable dreq for the selected channel. wo 1:0 dma channel select these bits select the dma channel mode register to program. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7) wo table 226. dmach_mode?dma channel mode register (sheet 1 of 2) bits name description access 7:6 dma transfer mode each dma channel may be programmed in one of four different modes: 00 = demand mode 01 = single mode 10 = reserved 11 = cascade mode wo 5 address increment/ decrement select this bit controls address increment/decrement during dma transfers. 0 = address increment. (default after part reset or master clear) 1 = address decrement. wo device: 31 function: 0 i/o address: ch. #0-3 = 0ah ch. #4-7 = d4h attribute: write-only default value: 0000 01xx size: 8-bit lockable: no power well: core device: 31 function: 0 i/o address: ch. #0-3 = 0bh ch. #4-7 = d6h attribute: write-only default value: 0000 00xx size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 353 8?intel ? 6300ESB ich 8.2.8 dma clear byte pointer register 4 autoinitialize enable 0 = autoinitialize feature is disabled and dma transfers terminate on a terminal count. a part reset or master clear disables autoinitialization. 1 = dma restores the base address and count registers to the current registers following a terminal count (tc). wo 3:2 dma transfer type these bits represent the direction of the dma transfer. when the channel is programmed for cascade mode, (bits[7:6] = ?11?) the transfer type is irrelevant. 00 = verify - no i/o or memory strobes generated 01 = write - data transferred from the i/o devices to memory 10 = read - data transferred from memory to the i/o device 11 = illegal wo 1:0 dma channel select these bits select the dma channel mode register that will be written by bits [7:2]. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7) wo table 227. dma clear byte pointer register bits name description access 7:0 clear byte pointer no specific pattern. command enabled with a write to the i/o port address. writing to this register initializes the byte pointer flip/flop to a known state. it clears the internal latch used to address the upper or lower byte of the 16-bit address and word count registers. the latch is also cleared by part reset and by the master clear command. this command precedes the first access to a 16-bit dma controller register. the first access to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte. wo table 226. dmach_mode?dma channel mode register (sheet 2 of 2) bits name description access device: 31 function: 0 i/o address: ch. #0-3 = 0bh ch. #4-7 = d6h attribute: write-only default value: 0000 00xx size: 8-bit lockable: no power well: core device: 31 function: 0 i/o address: ch. #0-3 = 0ch ch. #4-7 = d8h attribute: write-only default value: xxxx xxxx size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 354 order number: 300641-004us 8.2.9 dma master clear register 8.2.10 dma_clmsk?dma clear mask register table 228. dma master clear register bits name description access 7:0 master clear no specific pattern. enabled with a write to the port. this has the same effect as the hardware reset. the command, status, request, and byte pointer flip/flop registers are cleared and the mask register is set. wo table 229. dma_clmsk?dma clear mask register bits name description access 7:0 clear mask register no specific pattern. command enabled with a write to the port. wo device: 31 function: 0 i/o address: ch. #0-3 = 0dh ch. #4-7 = dah attribute: write-only default value: xxxx xxxx size: 8-bit device: 31 function: 0 i/o address: ch. #0-3 = 0eh; ch. #4-7 = dch attribute: write-only default value: xxxx xxxx size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 355 8?intel ? 6300ESB ich 8.2.11 dma_wrmsk?dma write all mask register i 8.3 timer i/o registers table 230. dma_wrmsk?dma write all mask register bits name description access 7:4 reserved reserved. must be 0. 3:0 channel mask bits this register permits all four channels to be simultaneously enabled/disabled instead of enabling/disabling each channel individually, as is the case with the mask register - write single mask bit. in addition, this register has a read path to allow the status of the channel mask bits to be read. a channel's mask bit is automatically set to 1 when the current byte/word count register reaches terminal count (unless the channel is in auto-initialization mode). setting the bit(s) to a 1 disables the corresponding dreq(s). setting the bit(s) to a 0 enables the corresponding dreq(s). bits [3:0] are set to 1 upon part reset or master clear. when read, bits [3:0] indicate the dma channel [3:0] ([7:4]) mask status. bit 0 = channel 0 (4)1 = masked, 0 = not masked bit 1 = channel 1 (5)1 = masked, 0 = not masked bit 2 = channel 2 (6)1 = masked, 0 = not masked bit 3 = channel 3 (7)1 = masked, 0 = not masked note: disabling channel 4 also disables channels 0-3 due to the cascade of channel?s 0 - 3 through channel 4. r/w table 231. timer i/o registers port aliases register name/function default value type 40h 50h counter 0 interval time status byte format 0xxxxxxxb ro counter 0 counter access port register undefined r/w 41h 51h counter 1 interval time status byte format 0xxxxxxxb ro counter 1 counter access port register undefined r/w 42h 52h counter 2 interval time status byte format 0xxxxxxxb ro counter 2 counter access port register undefined r/w 43h 53h timer control word register undefined wo timer control word register read back xxxxxxx0b wo counter latch command x0h wo device: 31 function: 0 i/o address: ch. #0-3 = 0fh; ch. #4-7 = deh attribute: read/write default value: 0000 1111 size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 356 order number: 300641-004us 8.3.1 tcw ?timer control word register note: this register is programmed prior to any counter being accessed to specify counter modes. following part reset, the control words for each register are undefined and each counter output is 0. each timer must be programmed to bring it into a known state. note: there are two special commands that may be issued to the counters through this register, the read back command and the counter latch command. when these commands are chosen, several bits within this register are redefined. these register formats are described below. table 232. tcw ?timer control word register bits name description access 7:6 counter select the counter selection bits select the counter the control word acts upon as shown below. the read back command is selected when bits[7:6] are both 1. 00 = counter 0 select 01 = counter 1 select 10 = counter 2 select 11 = read back command wo 5:4 read/write select these bits are the read/write control bits. the actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb wo 3:1 counter mode selection these bits select one of six possible modes of operation for the selected counter. 000 = mode 0out signal on end of count (=0) 001 = mode 1hardware retriggerable one-shot x10 = mode 2rate generator (divide by n counter) x11 = mode 3square wave output 100 = mode 4software triggered strobe 101 = mode 5hardware triggered strobe wo 0 binary/bcd countdown select 0 = binary countdown is used. the largest possible binary count is 2 16 1 = binary coded decimal (bcd) count is used. the largest possible bcd count is 10 4 wo device: 31 function: 0 i/o address: 43h attribute: write-only default value: all bits undefined size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 357 8?intel ? 6300ESB ich 8.3.1.1 rdbk_cmd?read back command note: the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. status and/or count may be latched in any or all of the counters by selecting the counter during the register write. the count and status remain latched until read, and further latch commands are ignored until the count is read. both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to zero. when both are latched, the first read operation from that counter returns the latched status. the next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. subsequent reads return an unlatched count. 8.3.1.2 ltch_cmd?counter latch command note: the counter latch command latches the current count value. this command is used to insure that the count read from the counter is accurate. the count value is then read from each counter's count register through the counter ports access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2). the count must be read according to the programmed format, i.e., when the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). when a counter is latched once and then latched again before the count is read, the second counter latch command is ignored. table 233. rdbk_cmd?read back command bits name description access 7:6 read back command must be ?11? to select the read back command 5 latch count of selected counters. 0 = current count value of the selected counters will be latched 1 = current count will not be latched 4 latch status of selected counters. 0 = status of the selected counters will be latched 1 = status will not be latched 3 counter 2 select. 1 = counter 2 count and/or status will be latched 2 counter 1 select. 1 = counter 1 count and/or status will be latched 1 counter 0 select. 1 = counter 0 count and/or status will be latched. 0 reserved reserved. must be 0. device: 31 function: 0 attribute: read-only size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 358 order number: 300641-004us 8.3.2 sbyte_fmt?interval timer status byte format register note: each counter's status byte may be read following a read back command. when latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. the status byte returns the following: table 234. ltch_cmd?counter latch command bits name description access 7:6 counter selection these bits select the counter for latching. when ?11? is written, the write is interpreted as a read back command. 00 = counter 0 01 = counter 1 10 = counter 2 5:4 counter latch command 00 = selects the counter latch command. 3:0 reserved reserved. must be 0. device: 31 function: 0 attribute: read-only size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 359 8?intel ? 6300ESB ich table 235. sbyte_fmt?interval timer status byte format register bits name description access 7 counter out pin state 0 = out pin of the counter is also a 0. 1 = out pin of the counter is also a 1. ro 6count register status this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the counter mode, but until the count is loaded into the counting element (ce), the count value will be incorrect. 0 = count has been transferred from cr to ce and is available for reading. 1 = null count. count has not been transferred from cr to ce and is not yet available for reading. ro 5:4 read/write selection status these reflect the read/write selection made through bits[5:4] of the control register. the binary codes returned during the status read match the codes used to program the counter read/write selection. 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb ro 3:1 mode selection status these bits return the counter mode programming. the binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 = mode 0:out signal on end of count (=0) 001 = mode 1: hardware retriggerable one-shot x10 = mode 2: rate generator (divide by n counter) x11 = mode 3: square wave output 100 = mode 4: software triggered strobe 101 = mode 5: hardware triggered strobe ro 0 countdown type status this bit reflects the current countdown type. 0 = binary countdown 1 = binary coded decimal (bcd) countdown. ro device: 31 function: 0 i/o address: counter 0 = 40h, counter 1 = 41h, counter 2 = 42h attribute: read-only default value: bits[6:0] undefined, bit 7=0 size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 360 order number: 300641-004us 8.3.3 counter access ports register 8.4 8259 interrupt controller (pic) registers 8.4.1 interrupt controller i/o map the interrupt controller registers are located at 20h and 21h for the master controller (irq0 - 7), and at a0h and a1h for the slave controller (irq8 - 13). these registers have multiple functions, depending upon the data written to them. listed in the table below are descriptions of the different register possibilities for each address. table 236. counter access ports register bits name description access 7:0 counter port each counter port address is used to program the 16-bit count register. the order of programming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control register at port 43h. the counter port is also used to read the current count from the count register, and return the status of the counter programming following a read back command. r/w device: 31 function: 0 i/o address: counter 0 - 40h, counter 1 - 41h, counter 2 - 42h attribute: read/write default value: all bits undefined size: 8-bit table 237. pic registers port aliases register name/function default value type 20h 24h, 28h, 2ch, 30h, 34h, 38h, 3ch master pic icw1 init. cmd word 1 register undefined wo master pic ocw2 op ctrl word 2 register 001xxxxxb wo master pic ocw3 op ctrl word 3 register x01xxx10b r/w 21h 25h, 29h, 2dh, 31h, 35h, 39h, 3dh master pic icw2 init. cmd word 2 register undefined wo master pic icw3 init. cmd word 3 register undefined wo master pic icw4 init. cmd word 4 register 01h wo master pic ocw1 op ctrl word 1 register 00h r/w a0h a4h, a8h, ach, b0h, b4h, b8h, bch slave pic icw1 init. cmd word 1 register undefined wo slave pic ocw2 op ctrl word 2 register 001xxxxxb wo slave pic ocw3 op ctrl word 3 register x01xxx10b r/w
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 361 8?intel ? 6300ESB ich 8.4.2 icw1?initialization command word 1 register a write to initialization command word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. the interrupt mask register is cleared. 2. irq7 input is assigned priority 7. 3. the slave mode address is set to 7. 4. special mask mode is cleared and status read is set to irr. once this write occurs, the controller expects writes to icw2, icw3, and icw4 to complete the initialization sequence. a1h a5h, a9h, adh, b1h, b5h, b9h, bdh slave pic icw2 init. cmd word 2 register undefined wo slave pic icw3 init. cmd word 3 register undefined wo slave pic icw4 init. cmd word 4 register 01h wo slave pic ocw1 op ctrl word 1 register 00h r/w 4d0h - master pic edge/level triggered register 00h r/w 4d1h - slave pic edge/level triggered register 00h r/w table 237. pic registers port aliases register name/function default value type table 238. icw1?initialization command word 1 register bits name description access 7:5 icw/ocw select these bits are mcs-85 specific, and not needed. 000 = should be programmed to ?000? wo 4 icw/ocw select 1 = this bit must be a 1 to select icw1 and enable the icw2, icw3, and icw4 sequence. wo 3 edge/level bank select (ltim) disabled. replaced by the edge/level triggered control registers (elcr). wo 2adi 0 = ignored for the intel ? 6300ESB ich. should be programmed to 0. wo 1 single or cascade (sngl) 0 = must be programmed to a 0 to indicate two controllers operating in cascade mode. wo 0 icw4 write required (ic4) 1 = this bit must be programmed to a 1 to indicate that icw4 needs to be programmed. wo device: 31 function: 0 offset: master controller - 020h slave controller - 0a0h attribute: write-only default value: all bits undefined size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 362 order number: 300641-004us 8.4.3 icw2?initialization command word 2 register note: icw2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. the value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each irq on the controller. typical isa icw2 values are 08h for the master controller and 70h for the slave controller. table 239. icw2?initialization command word 2 register bits name description access 7:3 interrupt vector base address bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. wo 2:0 interrupt request level when writing icw2, these bits should all be 0. during an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. this is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second inta# cycle. the code is a three bit binary code: code master interruptslave interrupt 000 irq0 irq8 001 irq1 irq9 010 irq2 irq10 011 irq3 irq11 100 irq4 irq12 101 irq5 irq13 110 irq6 irq14 111 irq7 irq15 wo device: 31 function: 0 offset: master controller - 021h slave controller - 0a1h attribute: write-only default value: all bits undefined size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 363 8?intel ? 6300ESB ich 8.4.4 icw3?master controller initialization command word 3 register 8.4.5 icw3?slave controller initialization command word 3 register table 240. icw3?master controller initialization command word 3 register bits name description access 7:3 0 = these bits must be programmed to zero. 2 cascaded interrupt controller irq connection this bit indicates that the slave controller is cascaded on irq2. when irq8#-irq15 is asserted, it goes through the slave controller?s priority resolver. the slave controller?s intr output onto irq2. irq2 then goes through the master controller?s priority solver. when it wins, the intr signal is asserted to the processor and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1 = this bit must always be programmed to a 1. wo 1:0 0 = these bits must be programmed to zero. table 241. icw3?slave controller initialization command word 3 register bits name description access 7:3 0 = these bits must be programmed to zero. 2:0 slave identification code these bits are compared against the slave identification code broadcast by the master controller from the trailing edge of the first internal inta# pulse to the trailing edge of the second internal inta# pulse. these bits must be programmed to 02h to match the code broadcast by the master controller. when 02h is broadcast by the master controller during the inta# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. wo device: 31 function: 0 offset: 21h attribute: write-only default value: all bits undefined size: 8-bit device: 31 function: 0 offset: a1h attribute: write-only default value: all bits undefined size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 364 order number: 300641-004us 8.4.6 icw4?initialization command word 4 register 8.4.7 ocw1?operational control word 1 (interrupt mask) register table 242. icw4?initialization command word 4 register bits name description access 7:5 0 = these bits must be programmed to zero. 4 special fully nested mode (sfnm) 0 = should normally be disabled by writing a 0 to this bit. 1 = special fully nested mode is programmed. wo 3 buffered mode (buf) 0 = must be programmed to 0 for the intel ? 6300ESB ich. this is non-buffered mode. wo 2 master/slave in buffered mode not used. 0 = should always be programmed to 0. wo 1 automatic end of interrupt (aeoi) 0 = this bit should normally be programmed to 0. this is the normal end of interrupt. 1 = automatic end of interrupt (aeoi) mode is programmed. wo 0 microprocessor mode 1 = must be programmed to 1 to indicate that the controller is operating in an intel ? architecture-based system. note: programming this bit to 0 will result in improper controller operation. wo table 243. ocw1?operational control word 1 (interrupt mask) register bits name description access 7:0 interrupt request mask when a 1 is written to any bit in this register, the corresponding irq line is masked. when a 0 is written to any bit in this register, the corresponding irq mask bit is cleared, and interrupt requests will again be accepted by the controller. masking irq2 on the master controller will also mask the interrupt requests from the slave controller. r/w device: 31 function: 0 offset: master controller - 021h slave controller - 0a1h attribute: write-only default value: all bits undefined size: 8-bit device: 31 function: 0 offset: master controller - 021h slave controller - 0a1h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 365 8?intel ? 6300ESB ich 8.4.8 ocw2?operational control word 2 register note: following a part reset or icw initialization, the controller enters the fully nested mode of operation. non-specific eoi without rotation is the default. both rotation mode and specific eoi mode are disabled following initialization. table 244. ocw2?operational control word 2 register bits name description access 7:5 rotate and eoi codes (r, sl, eoi) these three bits control the rotate and end of interrupt modes and combinations of the two. 000 = rotate in auto eoi mode (clear) 001 = non-specific eoi command 010 = no operation 011 = specific eoi command 100 = rotate in auto eoi mode (set) 101 = rotate on non-specific eoi command 110 = *set priority command 111 = *rotate on specific eoi command *l0 - l2 are used wo 4:3 ocw2 select when selecting ocw2, bits 4:3 = ?00? wo 2:0 interrupt level select (l2, l1, l0) l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined below, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. bits interrupt levelbitsinterrupt level 000 irq0/8 100 irq4/12 001 irq1/9 101 irq5/13 010 irq2/10 110 irq6/14 011 i rq3/11 111 irq7/15 wo device: 31 function: 0 offset: master controller - 020h slave controller - 0a0h attribute: write-only default value: bit[4:0]=undefined, bit[7:5]=001 size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 366 order number: 300641-004us 8.4.9 ocw3?operational control word 3 register table 245. ocw3?operational control word 3 register bits name description access 7 reserved reserved. must be 0. 6 special mask mode (smm) 1 = the special mask mode may be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. bit 5, the esmm bit, must be set for this bit to have any meaning. wo 5 enable special mask mode (esmm) 0 = disable. the smm bit becomes a ?don't care?. 1 = enable the smm bit to set or reset the special mask mode. wo 4:3 ocw3 select when selecting ocw3, bits 4:3 = ?01?. wo 2poll mode command 0 = disable. poll command is not issued. 1 = enable. the next i/o read to the interrupt controller is treated as an interrupt acknowledge cycle. an encoded byte is driven onto the data bus, representing the highest priority level requesting service. wo 1:0 register read command these bits provide control for reading the in-service register (isr) and the interrupt request register (irr). when bit 1=0, bit 0 will not affect the register read selection. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. when bit 0=0, the irr will be read. when bit 0=1, the isr will be read. following icw initialization, the default ocw3 port address read will be ?read irr?. to retain the current selection (read isr or read irr), always write a 0 to bit 1 when programming this register. the selected register may be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. 00 = no action 01 = no action 10 = read irq register 11 = read is register wo device: 31 function: 0 offset: master controller - 020h slave controller - 0a0h attribute: write-only default value: bit[6,0]=0, bit[7,4:2]=undefined, bit[5,1]=1 size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 367 8?intel ? 6300ESB ich 8.4.10 elcr1?master controller edge/level triggered register note: in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the cascade channel, irq2, the heart beat timer (irq0), and the keyboard controller (irq1), cannot be put into level mode. 8.4.11 elcr2?slave controller edge/level triggered register note: in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the real time clock, irq8#, and the floating point error interrupt, irq13, cannot be programmed for level mode. table 246. elcr1?master controller edge/level triggered register bits name description access 7irq7 ecl 0 = edge. 1 = level. r/w 6irq6 ecl 0 = edge. 1 = level. r/w 5irq5 ecl 0 = edge. 1 = level. r/w 4irq4 ecl 0 = edge. 1 = level. r/w 3irq3 ecl 0 = edge. 1 = level. r/w 2:0 reserved reserved. must be 0. table 247. elcr2?slave controller edge/level triggered register (sheet 1 of 2) bits name description access 7 irq15 ecl 0 = edge. 1 = level. r/w 6 irq14 ecl 0 = edge. 1 = level. r/w 5 reserved reserved. must be 0. 4 irq12 ecl 0 = edge. 1 = level. r/w device: 31 function: 0 offset: 4d0h attribute: read-write default value: 00h size: 8-bit device: 31 function: 0 offset: 4d1h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 368 order number: 300641-004us 8.5 advanced interrupt controller (apic0) there are two apics in the intel ? 6300ESB ich: apic0 and apic1 (device29, function 5). apic0?s direct registers are assigned with base address fec0xxxxh; however, only primary (legacy) pci device may write to these registers. apic1?s direct registers are assigned with base address fec1xxxxh. to support legacy device/drivers on external pci bus used with the intel ? ichx, apic1 has an alternate base address, fec0xxxxh. this means external pci devices may write to the irq pin assertion register (either fec0_0020h or fec1_0020h) to generate interrupts from apic1. since the intel ? 6300ESB ich does not implement hub interface eoi special cycle, the mch will translate eoi special cycle to a memory write cycle to eoi register at address fec0_0040h and pass it to the intel ? 6300ESB ich. this memory write cycle will be passed to both apic0 and apic1 internally. from the cpu/mch point of view, it should always use address fec0xxxxh to access apic0 registers and address fec1xxxxh to access apic1 registers. apic1 will not respond to the cpu/mcu?s access to address fec0xxxxh, other than the eoi cycle stated above. apic0 also includes an xapic_en config bit. this bit must be set to enable the i/o (x) apic extension to the i/o apic. this allows the extended feature to be disabled if a problem is found. for apic1, this extension is always enabled. 8.5.1 apic register map the apic is accessed through an indirect addressing scheme. two registers are visible by software for manipulation of most of the apic registers. these registers are mapped into memory space and are shown in tab le 24 8 . 3irq11 ecl 0 = edge. 1 = level. r/w 2irq10 ecl 0 = edge. 1 = level. r/w 1irq9 ecl 0 = edge. 1 = level. r/w 0 reserved reserved. must be 0. table 247. elcr2?slave controller edge/level triggered register (sheet 2 of 2) bits name description access device: 31 function: 0 offset: 4d1h attribute: read/write default value: 00h size: 8-bit table 248. apic direct registers address register size type fec0_0000h index register 8 bits r/w
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 369 8?intel ? 6300ESB ich table 249 lists the registers which may be accessed within the apic through the index register. when accessing these registers, accesses must be done a dword at a time. for example, software should never access byte 2 from the data register before accessing bytes 0 and 1. the hardware will not attempt to recover from a bad programming model in this case. 8.5.2 ind?index register note: the index register will select which apic indirect register to be manipulated by software. the selector values for the indirect registers are listed in ta b le 2 49 . software will program this register to select the desired apic internal register. 8.5.3 dat?data register this is a 32-bit register specifying the data to be read or written to the register pointed to by the index register. this register may only be accessed in dword quantities. fec0_0010h data register 32 bits r/w feco_0020h irq pin assertion register 32 bits wo feco_0040h eoi register 32 bits wo table 248. apic direct registers table 249. apic indirect registers index register size type 00 id 32 bits r/w 01 version 32 bits ro 02 arbitration id 32 bits ro 03 boot configuration 32 bits r/w 03-0f reserved ro 10 -11 redirection table 0 64 bits r/w 12 - 13 redirection table 1 64 bits r/w ... ... ... ... 3e-3f redirection table 23 64 bits r/w 40-ff reserved ro table 250. ind?index register bits name description access 7:0 apic index this is an 8-bit pointer into the i/o apic register table. r/w device: 31 function: 0 offset: fec0_0000h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 370 order number: 300641-004us 8.5.4 offset fec0_0020h: irqpa?irq pin assertion register note: the irq pin assertion register is present to provide a mechanism to scale the number of interrupt inputs into the i/o apic without increasing the number of dedicated input pins. when a device that supports this interrupt assertion protocol requires interrupt service, that device will issue a write to this register. bits 4:0 written to this register contain the irq number for this interrupt. the only valid values are 0-23. bits 31:5 are ignored. to provide for future expansion, peripherals should always write a value of 0 for bits 31:5. see section 5.7.4, ?interrupt mapping? for more details on how pci devices will use this field. note: writes to this register are only allowed by the processor and by masters on the intel ? 6300ESB ich?s pci bus. writes by devices on pci buses above the intel ? 6300ESB ich are not supported. 8.5.5 offset fec0 - eoir: eoi register the eoi register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. when a write is issued to this register, the i/o apic will check the lower eight bits written to this register, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, the remote_irr bit for that i/o redirection entry will be cleared. note: this is similar to what already occurs when the apic sees the eio message on the serial bus. note that if multiple i/o redirection entries, for any reason, assign the same table 251. dat?data register bits name description access 7:0 apic data this is a 32-bit register for the data to be read or written to the apic indirect register pointed to by the index register. r/w device: 31 function: 0 offset: fec0_0010h attribute: read/write default value: 00000000h size: 32-bit table 252. offset fec0_0020h: irqpa?irq pin assertion register bits name description access 31:5 reserved reserved. to provide for future expansion, the processor should always write a value of 0 to bits 31:5. 4:0 irq number bits 4:0 written to this register contain the irq number for this interrupt. the only valid values are 0-23. wo device: 31 function: 0 offset: fec0_0020h attribute: write-only default value: n/a size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 371 8?intel ? 6300ESB ich vector for more than one interrupt input, each of those entries will have the remote_irr bit reset to zero. the interrupt which was prematurely reset will not be lost because if its input remained active when the remote_irr bit is cleared, the interrupt will be reissued and serviced at a later time. 8.5.6 offset 00h: id?identification register note: the apic id serves as a physical name of the apic. the apic bus arbitration id for the apic is derived from its i/o apic id. this register is reset to zero on power up reset. table 253. offset fec0 - eoir: eoi register bits name description access 31:8 reserved reserved. to provide for future expansion, the processor should always write a value of zero to bits 31:8. 7:0 redirection entry clear when a write is issued to this register, the i/o apic will check this field, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, the remote_irr bit for that i/o redirection entry will be cleared. wo table 254. offset 00h: id?identification register bits name description access 31:2 8 reserved reserved. 27:2 4 apic id software must program this value before using the apic. r/w 23:1 6 reserved reserved. 15 scratchpad scratchpad bit. 14:0 reserved reserved. device: 31 function: 0 offset: fec0_0040h attribute: write-only default value: n/a size: 32-bit device: 31 function: 0 offset: 00h attribute: read/write default value: 00000000h size: 16-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 372 order number: 300641-004us 8.5.7 offset 01h: ver?version register note: each i/o apic contains a hardwired version register that identifies different implementation of apic and their versions. the maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this apic. 8.5.8 offset 02h: arbid?arbitration id register note: this register contains the bus arbitration priority for the apic. when the apic clock is running, this register is loaded whenever the apic id register is loaded. a rotating priority scheme is used for apic bus arbitration. the winner of the arbitration becomes the lowest priority agent and assumes an arbitration id of zero. table 255. offset 01h: ver?version register bits name description access 31:2 4 reserved reserved. 23:1 6 maximum redirection entries this is the entry number (0 being the lowest entry) of the highest entry in the redirection table. it is equal to the number of interrupt input pins minus one and is in the range 0 through 239. in the intel ? 6300ESB ich this field is hardwired to 17h to indicate 24 interrupts. ro 15 prq this bit is set to 1 to indicate that this version of the i/o apic implements the irq assertion register and allows pci devices to write to it to cause interrupts. ro 14:8 reserved reserved. 7:0 version this is a version number that identifies the implementation version. the version number assigned to the intel ? 6300ESB ich for the i/o (x) apic is 20h. ro table 256. offset 02h: arbid?arbitration id register bits name description access 31:2 8 reserved reserved. 27:2 4 i/o apic identification this 4-bit field contains the i/o apic arbitration id. ro 23:0 reserved reserved. device: 31 function: 0 offset: 01h attribute: read-only default value: 00170020h size: 32-bit device: 31 function: 0 offset: 02h attribute: read-only default value: 00000000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 373 8?intel ? 6300ESB ich 8.5.9 offset 03h: boot_config?boot configuration register 8.5.10 offset 10h - 11h (vector 0) through 3e - 3fh (vector 23): redirection table the redirection table has a dedicated entry for each interrupt input pin. the information in the redirection table is used to translate the interrupt manifestation on the corresponding interrupt pin into an apic message. the apic will respond to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. once the interrupt is detected, a delivery status bit internally to the i/o apic is set. the state machine will step ahead and wait for an acknowledgment from the apic bus unit that the interrupt message was sent over the apic bus. only then will the i/o apic be able to recognize a new edge on that interrupt pin. that new edge will only result in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from 0 to 1. (i.e., when the interrupt was not already pending at the destination). see ta b le 25 9 for delivery mode encoding information. table 257. offset 02h: arbid?arbitration id register bits name description access 31:1 reserved reserved 0 dt: delivery type hardwire to 1. interrupt delivery mechanism is always a processor system bus message. ro device: 31 function: 0 offset: 02h attribute: read-only default value: 00000000h size: 32-bit table 258. offset 10h - 11h (vector 0) through 3e - 3fh (vector 23): redirection table (sheet 1 of 2) bits name description access 63:5 6 destination when bit 11 of this entry is 0 [physical], then bits [59:56] specify an apic id. in this case, bits 63:59 should be programmed by software to 0. when bit 11 of this entry is 1 [logical], bits [63:56] specify the logical destination address of a set of processors. r/w 55:4 8 extended destination id (edid) these bits are only sent to a local apic when in processor system bus mode. they become bits [11:4] of the address. 47:1 7 reserved reserved. software should program these bits to 0 device: 31 function: 0 offset: 10h-11h (vector 0) through 3e-3fh (vector 23) attribute: read/write default value: bit 16-1, bits[15:12]=0. all other bits undefined size: 64-bit (accessed as two 32 bit quantities)
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 374 order number: 300641-004us 16 mask 0 = not masked: an edge or level on this interrupt pin results in the delivery of the interrupt to the destination. 1 = masked: interrupts are not delivered nor held pending. setting this bit after the interrupt is accepted by a local apic has no effect on that interrupt. this behavior is identical to the device withdrawing the interrupt before it is posted to the processor. it is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local apic unit but before the interrupt is dispensed to the processor. r/w 15 trigger mode this field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = edge triggered. 1 = level triggered. r/w 14 remote irr this bit is used for level triggered interrupts (in fixed or lowest priority delivery modes only); its meaning is undefined for edge triggered interrupts. for level triggered interrupts, this bit is set if the i/o apic successfully sends the level interrupt vector in this entry. this bit is never set for smi, nmi, int or extint delivery modes. r/w 13 interrupt input pin polarity this bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = active high. 1 = active low. r/w 12 delivery status this field contains the current status of the delivery of this interrupt. writes to this bit have no effect. 0 = idle. no activity for this interrupt. 1 = pending. interrupt has been injected, but delivery is held up due to the apic bus being busy or the inability of the receiving apic unit to accept the interrupt at this time. ro 11 destination mode this field determines the interpretation of the destination field. 0 = physical. destination apic id is identified by bits [59:56]. 1 = logical. destinations are identified by matching bit [63:56] with the logical destination in the destination format register and logical destination register in each local apic. r/w 10:8 delivery mode this field specifies how the apics listed in the destination field should act upon reception of this signal. certain delivery modes will only operate as intended when used in conjunction with a specific trigger mode. these encodings are listed in the note below: r/w 7:0 vector this field contains the interrupt vector for this interrupt. values range between 10h and feh. r/w table 258. offset 10h - 11h (vector 0) through 3e - 3fh (vector 23): redirection table (sheet 2 of 2) bits name description access device: 31 function: 0 offset: 10h-11h (vector 0) through 3e-3fh (vector 23) attribute: read/write default value: bit 16-1, bits[15:12]=0. all other bits undefined size: 64-bit (accessed as two 32 bit quantities)
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 375 8?intel ? 6300ESB ich 8.6 real time clock registers 8.6.1 i/o register address map the rtc internal registers and ram are organized as two banks of 128 bytes each, called the standard and extended banks. the first 14 bytes of the standard bank contain the rtc time and date information along with four registers, a - d, that are used for configuration of the rtc. the extended bank contains a full 128 bytes of battery backed sram, and will be accessible even when the rtc module is disabled (through the rtc configuration register). registers a-d do not physically exist in the ram. all data movement between the host processor and the real-time clock is done through registers mapped to the standard i/o space. the register map appears in table 260 . table 259. delivery mode encoding bits description 000 fixed: deliver the signal on the intr signal of all processor cores listed in the destination. trigger mode may be edge or level. 001 lowest priority: deliver the signal on the intr signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. trigger mode may be edge or level. 010 smi (system management interrupt): requires the interrupt to be programmed as edge triggered. the vector information is ignored but must be programmed to all zeroes for future compatibility. -- not supported. 011 reserved 100 nmi: deliver the signal on the nmi signal of all processor cores listed in the destination. vector information is ignored. nmi is treated as an edge triggered interrupt even when it is programmed as level triggered. for proper operation this redirection table entry must be programmed to edge triggered. the nmi delivery mode does not set the rirr bit. once the interrupt is detected, it will be sent over the apic bus. when the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. once the count for the nmi pin is reached again, the interrupt will be sent over the apic bus again. -- not supported. 101 init: deliver the signal to all processor cores listed in the destination by asserting the init signal. all addressed local apics will assume their init state. init is always treated as an edge triggered interrupt even when programmed as level triggered. for proper operation this redirection table entry must be programmed to edge triggered. the init delivery mode does not set the rirr bit. once the interrupt is detected, it will be sent over the apic bus. when the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. once the count for the init pin is reached again, the interrupt will be sent over the apic bus again. -- not supported. 110 reserved. 111 extint: deliver the signal to the intr signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259a compatible interrupt controller. the inta cycle that corresponds to this extint delivery will be routed to the external controller that is expected to supply the vector. requires the interrupt to be programmed as edge triggered.
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 376 order number: 300641-004us 8.6.2 indexed registers the rtc contains two sets of indexed registers that are accessed using the two separate index and target registers (70/71h or 72/73h), as shown in table 261 . table 260. rtc i/o registers i/o locations when u128e bit = 0 function 70h and 74h also alias to 72h and 76h real-time clock (standard ram) index register note: writes to 72h, 74h and 76h do not affect the nmi enable (bit 7 of 70h) 71h and 75h also alias to 73h and 77h real-time clock (standard ram) target register 72h and 76h extended ram index register (when enabled) 73h and 77h extended ram target register (when enabled) notes: 1. i/o locations 70h and 71h are the standard isa location for the real-time clock. the map for this bank is shown in table 261 . locations 72h and 73h are for accessing the extended ram. the extended ram bank is also accessed using an indexed scheme. i/o address 72h is used as the address pointer and i/o address 73h is used as the data register. index addresses above 127h are not valid. when the extended ram is not needed, it may be disabled. 2. software must preserve the value of bit 7 at i/o addresses 70h and 74h. when writing to these addresses, software must first read the value, and then write the same value for bit 7 during the sequential address write. table 261. rtc (standard) ram bank index name 00h seconds 01h seconds alarm 02h minutes 03h minutes alarm 04h hours 05h hours alarm 06h day of week 07h day of month 08h month 09h year 0ah register a 0bh register b 0ch register c 0dh register d 0eh - 7fh 114 bytes of user ram
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 377 8?intel ? 6300ESB ich 8.6.2.1 rtc_rega?register a note: this register is used for general configuration of the rtc functions. none of the bits are affected by rsmrst# or any other intel ? 6300ESB ich reset signal. table 262. rtc_regd?register d (flag register) bits name description access 7 uip: update in progress this bit may be monitored as a status flag. 0 = the update cycle will not start for at least 492 s. the time, calendar, and alarm information in ram is always available when the uip bit is 0. 1 = the update is soon to occur or is in progress. r/w 6:4 dv[2:0]: division chain select these three bits control the divider chain for the oscillator, and are not affected by rsmrst# or any other reset signal. dv[2] corresponds to bit 6. 010 = normal operation 11x = divider reset 101 = bypass 15 stages (test mode only) 100 = bypass 10 stages (test mode only) 011 = bypass 5 stages (test mode only) 001 = invalid 000 = invalid r/w 3:0 rs[3:0] rate select selects one of 13 taps of the 15 stage divider chain. the selected tap may generate a periodic interrupt when the pie bit is set in register b. otherwise this tap will set the pf flag of register c. when the periodic interrupt is not to be used, these bits should all be set to zero. rs3 corresponds to bit 3. 0000 = interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 s 0100 = 244.141 s 0101 = 488.281 s 0110 = 976.5625 s 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms r/w device: 31 function: 0 rtc index: 0a attribute: read/write default value: undefined size: 8-bit lockable: no power well: rtc
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 378 order number: 300641-004us 8.6.2.2 rtc_regb?register b (general configuration) table 263. rtc_regb?register b (general configuration) bits name description access 7 set: update cycle inhibit enables/inhibits the update cycles. this bit is not affected by rsmrst# nor any other reset signal. 0 = update cycle occurs normally once each second. 1 = a current update cycle will abort and subsequent update cycles will not occur until set is returned to zero. when set is one, the bios may initialize time and calendar bytes safely. r/w 6 pie: periodic interrupt enable this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = allows an interrupt to occur with a time base set with the rs bits of register a. r/w 5 aie: alarm interrupt enable this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = allows an interrupt to occur when the af is set by an alarm match from the update cycle. an alarm may occur once a second, one an hour, once a day, or one a month. r/w 4 uie: update-ended interrupt enable this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = allows an interrupt to occur when the update cycle ends. r/w 3 sqwe: square wave enable this bit serves no function in the intel ? 6300ESB ich. it is left in this register bank to provide compatibility with the motorola* 146818b. the intel ? 6300ESB ich has no sqw pin. this bit is cleared by rsmrst#, but not on any other reset. r/w device: 31 function: 0 rtc index: 0bh attribute: read-write default value: u0u00uuu (u: undefined) size: 8-bit lockable: no power well: rtc
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 379 8?intel ? 6300ESB ich 2 dm: data mode specifies either binary or bcd data representation. this bit is not affected by rsmrst# nor any other reset signal. 0 = bcd 1 = binary r/w 1 hourform: hour format indicates the hour byte format. this bit is not affected by rsmrst# nor any other reset signal. 0 = twelve-hour mode. in twelve-hour mode, the seventh bit represents am as zero and pm as one. 1 = twenty-four hour mode. r/w 0 dse: daylight savings enable triggers two special hour updates per year. the days for the hour adjustment are those specified in united states federal law as of 1987, which is different than previous years. this bit is not affected by rsmrst# nor any other reset signal. 0 = daylight savings time updates do not occur. 1 = a) update on the first sunday in april, where time increments from 1:59:59 am to 3:00:00 am. b) update on the last sunday in october when the time first reaches 1:59:59 am, it is changed to 1:00:00 am. the time must increment normally for at least two update cycles (seconds) previous to these conditions for the time change to occur properly. r/w table 263. rtc_regb?register b (general configuration) bits name description access device: 31 function: 0 rtc index: 0bh attribute: read-write default value: u0u00uuu (u: undefined) size: 8-bit lockable: no power well: rtc
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 380 order number: 300641-004us 8.6.2.3 rtc_regc?register c (flag register) note: writes to register c have no effect. 8.6.3 rtc_regd?register d (flag register) table 264. rtc_regc?register c (flag register) bits name description access 7 irqf: interrupt request flag irqf = (pf * pie) + (af * aie) + (uf *ufe). this also causes the ch_irq_b signal to be asserted. this bit is cleared upon rsmrst# or a read of register c. ro 6 pf: periodic interrupt flag this bit is cleared upon rsmrst# or a read of register c. 0 = when no taps are specified through the rs bits in register a, this flag will not be set. 1 = periodic interrupt flag will be 1 whenever the tap specified by the rs bits of register a is 1. ro 5 af: alarm flag 0 = this bit is cleared upon rtcrst# or a read of register c. 1 = alarm flag will be set after all alarm values match the current time. ro 4uf: update-ended flag 0 = the bit is cleared upon rsmrst# or a read of register c. 1 = set immediately following an update cycle for each second. ro 3:0 reserved reserved. will always report 0. table 265. rtc_regd?register d (flag register) bits name description access 7 vrt: valid ram and time bit 0 = this bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1 = this bit is hard-wired to 1 in the rtc power well. r/w 6reserved reserved. this bit always returns a 0 and should be set to 0 for write cycles. 5:0 date alarm these bits store the date of month alarm value. when set to 000000b, then a ?does not care? state is assumed. the host must configure the date alarm for these bits to do anything, yet they may be written at any time. when the date alarm is not enabled, these bits will return zeros to mimic the functionality of the motorola 146818b. these bits are not affected by reset. r/w device: 31 function: 0 rtc index: 0ch attribute: read-only default value: 00u00000 (u: undefined) size: 8-bit lockable: no power well: rtc device: 31 function: 0 offset: 0dh attribute: read/write default value: 10uuuuuu (u: undefined) size: 8-bit lockable: no power well: rtc
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 381 8?intel ? 6300ESB ich 8.7 cpu interface registers 8.7.1 nmi_sc?nmi status and control register i table 266. nmi_sc?nmi status and control register bits name description access 7 serr#_nmi_sts: serr# nmi source status 1 = pci agent detected a system error and pulses the pci serr# line. this interrupt source is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 1 and then set it to 0. when writing to port 61h, this bit must be 0. ro 6 iochk_nmi_sts: iochk# nmi source status 1 = an isa agent (through serirq) asserted iochk# on the isa bus. this interrupt source is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 0 and then set it to 1. when writing to port 61h, this bit must be a 0. ro 5 tmr2_out_sts: timer counter 2 out status this bit reflects the current state of the 8254 counter 2 output. counter 2 must be programmed following any pci reset for this bit to have a determinate value. when writing to port 61h, this bit must be a 0. ro 4 ref_toggle: refresh cycle toggle this signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. when writing to port 61h, this bit must be a 0. ro 3 iochk_nmi_en: iochk# nmi enable 0 = enabled. 1 = disabled and cleared. r/w 2 pci_serr_en: pci serr# enable 0 = serr# nmis are enabled. 1 = serr# nmis are disabled and cleared. r/w 1 spkr_dat_en: speaker data enable 0 = spkr output is a 0. 1 = spkr output is equivalent to the counter 2 out signal value. r/w 0 tim_cnt2_en: timer counter 2 enable 0 = disable 1 = enable r/w device: 31 function: 0 offset: 61h attribute: read/write, read-only default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 382 order number: 300641-004us 8.7.2 nmi_en?nmi enable (and real time clock index) note: the rtc index field is write-only for normal operation. this field may only be read in alt-access mode. this register is aliased to port 74h, and all bits are readable at that address. 8.7.3 port92?fast a20 and init register table 267. nmi_en?nmi enable (and real time clock index) bits name description access 7 nmi_en: nmi enable 0 = enable nmi sources. 1 = disable all nmi sources. r/w 6:0 rtc_indx: real time clock index address this data goes to the rtc to select which register or cmos ram address is being accessed. r/w table 268. port92?fast a20 and init register bits name description access 7:2 reserved reserved. 1 alt_a20_gate: alternate a20 gate this bit is ored with the a20gate input signal to generate a20m# to the processor. 0 = a20m# signal may potentially go active. 1 = this bit is set when init# goes active. r/w 0 init_now when this bit transitions from a 0 to a 1, the intel ? 6300ESB ich will force init# active for 16 pci clocks. r/w device: 31 function: 0 i/o address: 70h attribute: read/write (special) default value: 80h size: 8-bit lockable: no power well: core device: 31 function: 0 i/o address: 92h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 383 8?intel ? 6300ESB ich 8.7.4 coproc_err?coprocessor error register 8.7.5 rst_cnt?reset control register table 269. coproc_err?coprocessor error register bits name description access 7:0 coproc_err any value written to this register will cause ignne# to go active, if ferr# had generated an internal irq13. for ferr# to generate an internal irq13, the coproc_err_en bit (device 31:function 0, offset d0, bit 13) must be 1. wo table 270. rst_cnt?reset control register bits name description access 7:4 reserved reserved. 3 full_rst: full reset this bit is used to determine the states of slp_s3#, slp_s4# and slp_s5# after a cf9 hard reset (sys_rst =1 and rst_cpu is set to 1), after pwrok going low (with rsmrst# high), or after two tco timeouts. 0 = the intel ? 6300ESB ich will keep slp_s3#, slp_s4# and slp_s5# high. 1 = the intel ? 6300ESB ich will drive slp_s3#, slp_s4# and slp_s5# low for 3 - 5 seconds. r/w 2rst_cpu: reset cpu when this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the sys_rst bit (bit 1 of this register). r/w 1sys_rst: system reset this bit is used to determine a hard or soft reset to the processor. 0 = when rst_cpu bit goes from 0 to 1, the intel ? 6300ESB ich performs a soft reset by activating init# for 16 pci clocks. 1 = when rst_cpu bit goes from 0 to 1, the intel ? 6300ESB ich performs a hard reset by activating pxpcirst# for 1 millisecond. it also resets the resume well bits (except for those noted throughout the datasheet). the slp_s3#, slp_s4#, and slp_s5# signals will not go active. r/w 0 reserved reserved. device: 31 function: 0 i/o address: f0h attribute: read-only default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 0 offset: cf9h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 384 order number: 300641-004us 8.8 power management registers (d31:f0) the power management registers are distributed within the pci device 31: function 0 space, as well as a separate i/o range. each register is described below. unless otherwise indicate, bits are in the main (core) power well. bits not explicitly defined in each register are assumed to be reserved. when writing to a reserved bit, the value should always be 0. software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0. 8.8.1 power management pci configuration registers (d31:f0) table 271 shows a small part of the configuration space for pci device 31: function 0. it includes only those registers dedicated for power management. some of the registers are only used for legacy power management schemes. table 271. power management pci configuration registers (d31:f0) offset mnemonic register name/function default type 40h-43h acpi_base acpi base address 00000001 h r/w 44h acpi_cntl acpi control 00h r/w a0h gen_pmcon_1 general power management configuration 1 0000h r/w a2h gen_pmcon_2 general power management configuration 2 00h r/w a4h gen_pmcon_3 general power management configuration 3 00h r/w a8h reserved 0dh r/w b8 - bbh gpi_rout gpi route control 00000000 h r/w c0h mon_fwd_en i/o monitor forward enable 00h rw c4 - cahh mon[ n ]_trp_rng i/o monitor[4:7] trap range 0000h r/w cch mon_trp_msk i/o monitor trap range mask 0000h r/w
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 385 8?intel ? 6300ESB ich 8.8.1.1 offset a0h: gen_pmcon_1?general pm configuration 1 register (pm?d31:f0) note: usage: acpi or legacy. table 272. offset a0h: gen_pmcon_1?general pm configuration 1 register (pm?d31:f0) bits name description access 15:1 1 reserved reserved. 10 reserved reserved. 9pwrbtn_lvl this read-only bit indicates the current state of the pwrbtn# signal. 0 = low. 1 = high. ro 8:6 reserved reserved. 5 cpuslp_en: cpu slp# enable 0 = disable. 1 = enables the cpuslp# signal to go active in the s1-d states. this reduces the processor power. note that cpuslp# will go active on entry to s3, s4 and s5 even when this bit is not set. r/w 4smi_lock when this bit is set, writes to the glb_smi_en bit will have no effect once the smi_lock bit is set, writes of 0 to smi_lock bit will have no effect (i.e. once set, this bit may only be cleared by pxpcirst#). r/wo 3:2 reserved reserved. 1:0 per_smi_sel: periodic smi# rate select set by software to control the rate at which periodic smi# is generated. 00 = 64 seconds 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds r/w device: 31 function: 0 offset: a0h attribute: read/write default value: 00h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 386 order number: 300641-004us 8.8.1.2 offset a2h: gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) note: usage: acpi or legacy. table 273. offset a2h: gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) bits name description access 7:5 reserved reserved. 4 system reset status (srs) the intel ? 6300ESB ich sets this bit when the sys_reset# button is pressed. bios is expected to read this bit and clear it when it is set. this bit is also reset by rsmrst# and cf9h resets. srs bit is set only when the system is in s0 or s1 state. r/wc 3 cpu thermal trip status (cts) this bit is set when pxpcirst# is inactive and cputhrmtrip# goes active while the system is in an s0 or s1 state. this bit is also reset by rsmrst# and cf9h resets. it is not reset by the shutdown and reboot associated with the cputhrmtrip# event. r/wc 2 reserved reserved. 1 cpupwr_flr: cpu power failure 0 = software clears this bit by writing a 0 to the bit position. 1 = indicates that the pwrgd signal from the cpu?s vrm went low. software clears this bit by writing a 0 to this bit position. r/wc 0 pwrok_flr: pwrok failure 0 = software clears this bit by writing a 1 to the bit position, or when the system goes into a g3 state. 1 = this bit will be set any time pwrok goes low, when the system was in s0, or s1 state. the bit will be cleared only by software by writing a 1 to this bit or when the system goes to a g3 state. note: traditional designs have a reset button logically or?d with the pwrok signal from the power supply and the cpu?s voltage regulator module. when this is done with the intel ? 6300ESB ich, the pwrok_flr bit will be set. the intel ? 6300ESB ich treats this internally as though the rsmrst# signal had gone active. however, it is not treated as a full power failure. when pwrok goes inactive and then active (but rsmrst# stays high), the intel ? 6300ESB ich will reboot (regardless of the state of the afterg3 bit). when the rsmrst# signal also goes low before pwrok goes high, this is a full power failure and the reboot policy is controlled by the afterg3 bit. note: in the case of true pwrok failure, pwrok will go low first before pwrgd. r/wc device: 31 function: 0 offset: a2h attribute: read-only clear default value: 00h size: 8-bit lockable: no power well: resume
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 387 8?intel ? 6300ESB ich 8.8.1.3 offset a4h: gen_pmcon_3?general pm configuration 3 register (pm?d31:f0) note: usage: acpi or legacy. table 274. offset a4h: gen_pmcon_3?general pm configuration 3 register (pm?d31:f0) bits name description access 7:6 swsmi_rate_sel this 2-bit value indicates when the swsmi timer will time out. valid values are: 00 1.5 ms 0.5 ms 01 16 ms 4 ms 10 32 ms 4 ms 11 64 ms 4 ms r/w 5:3 reserved reserved. 2 rtc_pwr_sts: rtc power status this bit is set when rtcrst# is low. the bit is not cleared by any type of reset. r/w 1pwr_flr: power failure this bit is in the rtc well, and is not cleared by any type of reset except rtcrst#. 0 = indicates that the trickle current has not failed since the last time the bit was cleared. software clears this bit by writing a 1 to the bit position. 1 = indicates that the trickle current (from the main battery or trickle supply) was removed or failed. note: clearing cmos in a processor-based platform may be done by using a jumper on rtcrst# or gpi, or using safemode strap. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. r/wc 0 afterg3_en determines what state to go to when power is re-applied after a power failure (g3 state). this bit is in the rtc well and is not cleared by any type of reset except writes to cf9h or rtcrst#. 0 = system will return to s0 state (boot) after power is re- applied. 1 = system will return to the s5 state (except when it was in s4, in which case it will return to s4). in the s5 state, the only enabled wake event is the power button or any enabled wake event that was preserved through the power failure. r/w note: rsmrst# is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the intel ? 6300ESB ich. device: 31 function: 0 offset: a4h attribute: read/write default value: 00h size: 8-bit lockable: no power well: rtc
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 388 order number: 300641-004us 8.8.1.4 offset ach: rst_cnt2?reset control 2 register (pm? d31:f0) table 275. offset ach: rst_cnt2?reset control 2 register (pm?d31:f0) bits name description access 31:2 4 reserved reserved. 23 change sub class code (cscc) when set, the sub class code for the sata controller will report the value of ?04h?, a raid device. when cleared, the sub class code for the sata controller will report the value of ?01h?, an ide controller. this bit is in the resume well and is not reset when returning from s3. 22 change device id (cdid) when set, the device id for the sata controller will report the value of ?25b0h?(raid). when cleared, the device id for the sata controller will report the value of ?25a3h?(hard drive). this bit is in the resume well and is not reset when returning from s3. 21:1 9 reserved reserved. 18 cworwre - cf9 without resume well reset enable 1 = cf9h write of 6h or eh will not cause internal resume well reset to be asserted and thus resume well logic will maintain to their states. 0 = cf9h write of 6h or eh will reset resume well logic, r/w 17:1 6 programmable cputhrmtrip# behavior (pctb) this field selects the handling of cputhrmtrip# event by the intel ? 6300ESB ich internal logic. bits cputhrmtrip# behavior 00 cputhrmtrip# event will cause asynchronous assertion of slps3#, slps4#, slps5# and immediate transition to s5 01 cputhrmtrip# event will be double-synchronized to rtcclks before causing assertion of slps3#, slps4#,slps5# and entry to s5 10 cputhrmtrip event will cause asynchronous assertion of slps3#, slps4# and slps5#. however, internal entry to s5 is delayed until synchronization with rtcclk 11 reserved. 15:0 reserved reserved. device: 31 function: 0 offset: ach attribute: read/write default value: 00000000h size: 32-bit power well: resume
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 389 8?intel ? 6300ESB ich 8.8.1.5 offset b8h - bbh: gpi_rout?gpi routing control register (pm?d31:f0) table 276. offset b8h - bbh: gpi_rout?gpi routing control register (pm? d31:f0) bits name description access 31:2 gpi[15] through gpi[1] see bits 1:0 for description. 1:0 gpi0 route gpio[15:0] may be routed to cause an smi or sci when the gpi[n]_sts bit is set. when the gpio is not set to an input, this field has no effect. when the system is in an s1-s5 state and if the gpe0_en bit is also set, the gpi may cause a wake event, even if the gpi is not routed to cause an smi# or sci. exception: if the system is in s5 state due to a powerbutton override, then the gpis will not cause wake events, 00 = no effect. 01 = smi# (when corresponding alt_gp_smi_en bit is also set) 10 = sci (when corresponding gpe0_en bit is also set) 11 = reserved r/w device: 31 function: 0 offset: b8h - bbh attribute: read/write default value: 0000h size: 32-bit lockable: no power well: resume
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 390 order number: 300641-004us 8.8.1.6 offset c0h: mon_fwd_en?io monitor forward enable register (pm?d31:f0) note: usage: legacy only. note: the intel ? 6300ESB ich uses this register to enable the monitors to forward cycles to lpc, independent of the pos_dec_en bit and the bits that enable the monitor to generate an smi#. the only criteria is that the address passes the decoding logic as determined by the mon[ n ]_trp_rng and mon_trp_msk register settings. 8.8.1.7 offset c4h, c6h, c8h, cah: mon[ n ]_trp_rng?i/o monitor [4:7] trap range register for devices 4-7 (pm?d31:f0) note: usage: legacy only. these registers set the ranges that device monitors 4-7 should trap. offset c4h corresponds to monitor 4. offset c6h corresponds to monitor 5, etc. when the trap is enabled in the mon_smi register and the address is in the trap range (and passes the mask set in the mon_trp_msk register) the intel ? 6300ESB ich will generate an smi#. this smi# occurs when the address is positively decoded by another device on pci or by the intel ? 6300ESB ich (because it would be forwarded to lpc or some other intel ? 6300ESB ich internal registers). the trap ranges should not point to registers in the intel ? 6300ESB ich?s internal ide, usb, ac?97. when the cycle is to be claimed by the intel ? 6300ESB ich and targets one of the permitted intel ? 6300ESB ich internal registers (interrupt controller, rtc, etc.), the cycle will complete table 277. offset c0h: mon_fwd_en?io monitor forward enable register (pm? d31:f0) bits name description access 7 mon7_fwd_en 0 = disable. cycles trapped by i/o monitor 7 will not be forwarded to lpc. 1 = enable. cycles trapped by i/o monitor 7 will be forwarded to lpc. r/w 6 mon6_fwd_en 0 = disable. cycles trapped by i/o monitor 6 will not be forwarded to lpc. 1 = enable. cycles trapped by i/o monitor 6 will be forwarded to lpc. r/w 5 mon5_fwd_en 0 = disable. cycles trapped by i/o monitor 5 will not be forwarded to lpc. 1 = enable. cycles trapped by i/o monitor 5 will be forwarded to lpc. r/w 4 mon4_fwd_en 0 = disable. cycles trapped by i/o monitor 4 will not be forwarded to lpc. 1 = enable. cycles trapped by i/o monitor 4 will be forwarded to lpc. r/w 3:0 reserved reserved. device: 31 function: 0 offset: c0h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 391 8?intel ? 6300ESB ich to the intended target and an smi# will be generated (this is the same functionality as the intel ? 6300ESB ich component). when the cycle is to be claimed by the intel ? 6300ESB ich and the intended target is on lpc, an smi# will be generated but the cycle will only be forwarded to the intended target when forwarding to lpc is enabled through the trp_fwd_en register settings. 8.8.1.8 offset cch: mon_trp_msk?i/o monitor trap range mask register for devices 4-7 (pm?d31:f0) note: usage: legacy only. table 278. offset c4h, c6h, c8h, cah: mon[n]_trp_rng?i/o monitor [4:7] trap range register for devices 4-7 (pm?d31:f0) bits name description access 15:0 mon[ n ]_trap_base base i/o locations that mon[ n ] traps (where n = 4, 5, 6 or 7). the range may be mapped anywhere in the cpu i/o space (0-64k). any access to the range will generate an smi# when enabled by the associated dev[ n ]_trap_en bit in the mon_smi register (pmbase +40h). r/w table 279. offset cch: mon_trp_msk?i/o monitor trap range mask register for devices 4-7 (pm?d31:f0) bits name description access 15:1 2 mon7_mask selects low 4-bit mask for the i/o locations that mon7 will trap. similar to mon4_mask. r/w 11:8 mon6_mask selects low 4-bit mask for the i/o locations that mon6 will trap. similar to mon4_mask. r/w 7:4 mon5_mask selects low 4-bit mask for the i/o locations that mon5 will trap. similar to mon4_mask. r/w 3:0 mon4_mask selects low 4-bit mask for the i/o locations that mon7 will trap. when a mask bit is set to a 1, the corresponding bit in the base i/o selection will not be decoded. for example, if mon4_trap_base = 1230h, and mon4_msk = 0100b, the intel ? 6300ESB ich will decode 1230h and 1234h for monitor 4. r/w device: 31 function: 0 offset: c4h, c6h, c8h, cah attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core device: 31 function: 0 offset: cch attribute: read/write default value: 00h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 392 order number: 300641-004us 8.8.2 apm i/o decode table 280 shows the i/o registers associated with apm support. this register space is enabled in the pci device 31: function 0 space (apmdec_en), and cannot be moved (fixed i/o location). 8.8.2.1 apm_cnt?advanced power management control port register note: usage: legacy only. 8.8.2.2 apm_sts?advanced power management status port register note: usage: legacy only. table 280. apm register map address mnemonic register name/function default type b2h apm_cnt advanced power management control port 00h r/w b3h apm_sts advanced power management status port 00h r/w table 281. apm_cnt?advanced power management control port register bits name description access 7:0 used to pass an apm command between the os and the smi handler. writes to this port not only store data in the apmc register, but also generates an smi# when the apmc_en bit is set. table 282. apm_sts?advanced power management status port register bits name description access 7:0 used to pass data between the os and the smi handler. basically, this is a scratchpad register and is not affected by any other register or function (other than a pci reset). device: 31 function: 0 i/o address: b2h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 0 i/o address: b3h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 393 8?intel ? 6300ESB ich 8.8.3 power management i/o registers table 283 shows the registers associated with acpi and legacy power management support. these registers are enabled in the pci device 31: function 0 space (pm_io_en), and may be moved to any i/o location (128-byte aligned). the registers are defined to be compliant with the acpi 1.0 specification, and use the same bit names. note: all reserved bits and registers will always return zero when read and will have no effect when written. table 283. acpi and legacy i/o register map pmbase+ offset register name acpi pointer default attributes 00-01h pm1 status pm1a_evt_blk 0000h r/w 02-03h pm1 enable pm1a_evt_blk+2 0000h r/w 04-07h pm1 control pm1a_cnt_blk 00000000h r/w 08-0bh pm1 timer pmtmr_blk 00000000h ro 10h-13h processor control p_blk 00000000h r/w 14h level 2 register p_blk+4 00h ro 28-2bh general purpose event 0 status gpe0_blk 00000000h r/w 2c-2fh general purpose event 0 enables gpe0_blk+4 00000000h r/w 30-33h smi# control and enable 00000000h r/w 34-37h smi status register 00000000h r/w 38-39h alternate gpi smi enable 0000h r/w 3a-3bh alternate gpi smi status 0000h r/wc 40h device monitor smi status and enable 0000h r/w 44h device activity status 0000h r/w 48h device trap enable register 0000h r/w 4ch-4dh bus address tracker last cycle ro 4eh bus cycle tracker last cycle ro 60h-7fh reserved for tco registers
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 394 order number: 300641-004us 8.8.3.1 pm1_sts?power management 1 status register note: usage: acpi or legacy note: when bit 10 or 8 in this register is set, and the corresponding _en bit is set in the pm1_en register, the intel ? 6300ESB ich will generate a wake event. once back in an s0 state (or if already in an s0 state when the event occurs), the intel ? 6300ESB ich will also generate an sci when the sci_en bit is set, or an smi# when the sci_en bit is not set. note: bit 5 does not cause an smi# or a wake event. bit 0 does not cause a wake event but may cause an smi# or sci. table 284. pm1_sts?power management 1 status register (sheet 1 of 2) bits name description access 15 wak_sts: wake status this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware when the system is in one of the sleep states (through the slp_en bit) and an enabled wake event occurs. upon setting this bit, the intel ? 6300ESB ich will transition the system to the on state. when the afterg3_en bit is not set and a power failure (such as removed batteries) occurs without the slp_en bit set, the system will return to an s0 state when power returns, and the wak_sts bit will not be set. when the afterg3_en bit is set and a power failure occurs without the slp_en bit having been set, the system will go into an s5 state when power returns, and a subsequent wake event will cause the wak_sts bit to be set. note that any subsequent wake event would have to be caused by either a power button press, or an enabled wake event that was preserved through the power failure (enable bit in the rtc well). r/wc 14:1 2 reserved reserved. 11 prbtnor_sts: power button override status this bit is set any time a power button override occurs (i.e. the power button is pressed for at least four consecutive seconds), or due to the corresponding bit in the smbus slave message. the power button override causes an unconditional transition to the s5 state, as well as sets the afterg3 bit. the bios or sci handler clears this bit by writing a 1 to it. this bit is not affected by hard resets through cf9h writes, and is not reset by rsmrst#. thus, this bit is preserved through power failures. r/wc device: 31 function: 0 i/o address: pmbase + 00h (acpi pm1a_evt_blk) attribute: read/write clear default value: 0000h size: 16-bit lockable: no power well: bits 0-7: core; bits 8-10, 12-15;resume; bit 11: rtc
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 395 8?intel ? 6300ESB ich 10 rtc_sts: rtc status this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware when the rtc generates an alarm (assertion of the irq8# signal). additionally when the rtc_en bit is set, the setting of the rtc_sts bit will generate a wake event. r/wc 9 reserved reserved. 8 pwrbtn__sts: power button status this bit is not affected by hard resets caused by a cf9 write. 0 = when the pwrbtn# signal is held low for more than four seconds, the hardware clears the pwrbtn_sts bit, sets the pwrbtnor_sts bit, and the system transitions to the s5 state with only pwrbtn# enabled as a wake event. this bit may be cleared by software by writing a one to the bit position. 1 = this bit is set when the pwrbtn# signal is asserted (low), independent of any other enable bit. see pwrbtn_en for the effect when pwrbtn_sts goes active. pwrbtn_sts is always a wake event. this bit is only set by hardware and can be cleared by software writing a one to this bit position. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. r/wc 7:6 reserved reserved. 5gbl _sts: global status 0 = the sci handler should then clear this bit by writing a 1 to the bit location. 1 = set when an sci is generated due to bios wanting the attention of the sci handler. bios has a corresponding bit, bios_rls, which will cause an sci and set this bit. r/wc 4:1 reserved reserved. 0 tmrof_sts: timer overflow status 0 = the sci or smi# handler clears this bit by writing a 1 to the bit location. 1 = this bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). this will occur every 2.3435 seconds. when the tmrof_en bit is set, then the setting of the tmrof_sts bit will additionally generate an sci or smi# (depending on the sci_en). r/wc table 284. pm1_sts?power management 1 status register (sheet 2 of 2) bits name description access device: 31 function: 0 i/o address: pmbase + 00h (acpi pm1a_evt_blk) attribute: read/write clear default value: 0000h size: 16-bit lockable: no power well: bits 0-7: core; bits 8-10, 12-15;resume; bit 11: rtc
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 396 order number: 300641-004us 8.8.3.2 pm1_en?power management 1 enable register note: usage: acpi or legacy. table 285. pm1_en?power management 1 enable register bits name description access 15:1 1 reserved reserved. 10 rtc_en: rtc event enable this bit is in the rtc well to allow an rtc event to wake after a power failure. this bit is not cleared by any reset other than rtcrst# or a power button override event. 0 = no sci (or smi#) or wake event is generated then rtc_sts goes active. 1 = an sci (or smi#) and a wake event will occur when this bit is set and the rtc_sts bit goes active. r/w 9 reserved reserved. 8pwrbtn_en this bit is the power button enable. it works in conjunction with the sci_en bit: pwrbtn_en sci_en effect when pwrbtn_sts is set 0 x no smi# or sci 10smi# 11sci pwrbtn_en has no effect on the pwrbtn_sts bit being set by the assertion of the power button. the power button is always enabled as a wake event. 7:6 reserved reserved. 5 gbl_en: global enable when both the gbl_en and the gbl_sts are set, an sci is raised. disable. enable sci on gbl_sts going active. r/w 4:1 reserved reserved. 0 tmrof_en. timer overflow interrupt enable works in conjunction with the sci_en bit as described below: tmrof_en sci_en effect when tmrof_sts is set 0 x no smi# or sc. if system was in s1- s5, no wake event 1 0 smi# if system was in s1-s5, then a wake vent occurs before the smi# 1 1 sci if system was in s1-s5, then a wake vent occurs before the smi# r/w device: 31 function: 0 i/o address: pmbase + 02h (acpi pm1a_evt_blk + 2) attribute: read/write default value: 0000h size: 16-bit lockable: no power well: bits 0-7: core bits 8-9, 11-15: resume bit 10: rtc
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 397 8?intel ? 6300ESB ich 8.8.3.3 pm1_cnt?power management 1 control note: usage: acpi or legacy. table 286. pm1_cnt?power management 1 control bits name description access 31:1 4 reserved reserved. 13 slp_en: sleep enable setting this bit causes the system to sequence into the sleep state defined by the slp_typ field. wo 12:1 0 slp_typ: sleep type this 3-bit field defines the type of sleep the system should enter when the slp_en bit is set to 1. 000 = on: typically maps to s0 state. 001 = asserts stpclk#. puts cpu in stop-grant state. optional to assert cpuslp# to put cpu in sleep state: typically maps to s1 state. 010 = reserved 011 = reserved 100 = reserved 101 = suspend-to-ram. assert slp_s1# and slp_s3#: typically maps to s3 state. 110 = suspend-to-disk. assert slp_s1#, slp_s3#, and slp_s4#: typically maps to s4 state. 111 = soft off. assert slp_s1#, slp_s3#, slp_s4#, and slp_s5#: typically maps to s5 state. note: these bits are only reset by rtcrst#. r/w 9:3 reserved reserved. 2 gbl_rls: global release 0 = this bit always reads as 0. 1 = acpi software writes a 1 to this bit to raise an event to the bios. bios software has a corresponding enable and status bits to control its ability to receive acpi events. wo 1 reserved reserved. 0sci_en: sci enable selects the sci interrupt or the smi# interrupt for various events including the bits in the pm1_sts register (bit 10, 8, 0), and bits in gpe0_sts. 0 = these events will generate an smi#. 1 = these events will generate an sci. r/w device: 31 function: 0 i/o address: pmbase + 04h (acpi pm1a_cnt_blk) attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: bits 0-7: core, bits 8-12: rtc bits 13-15: resume
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 398 order number: 300641-004us 8.8.3.4 pm1_tmr?power management 1 timer register note: usage: acpi only. 8.8.3.5 proc_cnt?processor control register note: usage: acpi or legacy. table 287. pm1_tmr?power management 1 timer register bits name description access 31:2 4 reserved reserved. 23:0 tmr_val: timer value returns the running count of the pm timer. this counter runs off a 3.579545 mhz clock (14.31818 mhz divided by 4). it is reset to zero during a pci reset, and then continues counting as long as the system is in the s0 state. anytime bit 22 of the timer goes high to low (bits referenced from 0 to 23), the tmrof_sts bit is set. the high-to-low transition will occur every 2.3435 seconds. when the tmrof_en bit is set, an sci interrupt is also generated. ro table 288. proc_cnt?processor control register (sheet 1 of 2) bits name description access 31:1 8 reserved reserved. 17 thtl_sts: throttle status 0 = no clock throttling is occurring (maximum processor performance). 1 = indicates that the clock state machine is in some type of low power state (where the processor is not running at its maximum performance): thermal throttling or hardware throttling. ro 16:9 reserved reserved. 8 force_thtl: force thermal throttling software may set this bit to force the thermal throttling function. this has the same effect as the thrm# signal being active for 2 seconds. 0 = no forced throttling. 1 = throttling at the duty cycle specified in thrm_dty starts immediately (no 2 second delay), and no smi# is generated. r/w device: 31 function: 0 i/o address: pmbase + 08h (acpi pmtmr_blk) attribute: read-only default value: 00000000h size: 32-bit lockable: no power well: core device: 31 function: 0 i/o address: pmbase + 10h (acpi p_blk) attribute: read/write default value: 00000000h size: 32-bit lockable: no (bits 7:5 are write once) power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 399 8?intel ? 6300ESB ich 7:5 thrm_dty this write-once 3-bit field determines the duty cycle of the throttling when the thermal override condition occurs. the duty cycle indicates the approximate percentage of time the stpclk# signal is asserted while in the throttle mode. the stpclk# throttle period is 1024 pciclks. note that the throttling only occurs when the system is in the c0 state. when in the c2 state, no throttling occurs. there is no enable bit for thermal throttling, because it should not be disabled. once the thrm_dty field is written, any subsequent writes will have no effect until pxpcirst# goes active. thrm_dty throttle modepci clocks 000 50% default 512 001 87.5% 896 010 75.0% 768 011 62.5% 640 100 50% 512 101 37.5% 384 110 25% 256 111 12. 5% 128 4thtl_en when set and the system is in a c0 state, it enables a processor-controlled stpclk# throttling. the duty cycle is selected in the thtl_dty field. 0 = disable 1 = enable 3:1 thtl_dty this 3-bit field determines the duty cycle of the throttling when the thtl_en bit is set. the duty cycle indicates the approximate percentage of time the stpclk# signal is asserted (low) while in the throttle mode. the stpclk# throttle period is 1024 pciclks. thrm_dty throttle modepci clocks 000 50% default 512 001 87.5% 896 010 75.0% 768 011 62.5% 640 100 50% 512 101 37.5% 384 110 25% 256 111 12. 5% 128 0 reserved reserved. table 288. proc_cnt?processor control register (sheet 2 of 2) bits name description access device: 31 function: 0 i/o address: pmbase + 10h (acpi p_blk) attribute: read/write default value: 00000000h size: 32-bit lockable: no (bits 7:5 are write once) power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 400 order number: 300641-004us 8.8.3.6 lv2?level 2 register note: usage: acpi or legacy. 8.8.3.7 gpe0_sts?general purpose event 0 status register note: this register is symmetrical to the general purpose event 0 enable register. when the corresponding _en bit is set, and the _sts bit get set, the intel ? 6300ESB ich will generate a wake event. once back in an s0 state (or if already in an s0 state when the event occurs), the intel ? 6300ESB ich w ill also generate an sci when the sci_en bit is set, or an smi# when the sci_en bit is not set. there will be no sci/smi# or wake event on thrmor_sts since there is no corresponding _en bit. none of these bits are reset by cf9h write. all are reset by rsmrst#. note: usage: acpi. table 289. lv2?level 2 register bits name description access 7:0 reads to this register return all zeros, writes to this register have no effect. reads to this register generate a ?enter a level 2 power state? (c2) to the clock control logic. this will cause the stpclk# signal to go active, and stay active until a break event occurs. throttling (due either to thtl_en or thrm# override) will be ignored. ro device: 31 function: 0 i/o address: pmbase + 14h (acpi p_blk + 4) attribute: read-only default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 401 8?intel ? 6300ESB ich table 290. gpe0_sts?general purpose event 0 status register (sheet 1 of 3) bits name description access 31:1 6 gpin_sts these bits are set any time the corresponding gpio is set up as an input and the corresponding gpio signal is high (or low when the corresponding gp_inv bit is set). when the corresponding enable bit is set in the gpe0_en register, then the gpi[n]_sts bit is set: ? when the system is in an s1-s5 state, the event will also wake the system. ? when the system is in an s0 state (or upon waking back to an s0 state), a sci will be caused depending on the gpi_rout bits for the corresponding gpi. note: these bits are sticky and are cleared by writing a 1 back to this bit position. corresponding bits and gpios bit # gpi[n]bit # gpi[n] 16 0 24 8 17 1 25 na 18 2 26 na 19 3 27 11 20 4 28 12 21 5 29 13 22 6 30 na 23 7 31 na r/wc 15:1 4 reserved reserved. 13 pme_b0_sts this bit will be set to 1 by the intel ? 6300ESB ich when any internal device on bus 0 asserts the equivalent of the pme# signal. additionally, when the pme_b0_en bit is set, and the system is in an s0 state, the setting of the pme_b0_sts bit will generate an sci (or smi# when sci_en is not set). when the pme_b0_sts bit is set, and the system is in an s1-s4 state (or s5 state due to slp_typ and slp_en), the setting of the pme_b0_sts bit will generate a wake event, and an sci (or smi# when sci_en is not set) will be generated. when the system is in an s5 state due to power button override, the pme_b0_sts bit will not cause a wake event or sci. the default for this bit is 0. writing a 1 to this bit position clears this bit. r/wc 12 reserved reserved. device: 31 function: 0 i/o address: pmbase + 28h (acpi pgpe0_blk) attribute: read/write clear default value: 00000000h size: 32-bit lockable: no power well: resume
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 402 order number: 300641-004us 11 pme_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware when the pme# signal goes active. additionally, when the pme_en bit is set and the system is in an s0 state, then the setting of the pme_sts bit will generate an sci or smi# (when sci_en is not set). when the pme_en bit is set and the system is in an s1- s4 state (or s5 state due to setting slp_typ and slp_en), then the setting of the pme_sts bit will generate a wake event, and an sci (or smi# if smi_en is not set) will be generated. when the system is in an s5 state due to power button override, pme_sts will not cause a wake event or sci. r/wc 10:9 reserved reserved. 8ri_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware when the ri# input signal goes active. r/wc 7 smbus wake status (smb_wak_sts) the smbus controller may independently cause an smi# or sci, so this bit does not need to do so (unlike the other bits in this register). 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware to indicate that the wake event was caused by the intel ? 6300ESB ich?s smbus logic.this bit will be set by the wake/smi# command type, even when the system is already awake. the smi handler should then clear this bit. note: this bit is set by the smbus slave command 01h (wake/smi#) even when the system is in the s0 state. therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the wake/smi# command or just prior to entering the sleep state. note: when smb_wak_sts is set due to smbus slave receiving a message, it will be cleared by internal logic when a thrmtrip# event happens or a power button override event. however, thrmtrip# or power button override event will not clear smb_wak_sts when it is set due to smbalert# signal going active. r/wc 6 tcosci_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware when the tco logic causes an sci. r/wc table 290. gpe0_sts?general purpose event 0 status register (sheet 2 of 3) bits name description access device: 31 function: 0 i/o address: pmbase + 28h (acpi pgpe0_blk) attribute: read/write clear default value: 00000000h size: 32-bit lockable: no power well: resume
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 403 8?intel ? 6300ESB ich 5 ac97_sts this bit will be set to 1 by when the codecs are attempting to wake the system and the pme events for the codecs are armed for wakeup. a pme is armed by programming the appropriate pmee bit in the power management control and status register at bit 8 of offset 54h in each ac?97 function. 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware when the codecs are attempting to wake the system. the ac97_sts bit gets set only from the following two cases: 1. the pmee bit for the function is set, and the ac-link bit clock has been shut and the routed ac_sdin line is high (for audio, when routing is disabled, no wake events are allowed). 2. for modem, when audio routing is disabled, the wake event is an or of all ac_sdin lines. when routing is enabled, the wake event for modem is the remaining non-routed ac_sdin line), or o gpi status change interrupt bit (nabmbar + 30h, bit 0) is 1. this bit is not affected by a hard reset caused by a cf9h write. r/wc 4 usb2_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware when usb uhci controller 2 needs to cause a wake. wake event will be generated when the corresponding usb2_en bit is set. r/wc 3 usb1_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware when usb uhci controller 1 needs to cause a wake. wake event will be generated when the corresponding usb1_en bit is set. r/wc 2 reserved reserved. 1 thermal interrupt override status (thrmor_sts) 0 = software clears this bit by writing a 1 to the bit position. 1 = this bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling the processor?s clock at the thrm_dty ratio. this will not cause an smi#, sci, or wake event. r/wc 0 thermal interrupt status (thrm_sts) 0 = software clears this bit by writing a 1 to the bit position. 1 = set by hardware anytime the thrm# signal is driven active as defined by the thrm_pol bit. additionally, when the thrm_en bit is set, the setting of the thrm_sts bit will also generate a power management event (sci or smi#). r/wc table 290. gpe0_sts?general purpose event 0 status register (sheet 3 of 3) bits name description access device: 31 function: 0 i/o address: pmbase + 28h (acpi pgpe0_blk) attribute: read/write clear default value: 00000000h size: 32-bit lockable: no power well: resume
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 404 order number: 300641-004us 8.8.3.8 gpe0_en?general purpose event 0 enables register note: this register is symmetrical to the general purpose event 0 status register. all the bits in this register should be cleared to 0 based on a power button override. the resume well bits are all cleared by rsmrst#. the rtc well bits are cleared by rtcrst#. note: usage: acpi. table 291. gpe0_en?general purpose event 0 enables register (sheet 1 of 2) bits name description access 31:1 6 gpin_en these bits enable the corresponding gpi[n]_sts bits being set to cause a sci, and/or wake event. these bits are cleared by rsmrst#. r/w 15:1 4 reserved reserved. 13 pme_b0_en enables the setting of the pme_b0_sts bit to generate a wake event and/or an sci or smi#. pme_b0_sts may be a wake event from the s1-s4 states, or from s5 (when entered through slp_typ and slp_en) or power failure, but not power button override. this bit defaults to 0. it is only cleared by software or rtcrst#. it is not cleared by cf9h writes. r/w 12 reserved reserved. 11 pme_en this bit defaults to 0. it is only cleared by software or rtcrst#. it is not cleared by cf9h writes. 0 = disable. 1 = enables the setting of the pme_sts to generate a wake event and/or an sci. pme# may be a wake event from the s1 - s4 state or from s5 (when entered through slp_en or power failure, but not power button override). r/w 10 reserved reserved. 9 reserved reserved. 8ri_en the value of this bit will be maintained through a g3 state and is not affected by a hard reset caused by a cf9h write. 0 = disable. 1 = enables the setting of the ri_sts to generate a wake event. r/w 7 reserved reserved. 6tcosci_en 0 = disable. 1 = enables the setting of the tcosci_sts to generate an sci. r/w 5ac97_en 0 = disable. 1 = enables the setting of the ac97_sts to generate a wake event. r/w device: 31 function: 0 i/o address: pmbase + 2ch (acpi gpe0_blk + 4) attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: bits 0-7, 12, 16-31 resume, bits 8-11, 13 rtc
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 405 8?intel ? 6300ESB ich 8.8.3.9 smi_en?smi control and enable register note: usage: acpi or legacy 4usb2_en 0 = disable. 1 = enable the setting of the usb2_sts bit to generate a wake event. the usb2_sts bit is set anytime usb uhci controller #2 signals a wake event. break events are handled through the usb interrupt. r/w 3usb1_en 0 = disable. 1 = enable the setting of the usb1_sts bit to generate a wake event. the usb1_sts bit is set anytime usb uhci controller #1 signals a wake event. break events are handled through the usb interrupt. r/w 2thrm#_pol this bit controls the polarity of the thrm# pin needed to set the thrm_sts bit. 0 = low value on the thrm# signal will set the thrm_sts bit. 1 = high value on the thrm# signal will set the thrm_sts bit. r/w 1 reserved reserved. 0thrm_en 0 = disable. 1 = active assertion of the thrm# signal (as defined by the thrm_pol bit) will set the thrm_sts bit and generate a power management event (sci or smi). r/w table 292. smi_en?smi control and enable register (sheet 1 of 3) bits name description access 31:1 9 reserved reserved. 18 intel_usb2_en enables intel-specific usb ehci smi logic to cause smi#. 17 legacy_usb2_en enables legacy usb ehci logic to cause smi#. 16:1 5 reserved reserved. table 291. gpe0_en?general purpose event 0 enables register (sheet 2 of 2) bits name description access device: 31 function: 0 i/o address: pmbase + 2ch (acpi gpe0_blk + 4) attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: bits 0-7, 12, 16-31 resume, bits 8-11, 13 rtc device: 31 function: 0 i/o address: pmbase + 30h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 406 order number: 300641-004us 14 periodic_en 0 = disable. 1 = enables the intel ? 6300ESB ich to generate an smi# when the periodic_sts bit is set in the smi_sts register. r/w 13 tco_en 0 = disables tco logic generating an smi#. note that when the nmi2smi_en bit is set, smis that are caused by re- routed nmis will not be gated by the tco_en bit. even when the tco_en bit is 0, nmis will still be routed to cause smis. 1 = enables the tco logic to generate smi#. note: this bit can not be written once the tco_lock bit (at offset 08h of tco i/o space) is set. this prevents unauthorized software from disabling the generation of tco-based smi?s r/w 12 reserved reserved. 11 mcsmi_en: microcon- troller smi enable 0 = disable. 1 = enables the intel ? 6300ESB ich to trap accesses to the microcontroller range (62h or 66h) and generate an smi#. note that ?trapped? cycles will be claimed by the intel ? 6300ESB ich on pci, but not forwarded to lpc. r/w 10:8 reserved reserved. 7 bios_rls: bios release 0 = this bit will always return 0 on reads. writes of 0 to this bit have no effect. 1 = enables the generation of an sci interrupt for acpi software when a one is written to this bit position by bios software. wo 6 swsmi_tmr_en: software smi# timer enable 0 = disable. clearing the swsmi_tmr_en bit before the timer expires will reset the timer and the smi# will not be generated. 1 = starts software smi# timer. when the swsmi timer expires (the timeout period depends upon the swsmi_rate_sel bit setting), swsmi_tmr_sts is set and an smi# is generated. swsmi_tmr_en stays set until cleared by software. r/w 5apmc_en 0 = disable. writes to the apm_cnt register will not cause an smi#. 1 = enables writes to the apm_cnt register to cause an smi#. r/w 4 slp_smi_en 0 = disables the generation of smi# on slp_en. note that this bit must be 0 before the software attempts to transition the system into a sleep state by writing a 1 to the slp_en bit. 1 = a write of 1 to the slp_en bit (bit 13 in pm1_cnt register) will generate an smi#, and the system will not transition to the sleep state based on that write to the slp_en bit. r/w 3 legacy_usb_en 0 = disable. 1 = enables legacy usb circuit to cause smi#. r/w table 292. smi_en?smi control and enable register (sheet 2 of 3) bits name description access device: 31 function: 0 i/o address: pmbase + 30h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 407 8?intel ? 6300ESB ich 8.8.3.10 smi_sts?smi status register note: when the corresponding _en bit is set when the _sts bit is set, the intel ? 6300ESB ich will cause an smi# (except bits 8-10 and 12, which do not need enable bits since they are logically ored with other registers that have enable bits). the intel ? 6300ESB ich uses the same gpe0_en register (i/o address: pmbase+2ch) to enable/disable both smi and acpi sci general purpose input events. acpi os assumes that it owns the entire gpe0_en register per acpi spec. problems arise when some of the general- purpose inputs are enabled as smi by bios, and some of the general purpose inputs are enabled for sci. in this case acpi os turns off the enabled bit for any gpix input signals that are not indicated as sci general-purpose events at boot, and exit from sleeping states. bios should define a dummy control method which prevents the acpi os from clearing the smi gpe0_en bits. note: usage: acpi or legacy. 2bios_en 0 = disable. 1 = enables the generation of smi# when acpi software writes a 1 to the gbl_rls bit. r/w 1eos: end of smi this bit controls the arbitration of the smi signal to the processor. this bit must be set for the intel ? 6300ESB ich to assert smi# low to the processor. 0 = once the intel ? 6300ESB ich asserts smi# low, the eos bit is automatically cleared. 1 = when this bit is set, smi# signal will be deasserted for 4 pci clocks before its assertion. in the smi handler, the processor should clear all pending smis (by servicing them and then clearing their respective status bits), set the eos bit, and exit smm. this will allow the smi arbiter to re-assert smi upon detection of an smi event and the setting of a smi status bit. note: the intel ? 6300ESB ich is able to generate 1st smi after reset even though eos bit is not set. subsequent smi require eos bit is set. r/w (special) 0 gbl_smi_en 0 = no smi# will be generated by the intel ? 6300ESB ich. this bit is reset by a pci reset event. 1 = enables the generation of smi# in the system upon any enabled smi event. r/w table 292. smi_en?smi control and enable register (sheet 3 of 3) bits name description access device: 31 function: 0 i/o address: pmbase + 30h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 408 order number: 300641-004us table 293. smi_sts?smi status register (sheet 1 of 2) bits name description access 31:2 4 reserved reserved. 23 wdt_smi_sts 0 = smi# not caused by wdt 1 st timeout. 1 = indicates the smi# was caused by the wdt 1 st timeout. 22:1 9 reserved reserved . 18 intel_usb2_sts this non-sticky read-only bit is a logical or of each of the smi status bits in the intel-specific usb ehci smi status register anded with the corresponding enable bits. this bit will not be active when the enable bits are not set. writes to this bit will have no effect. 17 legacy_usb2_sts this non-sticky read-only bit is a logical or of each of the smi status bits in the usb ehci legacy support register anded with the corresponding enable bits. this bit will not be active when the enable bits are not set. writes to this bit will have no effect. 16 smbus smi status (smbus_smi_sts) 0 = this bit is cleared by writing a 1 to its bit position. this bit is set from the 64 khz clock domain used by the smbus. software must wait at least 15.63 us after the initial assertion of this bit before clearing it. 1 = indicates that the smi# was caused by: 1. the smbus slave receiving a message, or 2. the smbalert# signal goes active and the smb_smi_en bit is set and the smbalert_dis bit is cleared, or 3. the smbus slave receiving a host notify message and the host_notify_intren and the smb_smi_en bits are set, or 4. the intel ? 6300ESB ich detecting the smlink_slave_smi command while in the s0 state. r/wc 15 serirq_smi_sts 0 = smi# was not caused by serirq decoder. this is not a sticky bit. 1 = indicates that the smi# was caused by the serirq decoder. ro 14 periodic_sts 0 = this bit is cleared by writing a 1 to its bit position. 1 = this bit will be set at the rate determined by the per_smi_sel bits. when the periodic_en bit is also set, the intel ? 6300ESB ich will generate an smi#. r/wc 13 tco_sts 0 = smi# not caused by tco logic. 1 = indicates the smi# was caused by the tco logic. note that this is not a wake event. ro 12 devmon_sts: device monitor status 0 = smi# not caused by device monitor. 1 = set under any of the following conditions: - any of the dev[7:4]_trap_sts bits are set and the corresponding dev[7:4]_trap_en bits are also set. - any of the devtrap_sts bits are set and the corresponding devtrap_en bits are also set. ro device: 31 function: 0 i/o address: pmbase + 34h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 409 8?intel ? 6300ESB ich 11 mcsmi_sts: microcon- troller smi# status 0 = indicates that there has been no access to the power management microcontroller range (62h or 66h). this bit is cleared by software writing a 1 to the bit position. 1 = set when there has been an access to the power management microcontroller range (62h or 66h). when this bit is set, and the mcsmi_en bit is also set, the intel ? 6300ESB ich will generate an smi#. r/wc 10 gpe1_sts this bit is a logical or of the bits in the alt_gp_smi_sts register that are also set up to cause an smi# (as indicated by the gpi_rout registers) and have the corresponding bit set in the alt_gp_smi_en register. bits that are not routed to cause an smi# will have no effect on this bit. 0 = smi# was not generated by a gpi assertion. 1 = smi# was generated by a gpi assertion. ro 9 gpe0_sts this bit is a logical or of the bits in the gpe0_sts register that also have the corresponding bit set in the gpe0_en register. 0 = smi# was not generated by a gpe0 event. 1 = smi# was generated by a gpe0 event. r/wc 8 pm1_sts_reg this is an ors of the bits in the acpi pm1 status register (offset pmbase+00h) that may cause an smi#. 0 = smi# was not generated by a pm1_sts event. 1 = smi# was generated by a pm1_sts event. r/wc 7 reserved reserved. 6 swsmi_tmr_sts 1 = set by the hardware when the software smi# timer expires. 0 = software clears this bit by writing a 1 to the bit location. r/wc 5apm_sts 0 = software clears this bit by writing a 1 to the bit location. 1 = smi# was generated by a write access to the apm control register with the apmc_en bit set. r/wc 4slp_smi_sts 0 = software clears this bit by writing a 1 to the bit location. 1 = indicates an smi# was caused by a write of 1 to slp_en bit when slp_smi_en bit is also set. r/wc 3 legacy_usb_sts this bit is a logical or of each of the smi status bits in the usb legacy keyboard/mouse control registers anded with the corresponding enable bits. this bit will not be active when the enable bits are not set. 0 = smi# was not generated by usb legacy event. 1 = smi# was generated by usb legacy event. ro 2 bios_sts 0 = this bit cleared by software writing a 1 to its bit position. 1 = smi# was generated due to acpi software requesting attention (writing a 1 to the gbl_rls bit with the bios_en bit set). r/wc 1:0 reserved reserved. table 293. smi_sts?smi status register (sheet 2 of 2) bits name description access device: 31 function: 0 i/o address: pmbase + 34h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 410 order number: 300641-004us 8.8.3.11 alt_gp_smi_en?alternate gpi smi enable register note: usage: acpi or legacy. table 294. alt_gp_smi_en?alternate gpi smi enable register bits name description access 15:0 these bits are used to enable the corresponding gpio to cause an smi#. in order for these bits to have any effect, the following must be true. ? the corresponding bit in the alt_gp_smi_en register is set. ? the corresponding gpi must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. device: 31 function: 0 i/o address: pmbase +38h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: resume
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 411 8?intel ? 6300ESB ich 8.8.3.12 alt_gp_smi_sts?alternate gpi smi status register note: usage: acpi or legacy. 8.8.3.13 mon_smi?device monitor smi status and enable register note: usage: legacy only. table 295. alt_gp_smi_sts?alternate gpi smi status register bits name description access 15:0 these bits report the status of the corresponding gpis. 1 = active, 0 = inactive. these bits are sticky. when the following conditions are true, an smi# will be generated and the gpe0_sts bit set: ? the corresponding bit in the alt_gpi_smi_en register is set. ? the corresponding gpi must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. all bits are in the resume well. default for these bits is dependent on the state of the gpi pins. table 296. mon_smi?device monitor smi status and enable register bits name description access 15:1 2 dev[7:4]_trap_sts bit 12 corresponds to monitor 4, bit 13 corresponds to monitor 5 etc. 0 = smi# was not caused by the associated device monitor. 1 = smi# was caused by an access to the corresponding device monitor?s i/o range. r/wc 11:8 dev[7:4]_trap_en bit 8 corresponds to monitor 4, bit 9 corresponds to monitor 5 etc. 0 = disable. 1 = enables smi# due to an access to the corresponding device monitor?s i/o range. r/w 7:0 reserved reserved. device: 31 function: 0 i/o address: pmbase +3ah attribute: read-only default value: 0000h size: 16-bit lockable: no power well: resume device: 31 function: 0 i/o address: pmbase +40h attribute: read/write, read/write clear default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 412 order number: 300641-004us 8.8.3.14 devact_sts?device activity status register note: this register is used in conjunction with the periodic smi# timer to detect any system activity for legacy power management. each bit indicates if the an access has occurred to the corresponding device?s trap range, or for bits 6:9 if the corresponding pci interrupt is active. write 1 to the same bit position to clear it. this register is used by apm power management software to see if there has been system activity. the periodic smi# timer indicates if it is the right time to read the devtrap_sts register. note: usage: legacy only. table 297. devact_sts?device activity status register (sheet 1 of 2) bits name description access 15:1 4 reserved reserved. 13 adlib_act_sts ad-lib. 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. note: this bit is no longer supported and will not be validated. r/wc 12 kbc_act_sts kbc (60/64h). 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. note: if bit 7 of etr1 (d31:f0, offset f4h, section 9.1.35) is set. ports 60/64h accesses initiated from an external pci agent will not set this bit. r/wc 11 midi_act_sts midi. 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. note: this bit is no longer supported and will not be validated. r/wc 10 audio_act_sts audio (sound blaster ?or?d? with mss). 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. note: this bit is no longer supported and will not be validated. r/wc 9pirqdh_act_sts pirq[d or h]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. r/wc device: 31 function: 0 i/o address: pmbase +44h attribute: read/write clear default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 413 8?intel ? 6300ESB ich 8 pirqcg_act_sts pirq[c or g]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. r/wc 7pirqbf_act_sts pirq[b or f]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. r/wc 6pirqae_act_sts pirq[a or e]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. r/wc 5leg_act_sts parallel port, serial port 1, serial port 2, floppy disk controller. 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. r/wc 4 reserved reserved. 3ides1_act_sts ide secondary drive 1. 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. r/wc 2ides0_act_sts ide secondary drive 0. 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. r/wc 1 idep1_act_sts ide primary drive 1. 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. r/wc 0 idep0_act_sts ide primary drive 0. 0 = indicates that there has been no access to this device?s i/ o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. r/wc table 297. devact_sts?device activity status register (sheet 2 of 2) bits name description access device: 31 function: 0 i/o address: pmbase +44h attribute: read/write clear default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 414 order number: 300641-004us 8.8.3.15 devtrap_en? device trap enable register note: this register enables the individual trap ranges to generate an smi# when the corresponding status bit in the devact_sts register is set. when a range is enabled, i/ o cycles associated with that range will not be forwarded to lpc or ide. note: usage: legacy only. table 298. devtrap_en? device trap enable register bits name description access 15:1 4 reserved reserved. 13 adlib_trp_en ad-lib. 0 = disable. 1 = enable. note: this bit is no longer supported and will not be validated. r/w 12 kbc_trp_en kbc (60/64h). 0 = disable. 1 = enable. r/w 11 midi_trp_en midi. 0 = disable. 1 = enable. note: this bit is no longer supported and will not be validated. r/w 10 audio_trp_en audio (sound blaster ?ored? with mss). 0 = disable. 1 = enable. note: this bit is no longer supported and will not be validated. r/w 9:6 reserved reserved. 5 leg_io_trp_en parallel port, serial port 1, serial port 2, floppy disk controller. 0 = disable. 1 = enable. r/w 4 reserved reserved. 3ides1_trp_en ide secondary drive 1. 0 = disable. 1 = enable. r/w device: 31 function: 0 i/o address: pmbase +48h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 415 8?intel ? 6300ESB ich 8.8.3.16 bus_addr_track? bus address tracker this register could be used by the smi# handler to assist in determining what was the last cycle from the processor. bus_addr_track may not contain ?expected? last i/o cycle data when asynchronous smis and synchronous smis are occurring simultaneously. this register only reports ?expected? last i/o cycle data when asynchronous smis are disabled. note: usage: legacy only. 8.8.3.17 bus_cyc_track? bus cycle tracker this register could be used by the smm handler to assist in determining what was the last cycle from the processor. bus_cyc_track may not contain ?expected? last i/o cycle data when asynchronous smis and synchronous smis are occurring simultaneously. this register only reports ?expected? last i/o cycle data when asynchronous smis are disabled. note: usage: legacy only. 2 ides0_trp_en ide secondary drive 0. 0 = disable. 1 = enable. r/w 1idep1_trp_en ide primary drive 1. 0 = disable. 1 = enable. r/w 0idep0_trp_en ide primary drive 0. 0 = disable. 1 = enable. r/w table 298. devtrap_en? device trap enable register bits name description access device: 31 function: 0 i/o address: pmbase +48h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core table 299. bus_addr_track? bus address tracker bits name description access 15:0 corresponds to the low 16 bits of the last i/o cycle, as would be defined by the pci ad[15:0] signals on the pci bus (even though it may not be a real pci cycle). the value is latched based on smi# active. this functionality is useful for figuring out which i/o was last being accessed. device: 31 function: 0 i/o address: pmbase +4ch attribute: read-only size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 416 order number: 300641-004us 8.9 system management tco registers (d31:f0) the tco logic is accessed through registers mapped to the pci configuration space (device 31:function 0) and the system i/o space. for tco pci configuration registers, see lpc device 31:function 0 pci configuration registers. 8.9.1 tco register i/o map the tco i/o registers reside in a 32-byte range pointed to by a tcobase value, which is, acpibase + 60h in the pci config space. the following table shows the mapping of the registers within that 32-byte range. each register is described in the sections below. table 300. bus_cyc_track? bus cycle tracker bits name description access 7:4 corresponds to the byte enables, as would be defined by the pci c/be# signals on the pci bus (even though it may not be a real pci cycle). the value is latched based on smi# going active. 3:0 corresponds to the cycle type, as would be defined by the pci c/be# signals on the pci bus (even though it may not be a real pci cycle). the value is latched based on smi# going active. device: 31 function: 0 i/o address: pmbase +4eh attribute: read-only size: 8-bit lockable: no power well: core table 301. tco i/o register map offset typ e register name: function 00h r/w tco_rld: tco timer reload and current value 01h r/w tco_tmr: tco timer initial value 02h r/w tco_dat_in: tco data in 03h r/w tco_dat_out: tco data out 04h - 05h r/w tco1_sts: tco status 06h - 07h r/w tco2_sts: tco status 08h - 09h r/w tco1_cnt: tco control 0ah - 0bh r/w tco2_cnt: tco control 0ch - 0dh r/w tco_message1, tco_message2: used by bios to indicate post/boot progress 0eh r/w tco_wdstatus: watchdog status register
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 417 8?intel ? 6300ESB ich 8.9.2 tco1_rld?tco timer reload and current value 8.9.3 tco1_tmr?tco timer initial value 0fh ro reserved 10h r/w sw_irq_gen: software irq generation register 11h - 1fh ro reserved table 302. tco1_rld?tco timer reload and current value bits name description access 7:0 reading this register will return the current count of the tco timer. writing any value to this register will reload the timer to prevent the timeout. bits 7:6 will always be 0. table 303. tco1_tmr?tco timer initial value bits name description access 7:6 reserved reserved. 5:0 value that is loaded into the timer each time the tco_rld register is written. values of 0h - 3h will be ignored and should not be attempted. the timer is clocked at approximately 0.6 seconds, and this allows timeouts ranging from 2.4 seconds to 38 seconds. r/w table 301. tco i/o register map offset typ e register name: function device: 31 function: 0 i/o address: tcobase +00h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 0 i/o address: tcobase +01h attribute: read/write default value: 04h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 418 order number: 300641-004us 8.9.4 tco1_dat_in?tco data in register 8.9.5 tco1_dat_out?tco data out register table 304. tco1_dat_in?tco data in register bits name description access 7:0 data register for passing commands from the os to the smi handler. writes to this register will cause an smi and set the os_tco_smi bit in the tco_sts register. table 305. tco1_dat_out?tco data out register bits name description access 7:0 data register for passing commands from the smi handler to the os. writes to this register will set the tco_int_sts bit in the tco_sts register. it will also cause an interrupt, as selected by the tco_int_sel bits. device: 31 function: 0 i/o address: tcobase +02h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 0 i/o address: tcobase +03h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 419 8?intel ? 6300ESB ich 8.9.6 tco1_sts?tco1 status register table 306. tco1_sts?tco1 status register (sheet 1 of 2) bits name description access 15:1 3 reserved reserved. 12 hubserr_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = the intel ? 6300ESB ich received an serr# message through the hub interface. the software must read the memory controller hub (or its equivalent) to determine the reason for the serr#. note: when this bit is set and the serr_en bit in cmd register (d30:f0, offset 04h, bit 8) is also set, the intel ? 6300ESB ich will set the sse bit in secsts register (d30:f0, offset 1eh, bit 14) and will also generate a nmi (or smi# when nmi routed to smi#). r/wc 11 hubnmi_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = the intel ? 6300ESB ich received an nmi message through the hub interface. the software must read the memory controller hub (or its equivalent) to determine the reason for the nmi. r/wc 10 hubsmi_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = the intel ? 6300ESB ich received an smi message through the hub interface. the software must read the memory controller hub (or its equivalent) to determine the reason for the smi#. r/wc 9 hubsci_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = the intel ? 6300ESB ich received an sci message through the hub interface. the software must read the memory controller hub (or its equivalent) to determine the reason for the sci. r/wc 8 bioswr_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = the intel ? 6300ESB ich sets this bit and generates and smi# to indicate an illegal attempt to write to the bios. this occurs when either: a) the bioswp bit is changed from 0 to 1 and the bld bit is also set, or b) any write is attempted to the bios and the bioswp bit is also set. r/wc device: 31 function: 0 i/o address: tcobase +04h attribute: read-only, read/write clear default value: 0000h size: 16-bit lockable: no power well: core (except bit 7, in rtc)
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 420 order number: 300641-004us 7newcentury_sts this bit is in the rtc well. 0 = cleared by writing a 1 to the bit position or by rtcrst# going active. 1 = this bit is set when the year byte (rtc i/o space, index offset 09h) rolls over from 99 to 00. setting this bit will cause an smi# (but not a wake event). note that the newcentury_sts bit is not valid when the rtc battery is first installed (or when rtc power has not been maintained). software may determine when rtc power has not been maintained by checking the rtc_pwr_sts bit, or by other means (such as a checksum on rtc ram). when rtc power is determined to have not been maintained, bios should set the time to a legal value and then clear the newcentury_sts bit. the newcentury_sts bit may take up to 3 rtc clocks for the bit to be cleared after a ?1? is written to the bit to clear it. after writing a ?1? to this bit, software should not exit the smi handler until verifying that the bit has actually been cleared. this will ensure that the smi is not re-entered. r/wc 6:4 reserved reserved. 3timeout 0 = software clears this bit by writing a 1 to the bit position. 1 = set by the intel ? 6300ESB ich to indicate that the smi was caused by the tco timer reaching 0. r/wc 2tco_int_sts 0 = software clears this bit by writing a 1 to the bit position. 1 = smi handler caused the interrupt by writing to the tco_dat_out register. r/wc 1sw_tco_smi 0 = software clears this bit by writing a 1 to the bit position. 1 = software caused an smi# by writing to the tco_dat_in register. r/wc 0 nmi2smi_sts 0 = cleared by clearing the associated nmi status bit. 1 = set by the intel ? 6300ESB ich when an smi# occurs because an event occurred that would otherwise have caused an nmi (because nmi2smi_en is set). ro table 306. tco1_sts?tco1 status register (sheet 2 of 2) bits name description access device: 31 function: 0 i/o address: tcobase +04h attribute: read-only, read/write clear default value: 0000h size: 16-bit lockable: no power well: core (except bit 7, in rtc)
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 421 8?intel ? 6300ESB ich 8.9.7 tco2_sts?tco2 status register table 307. tco2_sts?tco2 status register bits name description access 15:5 reserved reserved. 4 smlink_slv_smi_sts smlink slave smi status (allow the software to go directly into pre-determined sleep state. this avoids race conditions. 0 = the bit is reset by rsmrst#, but not due to the pci reset associated with exit from s3-s5 states. 1 = the intel ? 6300ESB ich sets this bit to 1 when it receives the smi message on the smlink's slave interface. software clears the bit by writing a 1 to this bit position. r/w 3bad_bios this bit is set by the intel ? 6300ESB ich when it detects ffh on the first bios read (i.e., the bios is bad). intel ? 6300ESB ich clears this bit to 0 if the first bios read is not ffh. this is detected when the initial read returns ffh from the fwh. this bit is not intended to be read by the bios or software. it is only used for sending the tco/heartbeat messages to an external lan controller. reads to this bit always return 0 and writes have no effect. 2 boot_sts: 0 = cleared by the intel ? 6300ESB ich based on rsmrst# or by software writing a 1 to this bit. note that software should first clear the second_to_sts bit before writing a 1 to clear the boot_sts bit. 1 = set to 1 when the second_to_sts bit goes from 0 to 1 and the processor has not fetched the first instruction. 1second_to_sts 0 = this bit is cleared by writing a 1 to the bit position or by a rsmrst#. 1 = the intel ? 6300ESB ich sets this bit to a 1 to indicate that the tco timer timed out a second time (probably due to system lock). when this bit is set and the no_reboot configuration bit is 0, then the intel ? 6300ESB ich will reboot the system after the second timeout. the reboot is done by asserting pxpcirst#. r/wc 0 intrd_det: intruder detect 0 = this bit is only cleared by writing a 1 to the bit position, or by rtcrst# assertion. 1 = set by the intel ? 6300ESB ich to indicate that an intrusion was detected. this bit is set even when the system is in g3 state. r/wc device: 31 function: 0 i/o address: tcobase +06h attribute: read-only, read/write clear default value: 0000h size: 16-bit lockable: no power well: resume (except bit 0, in rtc)
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 422 order number: 300641-004us 8.9.8 tco1_cnt?tco1 control register table 308. tco1_cnt?tco1 control register bits name description access 15:1 3 reserved reserved. 12 tco_lock 0 = this bit defaults to 0. a core-well reset is required to change this bit from 1 to 0. 1 = prevents writes from changing the tco_en bit (in offset 30h of power management i/o space). once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. r/w 11 tco_tmr_hlt: tco timer halt 0 = the tco timer is enabled to count. 1 = the tco timer will halt. it will not count, and thus cannot reach a value that will cause an smi# or set the second_to_sts bit. when set, this bit will prevent rebooting and prevent alert on lan event messages from being transmitted on the smlink (but not alert on lan* heartbeat messages). r/w 10 send_now 0 = the intel ? 6300ESB ich will clear this bit when it has completed sending the message. software must not set this bit to 1 again until the intel ? 6300ESB ich has set it back to 0. 1 = writing a 1 to this bit will cause the intel ? 6300ESB ich to send an event message with the software event bit set. r/w 9 nmi2smi_en 0 = normal nmi functionality. 1 = forces all nmis to instead cause smis. the functionality of this bit is dependent upon the settings of the nmi_en bit and the gbl_smi_en bit as detailed in the following table: nmi_en gbl_smi_en description 0 0 no smi# at all because gbl_smi_en = 0 0 1 smi# will be caused due to nmi events 1 0 no smi# at all because gbl_smi_en = 0 1 1 no smi# due to nmi because nmi_en = 1 r/w 8nmi_now 0 = this bit is cleared by writing a 1 to the bit position. the nmi handler is expected to clear this bit. another nmi will not be generated until the bit is cleared. 1 = writing a 1 to this bit causes an nmi. this allows the bios or smi handler to force an entry to the nmi handler. r/wc 7:0 reserved reserved. device: 31 function: 0 i/o address: tcobase +08h attribute: read-only, read/write clear default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 423 8?intel ? 6300ESB ich 8.9.9 tco2_cnt?tco2 control register 8.9.10 tco_message1 and tco_message2 registers table 309. tco2_cnt?tco2 control register bits name description access 15:4 reserved reserved. 3 gpio11_alert_disabl e disable gpio11/smbalert# as an alert source for the heartbeats and the smbus slave. at reset (via rsmrst# asserted) this bit is set and gpio[11] alerts are disabled r/w 2:1 intrd_se selects the action to take when the intruder# signal goes active. 00 = no interrupt or smi# 01 = interrupt (as selected by tco_int_sel). 10 = smi 11 = reserved r/w 0 reserved reserved. table 310. tco_message1 and tco_message2 registers bits name description access 7:0 tco_message[ n ] the value written to this register can be passed via smbus to an external lan controller. it may be used by the bios or system management software to indicate more details on the boot progress. this register will be reset to the default of 00h based on rsmrst# (but not pci reset). r/w device: 31 function: 0 i/o address: tcobase +0ah attribute: read/write default value: 0008h size: 16-bit lockable: no power well: resume device: 31 function: 0 i/o address: tcobase+0ch(message 1) tcobase+0dh(message 2) attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 424 order number: 300641-004us 8.9.11 offset tcobase + oeh: tco_wdstatus?tco2 control register 8.9.12 offset tcobase + 10h: sw_irq_gen?software irq generation register table 311. offset tcobase + oeh: tco_wdstatus?tco2 control register bits name description access 7:0 wdstatus: watchdog status the value written to this register can be passed via smbus to an external lan controller. it may be used by the bios or system management software to indicate more details on the boot progress. this register will be reset to the default of 00h based on rsmrst# (but not pci reset). r/w table 312. offset tcobase + 10h: sw_irq_gen?software irq generation register bits name description access 7:2 reserved reserved. 1 irq12_cause the state of this bit is logically anded with the irq12 signal as received by the intel ? 6300ESB ich?s serirq logic. this bit must be a ?1? (default) when the intel ? 6300ESB ich is expected to receive irq12 assertions from a serirq device. r/w 0irq1_cause the state of this bit is logically anded with the irq1 signal as received by the intel ? 6300ESB ich?s serirq logic. this bit must be a ?1? (default) when the intel ? 6300ESB ich is expected to receive irq1 assertions from a serirq device. r/w device: 31 function: 0 offset: tcobase + 0eh attribute: read/write default value: 00h size: 8-bit lockable: no power well: resume device: 31 function: 0 offset: tcobase + 10h attribute: read/write default value: 11h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 425 8?intel ? 6300ESB ich 8.10 general purpose i/o registers (d31:f0) the control for the general purpose i/o signals is handled through a separate 64-byte i/o space. the base offset for this space is selected by the gpio_bar register. 8.10.1 gpio register i/o address map table 313. registers to control gpio offset mnemonic register name default access general registers 00-03h gpio_use_sel gpio use select 1b003100h r/w 04-07h gp_io_sel gpio input/output select 0000 ffffh r/w 0c-0fh gp_lvl gpio level for input or output 1f1f 0000h r/w output control registers 18-1bh gpo_blink gpio blink enable 00000000h r/w input control registers 2c-2fh gpi_inv gpio signal invert 00000000h r/w 30-33h gpio_use_sel 2 gpio use select 03000000h r/w 34-37h gp_io_sel2 gpio input/output select 2 00000000h r/w 38-3bh gp_lvl2 gpio level for input or output 2 00000fffh r/w
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 426 order number: 300641-004us 8.10.2 offset gpiobase + 00h: gpio_use_sel?gpio use select register 8.10.3 offset gpiobase + 04h: gp_io_sel?gpio input/output select register table 314. offset gpiobase + 00h: gpio_use_sel?gpio use select register bits name description access 23, 21:1 6, 11, 7:0 gpio_use_sel[0:7, 11, 16:21, 23] enables gpio[n] (where n is the bit number) to be used as a gpio, rather than for the native function. 1 = signal used as gpio (or unmuxed). 0 = signal used as native function. notes: 1. the following bits are not implemented because there is no corresponding gpio: 9:10, 14:15, 22, 26 and 29:31. 2. the following bits are always 1 because they are unmuxed: 8, 12:13, 24, 25, 27:28. 3. when gpio[n] does not exist, the bit in this register will always read as 0 and writes will have no effect. 4. after a full reset (rsmrst#) all multiplexed signals in the resume and core wells are configured as their native function rather than as a gpio. after just a pxpcirst#, the gpio in the core well are configured as their native function. table 315. offset gpiobase + 04h: gp_io_sel?gpio input/output select register bits name description access 31:2 9, 26 reserved reserved. 28:2 7 25:2 4 gpio[n]_sel 0 = output. the corresponding gpio signal is an output. 1 = input. the corresponding gpio signal is an input. r/w 23 always 0. the gpios are fixed as outputs. device: 31 function: 0 offset: gpiobase + 00h attribute: read/write default value: 1b003100h size: 32-bit lockable: yes power well: core for 0:7 and 16:21, 23 resume for 8:15 and 24:31 device: 31 function: 0 offset: gpiobase +04h attribute: read-only default value: 0000ffffh size: 32-bit lockable: no power well: resume
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 427 8?intel ? 6300ESB ich 8.10.4 offset gpiobase + 0ch: gp_lvl?gpio level for input or output register 22 reserved reserved. 21:1 6 always 0. the gpios are fixed as outputs. 15:0 always 1. these gpios are fixed as inputs. table 316. offset gpiobase + 0ch: gp_lvl?gpio level for input or output register bits name description access 31:2 9, 26 reserved reserved. 28:2 7, 25:2 4 gp_lvl[n] when gpio[n] is programmed to be an output (through the corresponding bit in the gp_io_sel register), the bit may be updated by software to drive a high or low value on the output pin. when gpio[n] is programmed as an input, software may read the bit to determine the level on the corresponding input pin. these bits correspond to gpio that are in the resume well, and will be reset to their default values by rsmrst# and also by a write to the cf9h register. 0 = low 1 = high r/w table 315. offset gpiobase + 04h: gp_io_sel?gpio input/output select register bits name description access device: 31 function: 0 offset: gpiobase +04h attribute: read-only default value: 0000ffffh size: 32-bit lockable: no power well: resume device: 31 function: 0 offset: gpiobase +0ch attribute: read/write default value: 1b3f0000h size: 32-bit lockable: no power well: see bit descriptions
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 428 order number: 300641-004us 23 gp_lvl[n] these bits may be updated by software to drive a high or low value on the output pin. these bits correspond to gpio that are in the core well, and will be reset to their default values by pxpcirst#. 0 = low 1 = high r/w 21:1 6 gp_lvl[n] these bits may be updated by software to drive a high or low value on the output pin. these bits correspond to gpio that are in the core well, and will be reset to their default values by pxpcirst#. 0 = low 1 = high r/w 15:0 reserved reserved. these bits are not needed as the level of general inputs can be read through the gpe0_sts and alt_gp_smi_sts registers. see section 8.8.3.7 and section 8.8.3.12 table 316. offset gpiobase + 0ch: gp_lvl?gpio level for input or output register bits name description access device: 31 function: 0 offset: gpiobase +0ch attribute: read/write default value: 1b3f0000h size: 32-bit lockable: no power well: see bit descriptions
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 429 8?intel ? 6300ESB ich 8.10.5 offset gpiobase + 18h: gpo_blink?gpo blink enable register table 317. offset gpiobase + 18h: gpo_blink?gpo blink enable register bits name description access 31:2 9, 26, 24:2 0, 17:0 reserved reserved. 28:2 7, 25 gp_blink[n] the setting of these bits will have no effect when the corresponding gpio is programmed as an input. these bits correspond to gpio that are in the resume well, and will be reset to their default values by rsmrst# or a write to the cf9h register. 0 = the corresponding gpio will function normally. 1 = when the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times have approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. r/w 19:1 8 gp_blink[n] the setting of these bits will have no effect when the corresponding gpio is programmed as an input. these bits correspond to gpio that are in the core well, and will be reset to their default values by pxpcirst#. 0 = the corresponding gpio will function normally. 1 = when the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times are approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. r/w device: 31 function: 0 offset: gpiobase +18h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: see bit description
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 430 order number: 300641-004us 8.10.6 offset gpiobase + 2ch: gpi_inv?gpio signal invert register table 318. offset gpiobase + 2ch: gpi_inv?gpio signal invert register bits name description access 31:1 4, 10:9 reserved reserved. 13:1 1, 8 gp_inv[n] these bits are used to allow both active-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, the input signal must be active for at least 2 pci clocks to ensure detection by the intel ? 6300ESB ich. in the s3, s4 or s5 states the input signal must be active for at least 2 rtc clocks to ensure detection. the setting of these bits will have no effect when the corresponding gpio is programmed as an output. these bits correspond to gpio that are in the resume well, and will be reset to their default values by rsmrst# or a write to the cf9h register. 0 = the corresponding gpin_sts bit will be set when the intel ? 6300ESB ich detects the state of the input pin to be high. 1 = the corresponding gpin_sts bit will be set when the intel ? 6300ESB ich detects the state of the input pin to be low. note: the gpin_sts bits are in the gpe0_sts register. see section 9.8.3.7 r/w 7:0 gp_inv[n] these bits are used to allow both active-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, the input signal must be active for at least 2 pci clocks to ensure detection by the intel ? 6300ESB ich. the setting of these bits will have no effect when the corresponding gpio is programmed as an output. these bits correspond to gpio that are in the core well, and will be reset to their default values by pxpcirst#. 0 = the corresponding gpin_sts bit will be set when the intel ? 6300ESB ich detects the state of the input pin to be high. 1 = the corresponding gpin_sts bit will be set when the intel ? 6300ESB ich detects the state of the input pin to be low. r/w device: 31 function: 0 offset: gpiobase +2ch attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: see bit description
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 431 8?intel ? 6300ESB ich 8.10.7 offset gpiobase + 30h:gpio_use_sel2?gpio use select 2 register table 319. offset gpiobase + 30h:gpio_use_sel2?gpio use select 2 register bits name description access 31:2 6 always 0. no corresponding gpio. 25:2 4 always 1. these pins are unmuxed. 23:1 2 always 0. no corresponding gpio. 11:8 gpio_use_sel[43:40]: enables gpio[n] (where n is the bit number) to be used as a gpio, rather than for the native function. since these pins may be used as outputs for controlling power planes, switching the pin from functional to gpo mode must be glitch-free. 1 = signal used as gpio (or unmuxed). 0 = signal used as native function. after a full reset(rsmrst#) all multiplexed signals in the resume and core wells are configured as their native function rather than as a gpio. after just a pxpcirst#, the gpio in the core well are configured as gpio. 7:0 gpio_use_sel[39:32]: enables gpio[n] (where n is the bit number) to be used as a gpio, rather than for the native function. since these pins may be used as outputs for controlling power planes, switching the pin from functional to gpo mode must be glitch-free. 1 = signal used as gpio (or unmuxed). 0 = signal used as native function. after a full reset(rsmrst#) all multiplexed signals in the resume and core wells are configured as their native function rather than as a gpio. after just a pxpcirst#, the gpio in the core well are configured as gpio. implementation note: bits 26:31 may be in core well. device: 31 function: 0 offset: gpiobase +30h attribute: read/write default value: 03000000h size: 32-bit lockable: no power well: core for 55:32 = bits 23:0 resume for 63:56 = bits 31:24
intel ? 6300ESB ich?8 intel ? 6300ESB i/o controller hub ds november 2007 432 order number: 300641-004us 8.10.8 offset gpiobase + 34h: gp_io_sel2?gpio input/output select 2 register 8.10.9 offset gpiobase + 38h: gp_lvl2?gpio level for input or output 2 register table 320. offset gpiobase + 34h: gp_io_sel2?gpio input/output select 2 register bits name description access 31:2 6 always 0. no corresponding gpio. 25:2 4 always 0. output only. 23:1 2 always 0. no corresponding gpio. 11:0 gp_io_sel2[43:32] when set to a 1, the corresponding gpio signal (when enabled in the gpio_use_sel2 register) is programmed as an input. when set to 0, the gpio signal is programmed as an output. implementation note: bits 26:31 may be in core well. table 321. offset gpiobase + 38h: gp_lvl2?gpio level for input or output 2 register bits name description access 31:2 6 reserved reserved. read-only 0. ro 25:2 4 gp_lvl[57:56] the gp_lvl[n] bit may be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. note: these output are open drain. setting this bit to one does not drive a ?1? but allows for an external pullup to cause a high value on the pin. since these bits correspond to gpio that are in the rtc well, these bits will be reset by rtcrst#. device: 31 function: 0 offset: gpiobase +34h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core for 23:0; resume for 31:24 device: 31 function: 0 offset: gpiobase +38h attribute: read/write default value: 00000fffh size: 32-bit lockable: no power well: core for 23:0, rtc for 31:24
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 433 8?intel ? 6300ESB ich 23:1 2 reserved reserved. read-only 0. ro 11:0 gp_lvl2[43:32] when gpio[n] is programmed to be an output (through the corresponding bit in the gp_io_sel2 register), the corresponding gp_lvl2[n] bit may be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. when gpio[n] is programmed as an input, then the corresponding gp_lvl2 bit reflects the state of the input signal (1 = high, 0 = low). writes will have no effect. since these bits correspond to gpio that are in the core well, these bits will be reset by pxpcirst#. implementation note: bits 26:31 may be in core well. table 321. offset gpiobase + 38h: gp_lvl2?gpio level for input or output 2 register bits name description access device: 31 function: 0 offset: gpiobase +38h attribute: read/write default value: 00000fffh size: 32-bit lockable: no power well: core for 23:0, rtc for 31:24
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intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 435 9?intel ? 6300ESB ich ide controller registers (d31:f1) 9 9.1 pci configuration registers (ide?d31:f1) note: registers that are not shown should be treated as reserved (see section 6.2, ?pci configuration map? for details). all of the ide registers are in the core well. none of the registers may be locked. table 322. pci configuration map (ide-d31:f1) offset mnemonic register name/function default type 00-01h vid vendor id 8086h ro 02-03h did device id 25a2h ro 04-05h cmd command 00h r/w 06-07h sts device status 0280h r/w 08h rid revision id 00h see note 1 ro 09h pi programming interface 8ah ro 0ah scc sub class code 01h ro 0bh bcc base class code 01h ro 0dh mlt master latency timer 00h ro 10-13h pcmd_bar primary command block base address 00000001h r/w 14-17h pcnl_bar primary control block base address 00000001h r/w 18-1bh scmd_bar secondary command block base address 00000001h r/w 1c-1fh scnl_bar secondary control block base address 00000001h r/w 20-23h bm_base bus master base address 00000001h r/w 24-27h cpba ide command posting base address 00000000h r/w 2c-2dh ide_svid subsystem vendor id 00h r/write-once 2e-2fh ide_sid subsystem id 00h r/write-once 3c intr_ln interrupt line 00h r/w 3d intr_pn interrupt pin 01h r/w 40-41h ide_tim primary ide timing 0000h r/w 42-43h id_tims secondary ide timing 0000h r/w 44h slv_idetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control 00h r/w 4a-4bh sdmatim synchronous dma timing 0000h r/w 54h ide_config ide i/o configuration 00h r/w notes: 1. see the intel ? 6300ESB ich specification update for the most up-to-date value of the revision id register. 2. the intel ? 6300ESB ich ide controller is not arbitrated as a pci device, therefore it does not need a master latency timer.
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 436 order number: 300641-004us 9.1.1 offset 00 - 01h: vid?vendor id register (lpc i/ f?d31:f1) 9.1.2 offset 02 - 03h: did?device id register (lpc i/ f?d31:f1) table 323. offset 00 - 01h: vid?vendor id register (lpc i/f?d31:f1) bits name description access 15:0 vendor id value this is a 16-bit value assigned to intel. intel vid = 8086h. table 324. offset 02 - 03h: did?device id register (lpc i/f?d31:f1) bits name description access device id this is a 16-bit value assigned to the intel ? 6300ESB ich ro device: 31 function: 1 offset: 00 - 01h attribute: read-only default value: 8086h size: 16-bit lockable: no power well: core device: 31 function: 1 offset: 02 - 03h attribute: read-only default value: 25a2h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 437 9?intel ? 6300ESB ich 9.1.3 offset 04h - 05h: cmd?command register (ide? d31:f1) table 325. offset 04h - 05h: cmd?command register (ide?d31:f1) bits name description access 15:1 1 reserved reserved. 10 interrupt disable (id) enables the p-ata host controller to assert the inta# (in native mode) or irq14/15 (in legacy mode). when set, the interrupt will be deasserted. when cleared, the interrupt may be asserted. 9 fast back to back enable (fbe) reserved as ?0?. ro 8 serr# enable reserved as ?0?. ro 7 wait cycle control reserved as ?0?. ro 6 parity error response reserved as ?0?. ro 5 vga palette snoop reserved as ?0?. ro 4 postable memory write enable (pmwe) reserved as ?0?. ro 3 special cycle enable (sce) reserved as ?0?. ro 2 bus master enable (bme) controls the intel ? 6300ESB ich?s ability to act as a pci master for ide bus master transfers. r/w 1 memory space enable (mse) 0 = disables access. 1 = enables access to the ide expansion memory range. the exbar register (offset 24h) must be programmed before this bit is set. note: bios should set this bit to a 1. r/w 0 iose - i/o space enable (iose) this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus master io registers. 1 = enable. the base address register for the bus master registers should be programmed before this bit is set. notes: 1. separate bits are provided (ide decode enable, in the ide timing register) to independently disable the primary or secondary i/o spaces. 2. when this bit is 0 and the ide controller is in native mode, the interrupt pin register will be masked (the interrupt will not be asserted) see section 10.1.16, ?offset 60h: usb_relnum?usb release number register (usb? d29:f0/f1)? for more information regarding the interrupt pin register. when an interrupt occurs while the masking is in place and the interrupt is still active when the masking ends, the interrupt will be allowed to be asserted. r/w device: 31 function: 1 offset: 04h-05h attribute: read-only, read/write default value: 00h size: 16-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 438 order number: 300641-004us 9.1.4 offset 06 - 07h: sts?device status register (ide?d31:f1) table 326. offset 06 - 07h: sts?device status register (ide?d31:f1) bits name description access 15 detected parity error (dpe) reserved as ?0?. ro 14 signaled system error (sse) reserved as ?0?. ro 13 received master-abort status (rma) 0 cleared by writing a 1 to it. bus master ide interface function, as a master, generated a master-abort. r/wc 12 reserved reserved as ?0? . ro 11 signaled target-abort status (sta) 0 = cleared by writing a 1 to it. 1 = the intel ? 6300ESB ich ide interface function is targeted with a transaction that the intel ? 6300ESB ich terminates with a target abort. r/wc 10:9 devsel# timing status (devt) 01 = hardwired; however, the intel ? 6300ESB ich does not have a real devsel# signal associated with the ide unit, so these bits have no effect. ro 8 data parity error detected reserved as ?0?. ro 7 fast back-to-back capable reserved as ?1?. ro 6 user definable features (udf) reserved as ?0?. ro 5 66 mhz capable reserved as ?0?. ro 4 capabilities list (cap) reserved as ?0? ro 3 interrupt status (is) reflects the state of interrupt at the input of the enable.disable circuit. this bit is a 1 when the interrupt is asserted. 1 = interrupt is asserted. 0 = interrupt has been cleared (independent of the state of the interrupt disable bit in the command register. ro 2:0 reserved reserved as ?0?. ro device: 31 function: 1 offset: 06-07h attribute: read/write clear, read-only default value: 0280h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 439 9?intel ? 6300ESB ich 9.1.5 offset 08h: rid?revision id register (ide? d31:f1) 9.1.6 offset 09h: pi?programming interface (ide? d31:f1) table 327. offset 08h: rid?revision id register (ide?d31:f1) bits name description access 7:0 revision id value refer to the intel ? 6300ESB ich specification update for the most up-to-date value of the revision id register. ro table 328. offset 09h: pi?programming interface (ide?d31:f1) bits name description access 7 this read-only bit is a 1 to indicate that the intel ? 6300ESB ich supports bus master operation 6:4 reserved reserved. will always return 0. 3sop_mode_cap this read-only bit is a 1 to indicate that the secondary controller supports both legacy and native modes. 2 sop_mode_sel this read-write bits determines the mode that the secondary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode 1pop_mode_cap this read-only bit is a 1 to indicate that the primary controller supports both legacy and native modes. 0pop_mode_sel this read-write bits determines the mode that the primary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode note: in the intel ? 6300ESB ich, this bit was read-only with a value of 0. device: 31 function: 1 offset: 08h attribute: read-only default value: see bit description size: 8-bit device: 31 function: 1 offset: 09h attribute: read/write default value: 8ah size: 8-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 440 order number: 300641-004us 9.1.7 offset 0ah: scc?sub class code (ide?d31:f1) table 329. offset 0ah: scc?sub class code (ide?d31:f1) bits name description access 7:0 sub class code 01h = ide device, in the context of a mass storage device. ro device: 31 function: 1 offset: 0ah attribute: read-only default value: 01h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 441 9?intel ? 6300ESB ich 9.1.8 offset 0bh: bcc?base class code (ide?d31:f1) 9.1.9 offset 0dh: mlt?master latency timer (ide? d31:f1) 9.1.10 offset 10h - 13h: pcmd_bar?primary command block base address register (ide?d31:f1) table 330. offset 0bh: bcc?base class code (ide?d31:f1) bits name description access 7:0 base class code 01 = mass storage device ro table 331. offset 0dh: mlt?master latency timer (ide?d31:f1) bits name description access 7:0 bus master latency hardwired to 00h. the ide controller is implemented internally, and is not arbitrated as a pci device, so it does not need a master latency timer. these bits are fixed at 0. ro table 332. offset 10h - 13h: pcmd_bar?primary command block base address register (ide?d31:f1) bits name description access 31:1 6 reserved reserved. 15:3 base address base address of the i/o space (8 consecutive i/o locations). r/w 2:1 reserved reserved. 0 resource type indicator (rte) this bit is set to one, indicating a request for io space. read- only. ro note: this 8-byte i/o space is used in native mode for the primary controller?s command block. device: 31 function: 1 offset: 0bh attribute: read-only default value: 01h size: 8-bit device: 31 function: 1 offset: 0dh attribute: read-only default value: 00h size: 8-bit device: 31 function: 1 offset: 10h-13h attribute: read/write default value: 00000001h size: 32-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 442 order number: 300641-004us 9.1.11 offset 14h - 17h: pcnl_bar?primary control block base address register (ide?d31:f1) 9.1.12 offset 18h - 1bh: scmd_bar?secondary command block base address register (ide d31:f1) table 333. offset 14h - 17h: pcnl_bar?primary control block base address register (ide?d31:f1) bits name description access 31:1 6 reserved reserved. 15:2 base address base address of the i/o space (4 consecutive i/o locations). r/w 1 reserved reserved. 0 resource type indicator (rte) this bit is set to one, indicating a request for io space. ro note: this 4-byte i/o space is used in native mode for the primary controller?s command block. table 334. offset 18h - 1bh: scmd_bar?secondary command block base address register (ide d31:f1) bits name description access 31:1 6 reserved reserved. 15:3 base address base address of the i/o space (8 consecutive i/o locations). r/w 2:1 reserved reserved. 0 resource type indicator (rte) this bit is set to one, indicating a request for io space. ro note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. device: 31 function: 1 offset: 14h-17h attribute: read-only default value: 00000001h size: 32-bit device: 31 function: 1 offset: 18h-1bh attribute: read/write default value: 00000001h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 443 9?intel ? 6300ESB ich 9.1.13 offset 1ch - 1fh: scnl_bar?secondary control block base address register (ide d31:f1) 9.1.14 offset 20h - 23h: bm_base?bus master base address register (ide?d31:f1) note: the bus master ide interface function uses base address register 5 to request a 16- byte io space to provide a software interface to the bus master functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. table 335. offset 1ch - 1fh: scnl_bar?secondary control block base address register (ide d31:f1) bits name description access 31:1 6 reserved reserved. 15:2 base address base address of the i/o space (4 consecutive i/o locations). r/w 1 reserved reserved. 0 resource type indicator (rte) this bit is set to one, indicating a request for io space. ro note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. table 336. offset 20h - 23h: bm_base?bus master base address register (ide?d31:f1) bits name description access 31:1 6 reserved reserved. 15:4 base address base address of the i/o space (16 consecutive i/o locations). 3:1 reserved reserved. 0 resource type indicator (rte) hardwired to?1?, indicating a request for io space. ro device: 31 function: 1 offset: 1ch - 1fh attribute: read/write default value: 00000001h size: 32-bit device: 31 function: 1 offset: 20h - 23h attribute: read/write default value: 00000001h size: 32-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 444 order number: 300641-004us 9.1.15 offset 24h - 27h: cpba ? ide command posting base address note: the intel ? 6300ESB ich requests 1 kbyte of memory space for the command posting accesses. this is much more than is needed; by requesting this much space, decoding may be simplified. in addition to the standard pci memory space enable bit, the command posting enable bits in the ide i/o configuration register must be set for the intel ? 6300ESB ich to properly decode the accesses to this range. table 337. offset 24h - 27h: cpba ? ide command posting base address bits name description access 31:1 0 base address base address of the ide command posting memory space (aligned to 1 kbyte). r/w 9:4 hardwired base address these bits are hardwired to ?0? to indicate that the size of the range requested is 1 kbyte. ro 3prefetchable hard-wired to ?0?, indicating that this range is not pre- fetchable. ro 2:1 type hard-wired to ?00?, indicating that this range may be mapped anywhere in 32-bit address space. ro 0 rte ? resource type indicator this bit is hard-wired to ?0?, indicating a request for memory space. ro device: 31 function: 1 offset: 24h-27h attribute: read/write default value: 00000000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 445 9?intel ? 6300ESB ich 9.1.16 offset 2ch - 2dh: ide_svid?subsystem vendor id (ide?d31:f1) table 338. offset 2ch - 2dh: ide_svid?subsystem vendor id (ide?d31:f1) bits name description access 15:0 subsystem vendor id (svid) the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value may be read, but subsequent writes to this register have no effect. the value written to this register will also be readable through the corresponding svid registers for the usb uhci #1, usb uhci #2, and smbus functions. note: write accesses to the svid register should only be done as 16-bit accesses. if two 8-bit write accesses are done, then the value in the register will not be correct. r/write-once device: 31 function: 1 offset: 2ch-2dh attribute: read/write once default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 446 order number: 300641-004us 9.1.17 offset 2eh - 2fh: ide_sid?subsystem id (ide? d31:f1) 9.1.18 offset 3ch: intr_ln?interrupt line register (ide?d31:f1) table 339. offset 2eh - 2fh: ide_sid?subsystem id (ide?d31:f1) bits name description access 15:0 subsystem id (sid) the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value may be read, but subsequent writes to this register have no effect. the value written to this register will also be readable through the corresponding sid registers for the usb uhci #1, usb uhci #2, and smbus functions. note: write accesses to the sid register should only be done as 16-bit accesses. if two 8-bit write accesses are done, then the value in the register will not be correct. r/write-once table 340. offset 3ch: intr_ln?interrupt line register (ide?d31:f1) bits name description access 7:0 interrupt line this data is not used by the intel ? 6300ESB ich. it is used to communicate to software the interrupt line which the interrupt pin is connected to. r/w device: 31 function: 1 offset: 2eh-2fh attribute: read/write once default value: 0000h size: 16-bit lockable: no power well: core device: 31 function: 1 offset: 3ch attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 447 9?intel ? 6300ESB ich 9.1.19 offset 3dh: intr_pn?interrupt pin register (ide?d31:f1) 9.1.20 ide_tim?ide timing register (ide?d31:f1) note: this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. table 341. offset 3dh: intr_pn?interrupt pin register (ide?d31:f1) bits name description access 7:3 reserved reserved. 2:0 interrupt pi the value of 01h indicates to ?software? that the intel ? 6300ESB ich will drive inta#. note that this is only used in native mode. also note that the routing to the internal interrupt controller does not necessarily relate to the value in this register. the ide interrupt is in fact routed to pirq[c]# (irq18 in apic mode). ro device: 31 function: 1 offset: 3dh attribute: read-only default value: 01h size: 8-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 448 order number: 300641-004us table 342. ide_tim?ide timing register (ide?d31:f1) (sheet 1 of 3) bits name description access 15 ide decode enable (ide) individually enable/disable the primary or secondary decode. the ide i/o space enable bit in the command register must be set in order for this bit to have any effect. additionally, separate configuration bits are provided (in the ide i/o configuration register) to individually disable the primary or secondary ide interface signals, even when the ide decode enable bit is set. 0 = disable. 1 = enables the intel ? 6300ESB ich to decode the associated command blocks (1f0-1f7h for primary, 170- 177h for secondary) and control block (3f6h for primary and 376h for secondary). this bit effects the ide decode ranges for both legacy and native-mode decoding. it also effects the corresponding primary or secondary memory decode range for ide expansion. r/w 14 drive 1 timing register enable (sitre) 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and use the slave ide timing register for drive 1 r/w 13:1 2 iordy sample point (isp) the setting of these bits determine the number of pci clocks between ide ior#/iow# assertion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 11 reserved reserved. device: 31 function: 1 offset: primary: 40-41h secondary: 42-43h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 449 9?intel ? 6300ESB ich 10 fast non-data pio (fndpio) software sets this read/write bit to 1 to enable the fast pio accesses for non data register accesses. when this bit is a 1, the timings for pio cycles to ide drive registers other than offset 170h or 1f0h will run using pio data timings. default for this bit is 0. this mode should only be enabled for udma- based ide protocols. when this bit is set to '1', bit 14 in this register (drive 1 timing register enable) must be either: '0' to force equivalent timings for both the master and slave devices, or '1' with equivalent timings programmed in the slave ide timing register. bits 7 and 3 in this register must be '0' in order to utilize this mode. likewise, bits 4 and 0 of this register must be programmed to '1'; bits 5 and 1 must be programmed to the same value. the timing parameters must, of course, be compatible with each of the devices on the channel. the two drives must be programmed for the same timings because some non-data register accesses must be received by both the master and slave devices simultaneously, and because different settings would result in timings that change in the middle of some of the non-data accesses. bits 13:12 and bits 9:8 determine the cycle timings. bits 6 and 2 do not apply to the non-data accesses.note that the non-data accesses are not posted, but that accesses to the data register may be posted. therefore, the non-data accesses may actually be limited by the access turn-around achievable on hub interface rather than the rct timing. 9:8 recovery time (rct) the setting of these bits determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock r/w 7 drive 1 dma timing enable (dte1) 0 = disable. 1 = enable the fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. r/w 6 drive 1 prefetch/posting enable (ppe1) 0 = disable. 1 = enable prefetch and posting to the ide data port for this drive. r/w 5 drive 1 iordy sample point enable (ie1) 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive. r/w table 342. ide_tim?ide timing register (ide?d31:f1) (sheet 2 of 3) bits name description access device: 31 function: 1 offset: primary: 40-41h secondary: 42-43h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 450 order number: 300641-004us 4 drive 1 fast timing bank (time1) 0 = accesses to the data port will use compatible timings for this drive. 1 = when this bit =?1? and bit 14 =?0?, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. when this bit =?1? and bit 14 =?1?, accesses to the data port will use the iordy sample point and recover time specified in the slave ide timing register. r/w 3 drive 0 dma timing enable (dte0) 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. r/w 2 drive 0 prefetch/posting enable (ppe0) 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. r/w 1 drive 0 iordy sample point enable (ie0) 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. r/w 0 drive 0 fast timing bank (time0) 0 = accesses to the data port will use compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time r/w table 342. ide_tim?ide timing register (ide?d31:f1) (sheet 3 of 3) bits name description access device: 31 function: 1 offset: primary: 40-41h secondary: 42-43h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 451 9?intel ? 6300ESB ich 9.1.21 offset 44h: slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) table 343. offset 44h: slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) bits name description access 7:6 secondary drive 1 iordy sample point (sisp1) determines the number of pci clocks between ide ior#/ iow# assertion and the first iordy sample point, when the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved r/w 5:4 secondary drive 1 recovery time (srct1) determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, when the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks r/w 3:2 primary drive 1 iordy sample point (pisp1) determines the number of pci clocks between ior#/iow# assertion and the first iordy sample point, when the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved r/w 1:0 primary drive 1 recovery time (prct1) determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, when the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks r/w device: 31 function: 1 offset: 44h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 452 order number: 300641-004us 9.1.22 offset 48h: sdma_cnt?synchronous dma control register (ide?d31:f1) table 344. offset 48h: sdma_cnt?synchronous dma control register (ide? d31:f1) bits name description access 7:4 reserved reserved. 3 secondary drive 1 synchronous dma mode enable (ssde1) 0 = disable (default) 1 = enable synchronous dma mode for secondary channel drive 1 r/w 2 secondary drive 0 synchronous dma mode enable (ssde0) 0 = disable (default) 1 = enable synchronous dma mode for secondary drive 0. r/w 1 primary drive 1 synchronous dma mode enable (psde1) 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 1 r/w 0 primary drive 0 synchronous dma mode enable (psde0) 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 0 r/w device: 31 function: 1 offset: 48h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 453 9?intel ? 6300ESB ich 9.1.23 offset 4a - 4bh: sdma_tim?synchronous dma timing register (ide?d31:f1) table 345. offset 4a - 4bh: sdma_tim?synchronous dma timing register (ide?d31:f1) (sheet 1 of 2) bits name description access 15:1 4 reserved reserved. 13:1 2 secondary drive 1 cycle time (sct1) for synchronous dma mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33 mhz clk ) 00 = ct 4 clocks, rp 6 clocks 01 = ct 3 clocks, rp 5 clocks 10 = ct 2 clocks, rp 4 clocks 11 = reserved scb1 = 1 (66 mhz clk) 00 = reserved 01 = ct 3 clocks, rp 8 clocks 10 = ct 2 clocks, rp 8 clocks 11 = reserved fast_scb1 = 1 (133 mhz clk ) 00 = reserved 01 = ct 3 clks, rp 16 clks 10 = reserved 11 = reserved r/w 11:1 0 reserved reserved. 9:8 secondary drive 0 cycle time (sct0) for synchronous dma mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33 mhz clk) 00 = ct 4 clocks, rp 6 clocks 01 = ct 3 clocks, rp 5 clocks 10 = ct 2 clocks, rp 4 clocks 11 = reserved scb1 = 1 (66 mhz clk) 00 = reserved 01 = ct 3 clocks, rp 8 clocks 10 = ct 2 clocks, rp 8 clocks 11 = reserved fast_scb1 = 1 (133 mhz clk) 00 = reserved 01 = ct 3 clks, rp 16 clks 10 = reserved 11 = reserved r/w 7:6 reserved reserved. device: 31 function: 1 offset: 4a - 4bh attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 454 order number: 300641-004us 5:4 primary drive 1 cycle time (pct1) f or synchronous dma mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33 mhz clk) 00 = ct 4 clocks, rp 6 clocks 01 = ct 3 clocks, rp 5 clocks 10 = ct 2 clocks, rp 4 clocks 11 = reserved pcb1 = 1 (66 mhz clk) 00 = reserved 01 = ct 3 clocks, rp 8 clocks 10 = ct 2 clocks, rp 8 clocks 11 = reserved fast_pcb1 = 1 (133 mhz clk) 00 = reserved 01 = ct 3 clks, rp 16 clks 10 = reserved 11 = reserved r/w 3:2 reserved reserved. 1:0 primary drive 0 cycle time (pct0) for synchronous dma mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33 mhz clk) 00 = ct 4 clocks, rp 6 clocks 01 = ct 3 clocks, rp 5 clocks 10 = ct 2 clocks, rp 4 clocks 11 = reserved pcb1 = 1 (66 mhz clk) 00 = reserved 01 = ct 3 clocks, rp 8 clocks 10 = ct 2 clocks, rp 8 clocks 11 = reserved fast_pcb1 = 1 (133 mhz clk) 00 = reserved 01 = ct 3 clks, rp 16 clks 10 = reserved 11 = reserved r/w table 345. offset 4a - 4bh: sdma_tim?synchronous dma timing register (ide?d31:f1) (sheet 2 of 2) bits name description access device: 31 function: 1 offset: 4a - 4bh attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 455 9?intel ? 6300ESB ich 9.1.24 ide_config?ide i/o configuration register (ide?d31:f1) 9.2 bus master ide i/o registers (d31:f1) the bus master ide function uses 16 bytes of i/o space, allocated through the bmiba register, located in device 31:function 1 configuration space, offset 20h. all bus master ide i/o space registers may be accessed as byte, word, or dword quantities. reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no effect, but should not be attempted. the description of the i/o registers is shown below in table 347 . table 346. ide_config?ide i/o configuration register (ide?d31:f1) bits name description access 31 enable prefetch and posting registers (eppr) until this bit is set, the ppe1 and ppe0 bits in the ide timing register (bits 6 and 2 of offset 40h for primary, and bits 6 and 2 of offset 42h for secondary) are ignored by the pio prefetch and posting hardware. therefore, even if those bits are set, pio posting and prefetching will not occur until this bit is set. r/w 30:0 reserved reserved. device: function: 1 offset: 54h attribute: r/w default value: 00h size: 32-bit table 347. bus master ide i/o registers offset mnemonic register default type 00 bmicp command register primary 00h r/w 01 reserved 00h ro 02 bmisp status register primary 00h r/wc 03 reserved 00h ro 04-07 bmidp descriptor table pointer primary xxxxxxxxh r/w 08 bmics command register secondary 00h r/w 09 reserved 00h ro 0a bmiss status register secondary 00h r/wc 0b reserved 00h ro 0c-0f bmids descriptor table pointer secondary xxxxxxxxh r/w
9? intel ? 6300ESB ich intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 456 9.2.1 bmic[p,s]?bus master ide command register table 348. bmic[p,s]?bus master ide command register bits name description access 7:4 reserved reserved. returns ?0?. 3 read / write control (rwc) this bit sets the direction of the bus master transfer: this bit must not be changed when the bus master function is active. 0 = memory reads 1 = memory writes r/w 2:1 reserved reserved. returns ?0?. 0 start/stop bus master (start) 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. when this bit is reset while bus master operation is still active (i.e., the bus master ide active bit of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bit in the bus master ide status register for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controller. bus master operation begins when this bit is detected changing from a zero to a one. the controller will transfer data between the ide device and memory only when this bit is set. master operation may be halted by writing a '0' to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bus master ide active bit being cleared or the interrupt bit of the bus master ide status register for that ide channel being set, or both. hardware does not clear this bit automatically. r/w device: 31 function: 1 offset: primary: 00h secondary: 08h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 457 9?intel ? 6300ESB ich 9.2.2 bmis[p,s]?bus master ide status register table 349. bmis[p,s]?bus master ide status register bits name description access 7 prd_int_sts the intel ? 6300ESB ich sets this bit when it completes execution of a prd that has its prd_int bit set. this bit is cleared by software writing a 1 to this bit position. when this bit is cleared, the interrupt is cleared. note that there is a small window where the intel ? 6300ESB ich completes execution of a prd, but the interrupt service routine does not clear this bit until the next prd has completed. in that case, there is a small probability that the interrupt associated with the subsequent prd is lost. software must be written to not break in this case. r/w 6 drive 1 dma capable 0 = not capable. 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 1 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the intel ? 6300ESB ich does not use this bit. it is intended for systems that do not attach bmide to the pci bus. r/w 5 drive 0 dma capable 0 = not capable 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 0 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the intel ? 6300ESB ich does not use this bit. it is intended for systems that do not attach bmide to the pci bus. r/w 4:3 reserved reserved. returns ?0?. device: 31 function: 1 offset: primary: 02h secondary: 0ah attribute: read/write clear default value: 00h size: 8-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 458 order number: 300641-004us 2interrupt software may use this bit to determine if an ide device has asserted its interrupt line (irq 14 for the primary channel, and irq 15 for secondary). 0 = this bit is cleared by software writing a '1' to the bit position. when this bit is cleared while the interrupt is still active, this bit will remain clear until another assertion edge is detected on the interrupt line. 1 = set by the rising edge of the ide interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal i/o apic. when this bit is read as a one, all data transferred from the drive is visible in system memory. r/wc 1error 0 = this bit is cleared by software writing a '1' to the bit position. 1 = this bit is set when the controller encounters a target abort or master abort when transferring data on pci. r/wc 0 bus master ide active (act) 0 = this bit is cleared by the intel ? 6300ESB ich when the last transfer for a region is performed, where eot for that region is set in the region descriptor. it is also cleared by the intel ? 6300ESB ich when the start bit is cleared in the command register. when this bit is read as a zero, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the intel ? 6300ESB ich when the start bit is written to the command register. ro table 349. bmis[p,s]?bus master ide status register bits name description access device: 31 function: 1 offset: primary: 02h secondary: 0ah attribute: read/write clear default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 459 9?intel ? 6300ESB ich 9.2.3 bmid[p,s]?bus master ide descriptor table pointer register note: when this register is read, the current value of the pointer is returned. the intel ? 6300ESB ich does not return the original base value of the pointer once one or more descriptors have been executed. this capability is useful for enabling low-cost disk drives. table 350. bmid[p,s]?bus master ide descriptor table pointer register bits name description access 31:2 address of descriptor ta b l e ( a d d r ) corresponds to a[31:2]. the descriptor table must be dword-aligned. the descriptor table must not cross a 64 k boundary in memory. r/w 1:0 reserved reserved. device: 31 function: 1 offset: primary: 04h secondary: 0ch attribute: read/write default value: all bits undefined size: 32-bit
intel ? 6300ESB ich?9 intel ? 6300ESB i/o controller hub ds november 2007 460 order number: 300641-004us
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 461 10?intel ? 6300ESB ich usb uhci controllers registers 10 10.1 pci configuration registers (d29:f0/f1) note: registers that are not shown should be treated as reserved (see section 6.2, ?pci configuration map? for details). table 351. pci configuration map (usb?d29:f0/f1) offset mnemonic register name/ function function 0 default function 1 default type 00-01h vid vendor id 8086h 8086h ro 02-03h did device id 25a9h 25aah ro 04-05h cmd command register 0000h 0000h r/w 06-07h sta device status 0280h 0280h r/w 08h rid revision id see note: see note: ro 09h pi programming interface 00h 00h ro 0ah scc sub class code 03h 03h ro 0bh bcc base class code 0ch 0ch ro odh mlt master latency timer 00h 00h r/w 0eh htype header type 80h 00h ro 20-23h base base address register 00000001h 00000001h r/w 2c-2dh svid subsystem vendor id 00 00 ro 2e-2fh sid subsystem id 00 00 ro 3ch intr_ln interrupt line 00h 00h r/w 3dh intr_pn interrupt pin 01h 02h ro 60h usb_relnum usb release number 10h 10 ro c0-c1h usb_legkey usb legacy keyboard/ mouse control 2000h 2000h r/w c4h usb_res usb resume enable 00h 00h r/w note: refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to- date value of the revision id register.
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 462 order number: 300641-004us 10.1.1 offset 00 - 01h: vid?vendor identification register (usb?d29:f0/f1) 10.1.2 offset 02 - 03h: did?device identification register (usb?d29:f0/f1) table 352. offset 00 - 01h: vid?vendor identification register (usb?d29:f0/ f1) bits name description access 15:0 vendor id value this is a 16-bit value assigned to intel. ro table 353. offset 02 - 03h: did?device identification register (usb?d29:f0/ f1) bits name description access 15:0 device id value this is a 16-bit value assigned to the intel ? 6300ESB ich usb host controllers. ro device: 29 function: 0/1 offset: 00 - 01h attribute: read-only default value: 8086h size: 16-bit device: 29 function: 0/1 offset: 02-03h attribute: read-only default value: function 0: 25a9h function 1: 25aah size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 463 10?intel ? 6300ESB ich 10.1.3 offset 04 - 05h: cmd?command register (usb?d29:f0/f1) table 354. offset 04 - 05h: cmd?command register (usb?d29:f0/f1) bits name description access 15:1 0 reserved reserved. ro 9 fast back-to-back enable (fbe) reserved as ?0?. ro 8 serr# enable reserved as ?0?. ro 7 wait cycle control reserved as ?0?. ro 6 parity error response reserved as ?0?. ro 5 vga palette snoop reserved as ?0?. ro 4 postable memory write enable (pmwe) reserved as ?0?. ro 3 special cycle enable (sce) reserved as ?0?. ro 2 bus master enable (bme) when set, the intel ? 6300ESB ich may act as a master on the pci bus for usb transfers. r/w 1 memory space enable (mse) reserved as ?0?. ro 0 i/o space enable (iose) this bit controls access to the i/o space registers. 0 = disable 1 = enable accesses to the usb i/o registers. the base address register for usb should be programmed before this bit is set. r/w device: 29 function: 0/1 offset: 04-05h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 464 order number: 300641-004us 10.1.4 offset 06 - 07h: sta?device status register (usb?d29:f0/f1) 10.1.5 offset 08h: rid?revision identification register (usb?d29:f0/f1) table 355. offset 06 - 07h: sta?device status register (usb?d29:f0/f1) bits name description access 15:1 4 reserved reserved as ?00b?. ro 13 received master-abort status (rma) 0 = software clears this bit by writing a ?1? to the bit location. 1 = usb, as a master, generated a master-abort. r/wc 12 reserved reserved. always read as ?0?. ro 11 signaled target-abort status (sta) 0 = software clears this bit by writing a ?1? to the bit location. 1 = usb function is targeted with a transaction that the intel ? 6300ESB ich terminates with a target abort. r/wc 10:9 devsel# timing status (devt) this 2-bit field defines the timing for devsel# assertion. these read only bits indicate the intel ? 6300ESB ich's devsel# timing when performing a positive decode. the intel ? 6300ESB ich generates devsel# with medium timing for usb. ro 8 data parity error detected reserved as ?0?. ro 7 fast back-to-back capable reserved as ?1?. ro 6 user definable features (udf) reserved as ?0?. ro 5 66 mhz capable reserved as ?0?. ro 4:0 reserved reserved. ro table 356. offset 08h: rid?revision identification register (usb?d29:f0/f1) bits name description access 7:0 revision id value refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. ro device: 29 function: 0/1 offset: 06 - 07h attribute: read/write clear default value: 0280h size: 16-bit device: 29 function: 0/1 offset: 08h attribute: read-only default value: see bit description size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 465 10?intel ? 6300ESB ich 10.1.6 offset 09h: pi?programming interface (usb? d29:f0/f1) 10.1.7 offset 0ah: scc?sub class code register (usb?d29:f0/f1) 10.1.8 offset 0bh: bcc?base class code register (usb?d29:f0/f1) 10.1.9 offset 0dh: mlt?master latency timer note: since the usb controller is internally implemented with arbitration through the hub interface, not pci, it does not need a master latency timer. the bits are fixed at ?0?. table 357. offset 09h: pi?programming interface (usb?d29:f0/f1) bits name description access 7:0 programming interface 00h = no specific register level programming interface defined. ro table 358. offset 0ah: scc?sub class code register (usb?d29:f0/f1) bits name description access 7:0 sub class code 03h = universal serial bus host controller. ro table 359. offset 0bh: bcc?base class code register (usb?d29:f0/f1) bits name description access 7:0 base class code 0ch = serial bus controller. ro device: 29 function: 0/1 offset: 09h attribute: read-only default value: 00h size: 8-bit device: 29 function: 0/1 offset: 0ah attribute: read-only default value: 03h size: 8-bit device: 29 function: 0/1 offset: 0bh attribute: read-only default value: 0ch size: 8-bit
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 466 order number: 300641-004us 10.1.10 offset 0eh: htype?header type register (usb?d29:f0/f1) note: for function 1, this register is hard-wired to 00h. for function 0, bit 7 is determined by the values in bits 15 and 9 of the function disable register (d31:f0:f2h). table 360. offset 0dh: mlt?master latency timer bits name description access mlt these bits are fixed at ?0?. table 361. offset 0eh: htype?header type register (usb?d29:f0/f1) bits name description access 7 multi-function bit multi-function device ? ro. 0 = single-function device. 1 = multi-function device. since the upper functions in this device can be individually hidden, this bit is based on the function-disable bits in device 31, function 0, offset f2h as follows: d29:f0 d29:f1 multi-function (bit 15) (bit 9) bit 0x 1 x x 1 x 0 1 11 0 6:0 configuration layout hardwired to 00h, which indicates the standard pci configuration layout. device: 29 function: 0/1 offset: 0dh attribute: read-only default value: 00h size: 8-bit device: 29 function: 0/1 offset: 0eh attribute: read-only default value: fn 0: 80h fn 1: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 467 10?intel ? 6300ESB ich 10.1.11 offset 20 - 23h: base?base address register (usb?d29:f0/f1) 10.1.12 offset 2ch - 2dh: svid?subsystem vendor id (usb?d29:f0/f1) table 362. offset 20 - 23h: base?base address register (usb?d29:f0/f1) bits name description access 31:1 6 reserved reserved. 15:5 base address bits [15:5] correspond to i/o address signals ad [15:5], respectively. this gives 32 bytes of relocatable i/o space. r/w 4:1 reserved reserved. 0 resource type indicator (rte) this bit is hardwired to ?1?, indicating that the base address field in this register maps to i/o space. ro table 363. offset 2ch - 2dh: svid?subsystem vendor id (usb?d29:f0/f1) bits name description access 15:0 subsystem vendor id (svid) the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide_svid register. ro device: 29 function: 0/1 offset: 20-23h attribute: read/write default value: 00000001h size: 32-bit device: 29 function: 0/1 offset: 2ch - 2dh attribute: read-only default value: 00h size: 16-bit
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 468 order number: 300641-004us 10.1.13 offset 2eh-2fh: sid?subsystem id (usb? d29:f0/f1) 10.1.14 offset 3ch: intr_ln?interrupt line register (usb?d29:f0/f1) table 364. offset 2eh-2fh: sid?subsystem id (usb?d29:f0/f1) bits name description access 15:0 subsystem id (sid) the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide_sid register. r/wo table 365. offset 3ch: intr_ln?interrupt line register (usb?d29:f0/f1) bits name description access 7:0 interrupt line this data is not used by the intel ? 6300ESB ich. it is to communicate to software the in terrupt line that the interrupt pin is connected to. r/w device: 29 function: 0/1 offset: 2eh - 2fh attribute: read-only default value: 00h size: 16-bit device: 29 function: 0/1 offset: 3ch attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 469 10?intel ? 6300ESB ich 10.1.15 offset 3dh: intr_pn?interrupt pin register (usb?d29:f0/f1) 10.1.16 offset 60h: usb_relnum?usb release number register (usb?d29:f0/f1) 10.1.17 offset c0 - c1h: usb_legkey?usb legacy keyboard/ mouse control register (usb?d29:f0/f1) note: this register is implemented separately in each of the usb uhci functions. however, the enable and status bits for the trapping logic are or?d and shared, respectively, since their functionality is not specific to any one host controller. see section 19.6, ?logical device 7 (07h): port 60/64 emulation? for details on the relationship between the same bits in each of the host controllers. system software should ensure that the host controller and an external pci agent are not simultaneously executing a keyboard sequence to port 60h and 64h. this event is not supported, and the results will be indeterminate. table 366. offset 3dh: intr_pn?interrupt pin register (usb?d29:f0/f1) bits name description access 7:3 reserved reserved. ro 2:0 interrupt pin the values of 01h and 02h, in function 0 and 1, respectively, indicate to software that the corresponding intel ? 6300ESB ich classic usb controllers drive the inta# and intb# pci signals. note that this does not determine the mapping to the intel ? 6300ESB ich pirq inputs. function 0 will drive pirqa. function 1 will drive pirqd. function 1 does not use the corresponding mapping in order to spread the interrupts with ac?97, which has historically been mapped to pirqb ro table 367. offset 60h: usb_relnum?usb release number register (usb? d29:f0/f1) bits name description access 7:0 serial bus release number 10h = indicates that the usb controller is compliant with the usb specification, release 1.0 . ro device: 29 function: 0/1 offset: 3dh attribute: read-only default value: function 0: 01h function 1: 02h size: 8-bit device: 29 function: 0/1 offset: 60h attribute: read-only default value: 10h size: 8-bit
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 470 order number: 300641-004us table 368. offset c0 - c1h: usb_legkey?usb legacy keyboard/ mouse control register (usb?d29:f0/f1) (sheet 1 of 3) bits name description access 15 smi caused by end of pass-through (smiby- endps) indicates if the event occurred. note that even when the corresponding enable bit is not set in bit 7, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a ?1? to the bit location in any of the controllers. 1 = event occurred r/wc 14 reserved reserved. 13 pci interrupt enable (usbpirqen) used to prevent the usb controller from generating an interrupt due to transactions on its ports. when disabled, it will be configured to generate an smi using bit 4 of this register. default to ?1? for compatibility with older usb software. 0 = disable 1 = enable r/w 12 smi caused by usb interrupt (smibyusb) indicates if an interrupt event occurred from this controller. the interrupt from the controller is taken before the enable in bit 13 has any effect to create this read-only bit. note that even when the corresponding enable bit is not set in the bit 4, this bit may still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software should clear the interrupts through the usb controllers. writing a ?1? to this bit will have no effect. 1 = event occurred. ro 11 smi caused by port 64 write (trapby64w) indicates if the event occurred. note that even when the corresponding enable bit is not set in the bit 3, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a ?1? to the bit location in any of the controllers. 1 = event occurred. note: if bit 7 of the etr1 (d31:f0, offset f4h etr1) is set. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. port 64 writes initiated from an external pci agent will not set this bit. r/wc 10 smi caused by port 64 read (trapby64r) indicates if the event occurred. note that even when the corresponding enable bit is not set in the bit 2, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a ?1? to the bit location in any of the controllers. 1 = event occurred. note: if bit 7 of the etr1 (d31:f0, offset f4h etr1) is set. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. port 64 reads initiated from an external pci agent will not set this bit. r/wc device: 29 function: 0/1 offset: c0-c1h attribute: read/write default value: 2000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 471 10?intel ? 6300ESB ich 9 smi caused by port 60 write (trapby60w) indicates if the event occurred. note that even when the corresponding enable bit is not set in the bit 1, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a ?1? to the bit location in any of the controllers. 1 = event occurred. note: if bit 7 of the etr1 (d31:f0, offset f4h etr1) is set. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. port 60 writes initiated from an external pci agent will not set this bit. r/wc 8 smi caused by port 60 read (trapby60r) indicates if the event occurred. note that even when the corresponding enable bit is not set in the bit 0, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a ?1? to the bit location in any of the controllers. 1 = event occurred. note: if bit 7 of the etr1 (d31:f0, offset f4h etr1) is set. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. port 60 reads initiated from an external pci agent will not set this bit. r/wc 7 smi at end of pass- through enable (smiatendps) may need to cause smi at the end of a pass-through. may occur when an smi is generated in the middle of a pass through and needs to be serviced later. 0 = disable 1 = enable r/w 6 pass-through state (pstate) 0 = when software needs to reset this bit, it should set bit 5 in all of the host controllers to 0. 1 = indicates that the state machine is in the middle of an a20gate pass-through sequence. ro 5 a20gate pass-through enable (a20passen) 0 = disable. 1 = allows a20gate sequence pass-through function. a specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the smi status bits. r/w 4 smi on usb irq enable (usbsmien) 0 = disable 1 = usb interrupt will cause an smi event. r/w 3 smi on port 64 writes enable (64wen) 0 = disable 1 = a ?1? in bit 11 will cause an smi event. note: if bit 7 of the etr1 (d31:f0, offset f4h etr1) is set. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. port 64 writes initiated from an external pci agent will not set this bit. r/w table 368. offset c0 - c1h: usb_legkey?usb legacy keyboard/ mouse control register (usb?d29:f0/f1) (sheet 2 of 3) bits name description access device: 29 function: 0/1 offset: c0-c1h attribute: read/write default value: 2000h size: 16-bit
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 472 order number: 300641-004us 10.1.18 offset c4h: usb_res?usb resume enable register (usb?d29:f0/f1) note: this register is in the resume well. 2 smi on port 64 reads enable (64ren) 0 = disable 1 = a ?1? in bit 10 will cause an smi event. note: if bit 7 of the etr1 (d31:f0, offset f4h etr1) is set. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. port 64 reads initiated from an external pci agent will not set this bit. r/w 1 smi on port 60 writes enable (60wen) 0 = disable 1 = a ?1? in bit 9 will cause an smi event. note: if bit 7 of the etr1 (d31:f0, offset f4h etr1) is set. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. port 60 writes initiated from an external pci agent will not set this bit. r/w 0 smi on port 60 reads enable (60ren) 0 = disable 1 = a ?1? in bit 8 will cause an smi event. note: if bit 7 of the etr1 (d31:f0, offset f4h etr1) is set. see section 8.1.37, ?offset f4: etr1?pci-x extended features register (lpc i/f?d31:f0)? for more information. port 60 reads initiated from an external pci agent will not set this bit. r/w table 369. offset c4h: usb_res?usb resume enable register (usb?d29:f0/ f1) bits name description access 7:2 reserved reserved. 1port1en 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/disconnect events r/w 0port0en 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/disconnect events. r/w table 368. offset c0 - c1h: usb_legkey?usb legacy keyboard/ mouse control register (usb?d29:f0/f1) (sheet 3 of 3) bits name description access device: 29 function: 0/1 offset: c0-c1h attribute: read/write default value: 2000h size: 16-bit device: 29 function: 0/1 offset: c4h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 473 10?intel ? 6300ESB ich 10.2 usb i/o registers some of the read/write register bits that deal with changing the state of the usb hub ports function so that, on read-back, they reflect the current state of the port, and not necessarily the state of the last write to the register. this allows the software to poll the state of the port and wait until it is in the proper state before proceeding. a host controller reset, global reset, or port reset will immediately terminate a transfer on the affected ports and disable the port. this affects the usbcmd register, bit [4] and the portsc registers, bits [12,6,2]. see individual bit descriptions for more detail. 10.2.1 offset 00 - 01h: usbcmd?usb command register note: the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. the table following the bit description provides additional information on the operation of the run/stop and debug bits. table 370. usb i/o registers offset mnemonic register default type 00-01 usbcmd usb command register 0000h r/w* 02-03 usbsta usb status register 0020h r/wc 04-05 usbintr interrupt enable 0000h r/w 06-07 frnum frame number 0000h r/w (see note: ) 08-0b frbaseadd frame list base address undefined r/w 0c sofmod start of frame modify 40h r/w 0d-0f reserved 0 ro 10-11 portsc0 port 0 status/control 0080h r/wc (see note: ) 12-13 portsc1 port 1 status/control 0080h r/wc (see note: ) 14-17 reserved 0 ro note: these registers are word writable only. byte writes to these registers have unpredictable effects.
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 474 order number: 300641-004us table 371. offset 00 - 01h: usbcmd?usb command register (sheet 1 of 3) bits name description access 15:7 reserved reserved. 8 loop back test mode 0 = disable loop back test mode. 1 = the intel ? 6300ESB ich is in loop back test mode. when both ports are connected together, a write to one port will be seen on the other port, and the data will be stored in i/o offset 18h. r/w 7 max packet (maxp) this bit selects the maximum packet size that may be used for full-speed bandwidth reclamation at the end of a frame. this value is used by the host controller to determine whether it should initiate another transaction based on the time remaining in the sof counter. use of reclamation packets larger than the programmed size will cause a babble error when executed during the critical window at frame end. the babble error results in the offending endpoint being stalled. software is responsible for ensuring that any packet that could be executed under bandwidth reclamation be within this size limit. 0 = 32 bytes 1 = 64 bytes r/w 6 configure flag (cf) this bit has no effect on the hardware. it is provided only as a semaphore service for software. 0 = indicates that software has not completed host controller configuration. 1 = hcd software sets this bit as the last action in its process of configuring the host controller. r/w 5 software debug (swdbg) the swdbg bit must only be manipulated when the controller is in the stopped state. this may be determined by checking the hchalted bit in the usbsts register. 0 = normal mode. 1 = debug mode. in sw debug mode, the host controller clears the run/stop bit after the completion of each usb transaction. the next transaction is executed when software sets the run/stop bit back to ?1?. r/w 4 force global resume (fgr) 0 = software resets this bit to ?0? after 20 ms has elapsed to stop sending the global resume signal. at that time, all usb devices should be ready for bus activity. the ?1? to ?0? transition causes the port to send a low speed eop signal. this bit will remain a ?1? until the eop has completed. 1 = host controller sends the global resume signal on the usb and sets this bit to ?1? when a resume event (connect, disconnect, or k-state) is detected while in global suspend mode. r/w device: 29 function: 0/1 offset: 00-01h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 475 10?intel ? 6300ESB ich 3 enter global suspend mode (egsm) 0 = software resets this bit to ?0? to come out of global suspend mode. software writes this bit to ?0? at the same time that force global resume (bit 4) is written to ?0? or after writing bit 4 to 0. 1 = host controller enters the global suspend mode. no usb transactions occur during this time. the host controller is able to receive resume signals from usb and interrupt the system. software must ensure that the run/stop bit (bit 0) is cleared prior to setting this bit. r/w table 371. offset 00 - 01h: usbcmd?usb command register (sheet 2 of 3) bits name description access device: 29 function: 0/1 offset: 00-01h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 476 order number: 300641-004us 2 global reset (greset) 0 = this bit is reset by the software after a minimum of 10 ms has elapsed as specified in chapter 7 of the usb specification. 1 = global reset. the host controller sends the global reset signal on the usb and then resets all its logic, including the internal hub registers. the hub registers are reset to their power on state. chip hardware reset has the same effect as global reset (bit 2), except that the host controller does not send the global reset on usb. r/w 1 host controller reset (hcreset) the effects of hcreset on hub registers are slightly different from chip hardware reset and global usb reset. the hcreset affects bits [8,3:0] of the port status and control register (portsc) of each port. hcreset resets the state machines of the host controller including the connect/ disconnect state machine (one for each port). when the connect/disconnect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. this virtual disconnect causes the port to be disabled. this disconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the portsc to get set. the disconnect also causes bit 8 of portsc to reset. about 64 bit times after hcreset goes to ?0?, the connect and low-speed detect will take place, and bits 0 and 8 of the portsc will change accordingly. 0 = reset by the host controller when the reset process is complete. 1 = reset. when this bit is set, the host controller module resets its internal timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. r/w 0 run/stop (rs) when set to ?1?, the intel ? 6300ESB ich proceeds with execution of the schedule. the intel ? 6300ESB ich continues execution as long as this bit is set. when this bit is cleared, the intel ? 6300ESB ich completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. the host controller clears this bit when the following fatal errors occur: consistency check failure, pci bus errors. 0 = stop 1 = run note: this bit should only be cleared when there are no active transaction descriptors in the executable schedule or software will reset the host controller prior to setting this bit again. r/w table 371. offset 00 - 01h: usbcmd?usb command register (sheet 3 of 3) bits name description access device: 29 function: 0/1 offset: 00-01h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 477 10?intel ? 6300ESB ich when the usb host controller is in software debug mode (usbcmd register bit 5=1), the single stepping software debug operation is as follows: to enter software debug mode: 1. hcd puts host controller in stop state by setting the run/stop bit to ?0?. 2. hcd puts host controller in debug mode by setting the swdbg bit to ?1?. 3. hcd sets up the correct command list and start of frame value for starting point in the frame list single step loop. 4. hcd sets run/stop bit to ?1?. 5. host controller executes next active td, sets run/stop bit to ?0? and stops. 6. hcd reads the usbcmd register to check if the single step execution is completed (hchalted = 1). 7. hcd checks results of td execution. go to step 4 to execute next td or step 8 to end software debug mode. 8. hcd ends software debug mode by setting swdbg bit to ?0?. 9. hcd sets up normal command list and frame list table. 10. hcd sets run/stop bit to ?1? to resume normal schedule execution. in software debug mode, when the run/stop bit is set, the host controller starts. when a valid td is found, the run/stop bit is reset. when the td is finished, the hchalted bit in the usbsts register (bit 5) is set. the sw debug mode skips over inactive tds and only halts after an active td has been executed. when the last active td in a frame has been executed, the host controller waits until the next sof is sent and then fetches the first td of the next frame before halting. this hchalted bit may also be used outside of software debug mode to indicate when the host controller has detected the run/stop bit and has completed the current transaction. outside of the software debug mode, setting the run/stop bit to ?0? table 372. run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation swdbg (bit 5) run/stop (bit 0) description 00 when executing a command, the host controller completes the command and then stops. the 1.0 ms frame counter is reset and command list execution resumes from start of frame using the frame list pointer selected by the current value in the frnum register. (while run/stop = 0, the frnum register may be reprogrammed). 01 execution of the command list resumes from start of frame using the frame list pointer selected by the current value in the frnum register. the host controller remains running until the run/stop bit is cleared (by software or hardware). 10 when executing a command, the host controller completes the command and then stops and the 1.0 ms frame counter is frozen at its current value. all statuses are preserved. the host controller begins execution of the command list from where it left off when the run/stop bit is set. 11 execution of the command list resumes from where the previous execution stopped. the run/stop bit is set to ?0? by the host controller when a td is being fetched. this causes the host controller to stop again after the execution of the td (single step). when the host controller has completed execution, the hc halted bit in the status register is set.
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 478 order number: 300641-004us always resets the sof counter so that when the run/stop bit is set, the host controller starts over again from the frame list location pointed to by the frame list index (see frnum register description) rather than continuing where it stopped. 10.2.2 offset 02 - 03h: usbsta?usb status register note: this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. software sets a bit to ?0? in this register by writing a ?1? to it. table 373. offset 02 - 03h: usbsta?usb status register (sheet 1 of 2) bits name description access 15:6 reserved reserved. 5hchalted 0 = software resets this bit to ?0? by writing a ?1? to the bit position. 1 = the host controller has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (debug mode or an internal error). default. r/wc 4 host controller process error 0 = software resets this bit to ?0? by writing a ?1? to the bit position. 1 = the host controller has detected a fatal error. this indicates that the host controller suffered a consistency check failure while processing a transfer descriptor. an example of a consistency check failure would be finding an illegal pid field while processing the packet header portion of the td. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further schedule execution. a hardware interrupt is generated to the system. r/wc 3host system error 0 = software resets this bit to ?0? by writing a ?1? to the bit position. 1 = a serious error occurred during a host system access involving the host controller module. in a pci system, conditions that set this bit to ?1? include pci parity error, pci master abort, and pci target abort. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system. r/wc device: 29 function: x offset: 02 - 03h attribute: rea/write clear default value: 0020h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 479 10?intel ? 6300ESB ich 10.2.3 offset base + (04 - 05h): usbintr?interrupt enable register note: this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. fatal errors (host controller processor error-bit 4, usbsts register) cannot be disabled by the host controller. interrupt sources that are disabled in this register still appear in the status register to allow the software to poll for events. 2 resume detect (rsm_det) 0 = software resets this bit to ?0? by writing a ?1? to the bit position. 1 = the host controller received a ?resume? signal from a usb device. this is only valid when the host controller is in a global suspend state (bit 3 of command register = 1). r/wc 1 usb error interrupt 0 = software resets this bit to ?0? by writing a ?1? to the bit position. 1 = completion of a usb transaction resulted in an error condition (e.g., error counter underflow). when the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit ?0? are set. r/wc 0 usb interrupt (usbint) 0 = software resets this bit to ?0? by writing a ?1? to the bit position. 1 = the host controller sets this bit when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. also set when a short packet is detected (actual length field in td is less than maximum length field in td) and short packet detection is enabled in that td. r/wc table 374. offset base + (04 - 05h): usbintr?interrupt enable register (sheet 1 of 2) bits name description access 15:5 reserved reserved. 4 scratchpad scratchpad. r/w 3 short packet interrupt enable 0 = disabled. 1 = enabled. r/w table 373. offset 02 - 03h: usbsta?usb status register (sheet 2 of 2) bits name description access device: 29 function: x offset: 02 - 03h attribute: rea/write clear default value: 0020h size: 16-bit device: 29 function: x offset: base + (04-05h) attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 480 order number: 300641-004us 2 interrupt on complete (ioc) enable 0 = disabled. 1 = enabled. r/w 1 resume interrupt enable 0 = disabled. 1 = enabled. r/w 0 timeout/crc interrupt enable 0 = disabled. 1 = enabled. r/w table 374. offset base + (04 - 05h): usbintr?interrupt enable register (sheet 2 of 2) bits name description access device: 29 function: x offset: base + (04-05h) attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 481 10?intel ? 6300ESB ich 10.2.4 offset base + (06 - 07h): frnum?frame number register note: bits [10:0] of this register contain the current frame number included in the frame sof packet. this register reflects the count value of the internal frame number counter. bits [9:0] are used to select a particular entry in the frame list during scheduled execution. this register is updated at the end of each frame time. note: this register must be written as a word. byte writes are not supported. this register cannot be written unless the host controller is in the stopped state as indicated by the hchalted bit (usbsts register). a write to this register while the run/stop bit is set (usbcmd register) is ignored. 10.2.5 offset base + (08 - 0bh): frbaseadd?frame list base address note: this 32-bit register contains the beginning address of the frame list in the system memory. hcd loads this register prior to starting the schedule execution by the host controller. when written, only the upper 20 bits are used. the lower 12 bits are written as ?0? (4-kbyte alignment). the contents of this register are combined with the frame number counter to enable the host controller to step through the frame list in sequence. the two least significant bits are always 00. this requires dword alignment for all list entries. this configuration supports 1024 frame list entries. table 375. offset base + (06 - 07h): frnum?frame number register bits name description access 15:1 1 reserved reserved. 10:0 frame list current index/frame number provides the frame number in the sof frame. the value in this register increments at the end of each time frame (approximately every 1 ms). in addition, bits [9:0] are used for the frame list current index and correspond to memory address signals [11:2]. r/w table 376. offset base + (08 - 0bh): frbaseadd?frame list base address bits name description access 31:1 2 base address these bits correspond to memory address signals [31:12], respectively. r/w 11:0 reserved reserved. device: 29 function: x offset: base + (06-07h) attribute: read/write default value: 0000h size: 16-bit device: 29 function: x offset: base + (08-0bh) attribute: read/write default value: undefined size: 32-bit
10? intel ? 6300ESB ich intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 482 10.2.6 offset base + och: sofmod?start of frame modify register note: this 1-byte register is used to modify the value used in the generation of sof timing on the usb. only the 7 least significant bits are used. when a new value is written into these 7 bits, the sof timing of the next frame will be adjusted. this feature may be used to adjust out any offset from the clock source that generates the clock that drives the sof counter. this register may also be used to maintain real-time synchronization with the rest of the system so that all devices have the same sense of real time. using this register, the frame length may be adjusted across the full range required by the usb specification. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. it may be reprogrammed by usb system software at any time. its value will take effect from the beginning of the next frame. this register is reset upon a host controller reset or global reset. software must maintain a copy of its value for reprogramming when necessary. table 377. offset base + och: sofmod?start of frame modify register bits name description access 7 reserved reserved. 6:0 sof timing value guidelines for the modification of frame time are contained in chapter 7 of the usb specification. the sof cycle time (number of sof counter clock periods to generate a sof frame length) is equal to 11936 + value in this field. the default value is decimal 64 which gives a sof cycle time of 12000. for a 12 mhz sof counter clock input, this produces a 1 ms frame period. the following table indicates what sof timing value to program into this field for a certain frame period. frame length (# 12 mhz clocks) sof reg. value (decimal) (decimal) 11936 0 11937 1 . . . . 11999 63 12000 64 12001 65 . . . . 12062 126 12063 127 r/w device: 29 function: x offset: base + (0ch) attribute: read/write default value: 40h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 483 10?intel ? 6300ESB ich 10.2.7 portsc[0,1]?port status and control register note: for function 0 this applies to the intel ? 6300ESB ich usb ports 0 and 1; for function 1 this applies to the intel ? 6300ESB ich usb ports 2 and 3. after a power-up reset, global reset, or host controller reset, the initial conditions of a port are: no device connected, port disabled, and the bus line status is 00 (single- ended ?0?). table 378. portsc[0,1]?port status and control register (sheet 1 of 2) bits name description access 15:1 3 reserved reserved. ro 12 suspend this bit should not be written to a ?1? when a global suspend is active (bit 3 =1 in the usbcmd register). bit 2 and bit 12 of this register define the hub states as follows: bits [12, 2] hub state x 0 disable 0 1 enable 1 1 suspend when in suspend state, downstream propagation of data is blocked on this port, except for single-ended ?0? resets (global reset and port reset). the blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to ?1?. in the suspend state, the port is sensitive to resume detection. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port when there is a transaction currently in progress on the usb. 1 = port in suspend state. 0 = port not in suspend state. note: normally, if a transaction is in progress when this bit is set, the port will be suspended when the current transaction completes. however, in the case of a specific error condition (out transaction with babble), the intel ? 6300ESB ich may issue a start-of-frame, then suspend the port. r/w 11 overcurrent indicator set by hardware. 0 = software clears this bit by writing a ?1? to the bit position. 1 = overcurrent pin has gone from inactive to active on this port. r/wc 10 overcurrent active this bit is set and cleared by hardware. 0 = indicates that the overcurrent pin is inactive (high). 1 = indicates that the overcurrent pin is active (low). ro 9port reset 0 = port is not in reset. 1 = port is in reset. when set, the port is disabled and sends the usb reset signaling. ro 8 low speed device attached (ls) writes have no effect. 0 = full-speed device is attached. 1 = low-speed device is attached to this port. ro device: x function: x offset: port 0/2: 10-11h port 1/3: 12-13h attribute: read/write default value: 0080h size: 16-bit
intel ? 6300ESB ich?10 intel ? 6300ESB i/o controller hub ds november 2007 484 order number: 300641-004us 7 reserved reserved. always read as ?1?. ro 6 resume detect (rsm_det) software sets this bit to a ?1? to drive resume signaling. the host controller sets this bit to a ?1? when a j-to-k transition is detected for at least 32 microseconds while the port is in the suspend state. the intel ? 6300ESB ich will then reflect the k-state back onto the bus as long as the bit remains a ?1? and the port is still in the suspend state (bit 12, 2 are ?11?). writing a ?0? (from ?1?) causes the port to send a low-speed eop. this bit will remain a ?1? until the eop has completed. 0 = no resume (k-state) detected/driven on port. 1 = resume detected/driven on port. r/w 5:4 line status these bits reflect the d+ (bit 4) and d- (bit 5) signals lines? logical levels. these bits are used for fault detect and recovery as well as for usb diagnostics. this field is updated at eof2 time (see chapter 11 of the usb specification). ro 3 port enable/disable change for the root hub, this bit gets set only when a port is disabled due to disconnect on that port or due to the appropriate conditions existing at the eof2 point (see chapter 11 of the usb specification). 0 = no change. software clears this bit by writing a ?1? to the bit location. 1 = port enabled/disabled status has changed. r/wc 2 port enabled/disabled (port_en) ports may be enabled by host software only. ports may be disabled by either a fault condition (disconnect event or other fault condition) or by host software. note that the bit status does not change until the port state actually changes and that there may be a delay in disabling or enabling a port when there is a transaction currently in progress on the usb. 0 = disable 1 = enable r/w 1 connect status change indicates that a change has occurred in the port?s current connect status (see bit 0). the hub device sets this bit for any changes to the port device connect status even when system software has not cleared a connect status change. if, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). however, the hub transfers the change bit only once when the host controller requests a data transfer to the status change endpoint. system software is responsible for determining state change history in such a case. 0 = no change. software clears this bit by writing a ?1? to the bit location. 1 = change in current connect status. r/wc 0 current connect status this value reflects the current state of the port and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. 0 = no device is present. 1 = device is present on port. ro table 378. portsc[0,1]?port status and control register (sheet 2 of 2) bits name description access device: x function: x offset: port 0/2: 10-11h port 1/3: 12-13h attribute: read/write default value: 0080h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 485 11?intel ? 6300ESB ich usb ehci controller registers (d29:f7) 11 11.1 usb ehci configuration registers (d29:f7) note: registers that are not shown should be treated as reserved (see section 6.2, ?pci configuration map? for details). offset reg. name/function default value type 00-01h vendor id 8086h ro 02-03h device id 25adh ro 04-05h command register 0000h rw 06-07h device status 0290h rw 08h revision id (rid) see note: ro 09h programming interface 20h ro 0ah sub class code 03h ro 0bh base class code 0ch ro 0dh master latency timer 00h ro 0eh header type 00h ro 10-13h memory base address register 00000000h rw 2c-2dh subsystem vendor id xxxxh rw-special 2e-2fh subsystem id xxxxh rw-special 34h capabilities pointer 50h ro 3ch interrupt line 00h rw 3dh interrupt pin 04h ro 50h power management capability id 01h ro 51h next item ptr 58h ro 52-53h power management capabilities c9c2h ro-special 54-55h power management control/ status 0000h rw 57h power management data 00h ro 58h debug port capability id 0ah ro 59h next item pointer #2 00h ro 5a-5bh debug port base offset 2080h ro 60h usb release number 20h ro 61h frame length adjustment 20h rw 62-63h power wake capabilities 007fh rw 64-65h classic usb override 0000 ro note: refer to the intel? 6300ESB i/o controller hub specification update for the most up- to-date value of the revision id register.
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 486 order number: 300641-004us 11.1.1 offset 04 - 05h: command register 66-67h reserved 0 ro 68-6bh usb ehci legacy support extended capability 00000001h read/write 6c-6fh usb ehci legacy support control/status 00000000h read/write 70-73h intel specific usb ehci smi 00000000h read/write 74-7f reserved 0 read only 80h access control 00h read/write 81-ffh reserved 0 read only dch hs_ ref_v_usb hs reference voltage register 00000000h read/write table 379. offset 04 - 05h: command register bits name description access 15:0 reserved reserved. 9 fast back-to-back enable (fbe) reserved as 0. ro 8 serr# enable 0 = disables the enhanced host controller?s ( ehc?s) capability to generate an serr#. 1 = the ehc is capable of generating internally serr# when it receives a completion status other than ?successful? for ?1? of its dma-initiated memory reads on the hub interface (and subsequently on its internal interface). r/w 7 wait cycle control reserved as 0. ro 6 parity error response reserved as 0. ro 5 vga palette snoop reserved as 0. ro 4 postable memory write enable (pmwe) reserved as 0. ro 3 special cycle enable (sce) reserved as 0. ro 2 bus master enable (bme) 0 = disables this functionality. 1 = enables the intel ? 6300ESB ich. may act as a master on the pci bus for usb transfers. r/w 1 memory space enable (mse) 0 = disables this functionality. 1 = enables accesses to the usb ehci registers. the base address register for usb ehci should be programmed before this bit is set r/w 0 i/o space enable (iose) reserved as 0. ro offset reg. name/function default value type note: refer to the intel? 6300ESB i/o controller hub specification update for the most up- to-date value of the revision id register. device: 29 function: 7 offset: 04-05h attribute: read write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 487 11?intel ? 6300ESB ich 11.1.2 offset 06 - 07h: device status table 380. offset 06 - 07h: device status bits name description access 15 detected parity error (dpe) this bit is set by the intel ? 6300ESB ich whenever a parity error is seen on the internal interface to the usb host controller due to a parity error on hub interface, regardless of the setting of bit 6 or bit 8 in the command register or any other conditions. software clears this bit by writing a ?1? to this bit location. note that the parity error response bit in the hl-to-pci bridge should be set in order for the hub interface parity errors to be forwarded to the usb2 interface. this is a result of the point-to-point nature of the hub interface r/w 14 signaled system error (sse) 0 = software clears this bit by writing a ?1? to this bit location. 1 = this bit is set by the intel ? 6300ESB ich whenever it signals serr# (internally). the ser_en bit (bit 8 of the command register) must be ?1? for this bit to be set. r/w 13 received master-abort status (rma) 0 = software clears this bit by writing a ?1? to this bit location. 1 = this bit is set when usb ehci, as a master, receives a master-abort status on a memory access. this is treated as a host error and halts the dma engines. this event may optionally generate an serr# by setting the serr# enable bit . r/w 12 received target abort status (rta) 0 = software clears this bit by writing a ?1? to this bit location. 1 = this bit is set when usb ehci, as a master, receives a target abort status on a memory access. this is treated as a host error and halts the dma engines. this event may optionally generate an serr# by setting the serr# enable bit . r/w 11 signaled target-abort status (sta) this bit is used to indicate when the usb ehci function responds to a cycle with a target abort. there is no reason for this to happen, so this bit will be hard-wired to ?0?. ro 10:9 devsel# timing status (devt) this 2-bit field defines the timing for devsel# assertion. ro 8 master data parity error detected 0 = software clears this bit by writing a ?1? to this bit location. 1 = this bit is set by the intel ? 6300ESB ich whenever a data parity error is detected on a usb ehci read completion packet on the internal interface to the usb ehci host controller (due to an equivalent data parity error on hub interface) and bit 6 of the command register is set to 1. r/w 7 fast back-to-back capable reserved as 1. ro 6 udf - user definable features reserved as 0. ro 5 66 mhz capable reserved as 0. ro 4 capabilities list this bit is hardwired to ?1? indicating the presence of a valid capabilities pointer at offset 34h. ro 3:0 reserved reserved. device: 29 function: 7 offset: 06 - 07h attribute: read/ write default value: 0290h size: 16-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 488 order number: 300641-004us
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 489 11?intel ? 6300ESB ich 11.1.3 offset 08h: rid?revision id register 11.1.4 offset 09h: programming interface 11.1.5 offset 0ah: sub class code table 381. offset 08h: rid?revision id register bits name description access 7:0 revision id value refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. ro table 382. offset 09h: programming interface bits name description access 7:0 programming interface a value of 20h indicates that this usb high-speed host controller conforms to the ehci specification. ro table 383. offset 0ah: sub class code bits name description access 7:0 sub class code a value of 03h indicates that this is a universal serial bus host controller. ro device: 29 function: 7 offset: 08h attribute: read-only default value: see bit description size: 8-bit device: 29 function: 7 offset: 09h attribute: read-only default value: 20h size: 8-bit device: 29 function: 7 offset: 0ah attribute: read-only default value: 03h size: 8-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 490 order number: 300641-004us 11.1.6 offset 0bh: base class code 11.1.7 offset 0dh: master latency timer 11.1.8 offset 10 - 13h: memory base address table 384. offset 0bh: base class code bits name description access 7:0 base class code a value of 0ch indicates that this is a serial bus controller. ro table 385. offset 0dh: master latency timer bits name description access 7:0 master latency timer since the usb ehci controller is internally implemented with arbitration through the hub interface (and not pci), it does not need a master latency timer. these bits will be fixed to 0. ro table 386. offset 10 - 13h: memory base address bits name description access 31:1 0 base address bits [31:10] correspond to memory address signals [31:10], respectively. this gives 1 kbyte of locatable memory space aligned to 1 kbyte boundaries. rw 9:4 reserved reserved. 3prefetchable this bit is hardwired to 0, indicating that this range should not be prefetched. ro 2:1 type this field is hardwired to 00b indicating that this range may be mapped anywhere within 32-bit address space. ro 0 resource type indicator (rte) this field is hardwired to 00b indicating that this range may be mapped anywhere within 32-bit address space. ro device: 29 function: 7 offset: 0bh attribute: read-only default value: 0ch size: 8-bit device: 29 function: 7 offset: 0dh attribute: read-only default value: 00h size: 8-bit device: 29 function: 7 offset: 10 - 13h attribute: read/write default value: 00000000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 491 11?intel ? 6300ESB ich 11.1.9 offset 2c - 2dh: usb ehci subsystem vendor id 11.1.10 offset 2e - 2fh: sid?usb ehci subsystem id 11.1.11 offset 34h: capabilities pointer table 387. offset 2c - 2dh: usb ehci subsystem vendor id bits name description access 15:0 usb ehci subsystem vendor id this register, in combination with the usb ehci subsystem id register, enables the operating system to distinguish each subsystem from the others. writes to this register are enabled when the wrt_rdonly bit (offset 80h, bit 0) is set to 1. rw-special table 388. offset 2e - 2fh: sid?usb ehci subsystem id bits name description access 15:0 usb ehci subsystem id this register, in combination with the subsystem vendor id register, enables the operating system to distinguish each subsystem from other(s). bios sets the value in this register to identify the subsystem id. writes to this register are enabled when the wrt_rdonly bit (offset 80h, bit 0) is set to 1. rw-special table 389. offset 34h: capabilities pointer bits name description access 7:0 capabilities pointer this register points to the starting offset of the usb ehci capabilities ranges. ro device: 29 function: 7 offset: 2c-2dh attribute: read/write-special default value: xxxxh size: 16-bit device: 29 function: 7 offset: 2e-2fh attribute: read/write-special default value: xxxxh size: 16-bit device: 29 function: 7 offset: 34h attribute: read-only default value: 50h size: 8-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 492 order number: 300641-004us 11.1.12 offset 3ch: interrupt line 11.1.13 offset 3dh: interrupt pin 11.1.14 offset 50h: pci power management capability id table 390. offset 3ch: interrupt line bits name description access 7:0 interrupt line this data is not used by the intel ? 6300ESB ich. it is used as a scratchpad register to communicate to software the interrupt line that the inte rrupt pin is connected to. r/w table 391. offset 3dh: interrupt pin bits name description access 7:0 interrupt pin the value of 04h indicates that the usb ehci function within the intel ? 6300ESB ich?s multi-function usb device will drive the fourth interrupt pin from the device?ntd# in pci terms. the value of 04h in function 7 is required because the pci specification does not recognize more than four interrupts, and older apm-based oss require that each function within a multi-function device has a different interrupt pin register value. internally the usb ehci controller uses pirq[h]#. ro table 392. offset 50h: pci power management capability id bits name description access 7:0 a value of 01h indicates that this is a pci power management capabilities field. device: 29 function: 7 offset: 3ch attribute: read/write default value: 00h size: 8-bit device: 29 function: 7 offset: 3dh attribute: read-only default value: 04h size: 8-bit device: 29 function: 7 offset: 50h attribute: read-only default value: 01h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 493 11?intel ? 6300ESB ich 11.1.15 offset 51h: next item pointer #1 11.1.16 offset 52 - 53h: power management capabilities table 393. offset 51h: next item pointer #1 bits name description access 7:0 next item pointer #1 this register defaults to 58h, which indicates that the next capability registers begin at configuration offset 58h. this register is writable when the wrt_rdonly bit is set. this allows bios to effectively hide the debug port capability registers when necessary. this register should be written only during system initialization before the plug-and-play software has enabled any master-initiated traffic. only values of 58h (debug port visible) and 00h (debug port invisible) are expected to be programmed in this register. rw-special table 394. offset 52 - 53h: power management capabilities (sheet 1 of 2) bits name description access 15:1 1 pme_support this 5-bit field indicates the power states in which the function may assert pme#. the intel ? 6300ESB ich ehc does not support d1 or d2 states. for all other states, the intel ? 6300ESB ich ehc is capable of generating pme#. software should never need to modify this field. rw-special 10 d2_support hardwired to 0 = d2 state is not supported. rw-special 9 d1_support hardwired to 0 = d1 state is not supported. rw-special 8:6 aux_current the intel ? 6300ESB ich ehc reports 375 ma maximum suspend well current required when in the d3cold state. this value may be written by bios when a more accurate value is known. rw-special 5dsi the intel ? 6300ESB ich reports 0, indicating that no device- specific initialization is required. rw-special 4 reserved reserved. device: 29 function: 7 offset: 51h attribute: read/write special default value: 58h size: 8-bit device: 29 function: 7 offset: 52-53h attribute: read/write special default value: c9c2h size: 16-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 494 order number: 300641-004us 11.1.17 offset 54 - 55h: power management control/ status 3pme clock the intel ? 6300ESB ich reports 0, indicating that no pci clock is required to generate pme#. rw-special 2:0 version the intel ? 6300ESB ich reports 010b, indicating that it complies with revision 1.1 of the pci power management specification. rw-special notes: 1. normally, this register is read-only to report capabilities to the power management software. to report different power management capabilities depending on the system in which the intel ? 6300ESB ich is used, bits 15:11 and 8:6 in this register are writable when the wrt_rdonly bit is set. the value written to this register does not affect the hardware other than changing the value returned during a read. 2. reset: core well, but not d3-to-d0 warm reset. table 395. offset 54 - 55h: power management control/status bits name description access 15 pme_status this bit is set when the intel ? 6300ESB ich ehc would normally assert the pme# signal independent of the state of the pme_en bit. writing a ?1? to this bit will clear it and cause the internal pme to deassert when enabled. writing a ?0? has no effect. this bit must be explicitly cleared by the operating system each time the operating system is loaded. r/wc 14:1 3 data_scale the intel ? 6300ESB ich hardwires these bits to 00b because it does not support the associated data register. ro 12:9 data_select the intel ? 6300ESB ich hardwires these bits to 0000b because it does not support the associated data register. ro 8pme_en a ?1? enables the intel ? 6300ESB ich ehc to generate an internal pme signal when pme_status is 1. this bit must be explicitly cleared by the operating system each time it is initially loaded. r/w table 394. offset 52 - 53h: power management capabilities (sheet 2 of 2) bits name description access device: 29 function: 7 offset: 52-53h attribute: read/write special default value: c9c2h size: 16-bit device: 29 function: 7 offset: 54 - 55h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 495 11?intel ? 6300ESB ich 11.1.18 offset 58h: debug port capability id 7:2 reserved reserved. 1:0 powerstate this 2-bit field is used both to determine the current power state of ehc function and to set a new power state. the definition of the field values are: 00b ? d0 state 11b ? d3 hot state when software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. when in the d3 hot state, the intel ? 6300ESB ich must not accept accesses to the ehc memory range, but the configuration space must still be accessible. when not in the d0 state, the generation of the interrupt output is blocked. specifically, the pirq[h] is not asserted by the intel ? 6300ESB ich when not in the d0 state. when software changes this value from the d3hot state to the d0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. r/w note: reset (bits 15, 8): suspend well, and not d3-to-d0 warm reset nor core well reset. table 396. offset 58h: debug port capability id bits name description access 7:0 debug port capability id this register is hardwired to 0ah, which indicates that this is the start of a debug port capability structure. ro table 395. offset 54 - 55h: power management control/status bits name description access device: 29 function: 7 offset: 54 - 55h attribute: read/write default value: 0000h size: 16-bit device: 29 function: 7 offset: 58h attribute: read-only default value: 0ah size: 8-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 496 order number: 300641-004us 11.1.19 offset 59h: next item pointer #2 11.1.20 offset 5ah - 5bh: debug port base offset 11.1.21 offset 60h: serial bus release number 11.1.22 offset 61h: frame length adjustment note: this feature is used to adjust any offset from the clock source that generates the clock that drives the sof counter. when a new value is written into these six bits, the length of the frame is adjusted. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. this register should only be modified when the hchalted bit in the usbsts register is a ?1?. changing value of this register while the host controller is operating yields undefined results. it table 397. offset 59h: next item pointer #2 bits name description access 7:0 next item pointer #2 this register is hardwired to 00h which indicates there are no more capability structures in this function. ro table 398. offset 5ah - 5bh: debug port base offset bits name description access 15:1 3 bar number this field is hardwired to 20h to indicate the memory bar begins at offset 20h in the ehci configuration space. ro 12:0 debug port offset this field is hardwired to 080h to indicate that the debug port registers begin at offset 80h in the ehci memory range. ro device: 29 function: 7 offset: 59h attribute: read-only default value: 00h size: 8-bit device: 29 function: 7 offset: 5ah - 5bh attribute: read-only default value: 2080h size: 16-bit table 399. offset 60h: serial bus release number bits name description access 7:0 a value of 20h indicates that this controller follows the usb specification rev. 2.0. device: 29 function: 7 offset: 60h attribute: read-only default value: 20h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 497 11?intel ? 6300ESB ich should not be reprogrammed by usb system software unless the default or bios programmed values are incorrect or the system is restoring the register while returning from a suspended state. 11.1.23 offset 62 - 63h: port wake capability note: this register is in the suspend power well. the intended use of this register is to establish a policy about which ports are to be used for wake events. bit positions 1-4 in the mask correspond to a physical port implemented on the current ehci controller. a ?1? in a bit position indicates that a device connected below the port may be enabled as a wake-up device, and the port may be enabled for disconnect/connect or over-current events as wake-up events. this is an information-only mask register. the bits in this register do not affect the actual operation of the ehci host controller. the system- specific policy may be established by bios initializing this register to a system-specific value. system software uses the information in this register when enabling devices and ports for remote wake-up. table 400. offset 61h: frame length adjustment bits name description access 7:6 reserved these bits are reserved for future use and should read as 00b. ro 5:0 frame length timing value each decimal value change to this register corresponds to 16 high-speed bit times. the sof cycle time (number of sof counter clock periods to generate a sof micro-frame length) is equal to 59488 + value in this field. the default value is decimal 32 (20h), which gives a sof cycle time of 60000. frame length (# high speed bit times)fladj value (decimal) (decimal) 59488 0 (00h) 59504 1 (01h) 59520 2 (02h) ? 59984 31 (1fh) 60000 32 (20h) ? 60480 62 (3eh) 60496 63 (3fh) device: 29 function: 7 offset: 61h attribute: read/write default value: 20h size: 8-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 498 order number: 300641-004us 11.1.24 offset 64 - 65h: classic usb override note: this 16-bit register provides a bit corresponding to each of the ports on the ehci host controller. when a bit is set to ?1?, the corresponding usb port is routed to the classic (uhci) host controller and will operate using only the classic signaling rates. the feature is implemented with the following requirements: ? the associated port owner bit does not reflect the value in this new override register. this guarantees compatibility with ehci drivers. ? the associated port owner bit does not reflect the value in this new override register. this guarantees compatibility with ehci drivers. ? bios must only write to this register during initialization (while the configured flag is ?0?). ? the register is implemented in the suspend well to maintain port-routing when the core power goes down ? when a ?1? is present in the override register, the classic controller operates the port regardless of the ehci port routing logic. the corresponding ehci port will always appear disconnected in this mode. note: ehci test modes will not work on a port that has been overridden by this register. table 401. offset 62 - 63h: port wake capability bits name description access 15:5 reserved reserved. 4:1 port wake up capability mask bit positions 1 through 4 correspond to a physical port implemented on this host controller. for example, bit position 1 corresponds to port 0, position 2 port 1, position 3 port 2, position 4 port 3. rw 0 port wake implemented a ?1? in bit 0 indicates that this register is implemented to software. rw device: 29 function: 7 offset: 62 - 63h attribute: read/write default value: 001fh size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 499 11?intel ? 6300ESB ich table 402. offset 64-65h: cuo - classic usb override 11.1.25 offset 68 - 6bh: usb ehci legacy support extended capability bits name description reset value access 15:4 reserved reserved. 3:2 classic usb port owner a ?1? in a bit position forces the corresponding usb port to the classic host controller r/w 0 reserved reserved. device: 29 function: 7 offset: 64-65h attribute: read/write default value: 0000h size: 16-bit power well: suspend table 403. offset 68 - 6bh: usb ehci legacy support extended capability bits name description reset value access 31:2 5 reserved reserved. hardwired to 00h. 24 hc os owned semaphore system software sets this bit to request ownership of the ehci controller. ownership is obtained when this bit reads as ?1? and the hc bios owned semaphore bit reads as clear. r/w 23:1 7 reserved reserved. hardwired to 00h. ro 16 hc bios owned semaphore the bios sets this bit to establish ownership of the ehci controller. system bios will clear this bit in response to a request for ownership of the ehci controller by system software. r/w 15:8 next ehci capability pointer a value of 00h indicates that there are no ehci extended capability structures in this device. ro 7:0 capability id a value of 01h indicates that this ehci extended capability is the legacy support capability. ro device: 29 function: 7 offset: 68-6bh attribute: read/write default value: 00000001h size: 32-bit power well: suspend
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 500 order number: 300641-004us 11.1.26 offset 6c - 6fh: usb ehci legacy support extended control/status table 404. offset 6c - 6fh: usb ehci legacy support extended control/status (sheet 1 of 2) bits name description access 31 smi on bar this bit is set to ?1? whenever the base address register (bar) is written. r/wc 30 smi on pci command this bit is set to ?1? whenever the pci command register is written. r/wc 29 smi on os ownership change this bit is set to ?1? whenever the hc os owned semaphore bit in the usb ehci legacy support extended capability register transitions from ?1? to a ?0? or ?0? to a ?1?. r/wc 28:2 2 reserved hardwired to 00h. ro 21 smi on async advance shadow bit of the interrupt on async advance bit in the usb2sts register. to clear this bit system software must write a ?1? to the interrupt on async advance bit in the usb2sts register. ro 20 smi on host system error shadow bit of host system error bit in the usb2sts. to clear this bit, system software must write a ?1? to the host system error bit in the usb2sts register. ro 19 smi on frame list rollover shadow bit of frame list rollover bit in the usb2sts register. to clear this bit system software must write a ?1? to the frame list rollover bit in the usb2sts register. ro 18 smi on port change detect shadow bit of port change detect bit in the usb2sts register. to clear this bit system software must write a ?1? to the port change detect bit in the usb2sts register. ro 17 smi on usb error shadow bit of usb error interrupt (usberrint) bit in the usb2sts register. to clear this bit system software must write a ?1? to the usb error interrupt bit in the usb2sts register. ro 16 smi on usb complete shadow bit of usb interrupt (usbint) bit in the usb2sts register. to clear this bit system software must write a ?1? to the usb interrupt bit in the usb2sts register. ro 15 smi on bar enable when this bit is ?1? and smi on bar is ?1?, the host controller will issue an smi. r/w 14 smi on pci command enable when this bit is ?1? and smi on pci command is ?1?, the host controller will issue an smi. r/w 13 smi on os ownership enable when this bit is a ?1? and the os ownership change bit is ?1?, the host controller will issue an smi. r/w 12:6 reserved reserved?ro. hardwired to 00h. ro 5 smi on async advance enable when this bit is a ?1? and the smi on async advance bit is a ?1?, the host controller will issue an smi immediately. r/w device: 29 function: 7 offset: 6c-6fh attribute: read/write default value: 00000000h size: 32-bit power well: suspend
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 501 11?intel ? 6300ESB ich 11.1.27 offset 70 - 73h: intel specific usb ehci smi note: this register provides a mechanism for bios to provide usb ehci related bug fixes and workarounds. writing a ?1? to that bit location clears bits that are marked as read/ write-clear (r/wc). software should clear all smi status bits prior to setting the global smi enable bit and individual smi enable bit to prevent spurious smi when returning from a powerdown. 4 smi on host system error enable when this bit is a ?1? and the smi on host system error is a ?1?, the host controller will issue an smi. r/w 3 smi on frame list rollover enable when this bit is a ?1? and the smi on frame list rollover bit is a ?1?, the host controller will issue an smi. r/w 2 smi on port change enable when this bit is a ?1? and the smi on port change detect bit is a ?1?, the host controller will issue an smi. r/w 1 smi on usb error enable when this bit is a ?1? and the smi on usb error bit is a ?1?, the host controller will issue an smi immediately. r/w 0 smi on usb complete enable when this bit is a ?1? and the smi on usb complete bit is a ?1?, the host controller will issue an smi immediately. r/w table 405. offset 70 - 73h: intel specific usb ehci smi (sheet 1 of 2) bits name description access 31:2 8 reserved reserved. hardwired to 00h. ro 27:2 6 reserved reserved. r/wc 25:2 2 smi on portowner bits 27:22 correspond to the port owner bits for ports 0 (22) through 3 (25). these bits are set to ?1? whenever the associated port owner bits transition from ?0?->?1? or ?1?->?0?. software clears these bits by writing a ?1?. r/wc 21 smi on pmcsr this bit is set to ?1? whenever software modifies the power state bits in the power management control/status (pmcsr) register. r/wc 20 smi on async this bit is set to ?1? whenever the async schedule enable bit transitions from ?1?->?0? or ?0?->?1? r/wc table 404. offset 6c - 6fh: usb ehci legacy support extended control/status (sheet 2 of 2) bits name description access device: 29 function: 7 offset: 6c-6fh attribute: read/write default value: 00000000h size: 32-bit power well: suspend device: 29 function: 7 offset: 70-73h attribute: read/write default value: 00000000h size: 32-bit power well: suspend
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 502 order number: 300641-004us 19 smi on periodic this bit is set to ?1? whenever the periodic schedule enable bit transitions from ?1?->?0? or ?0?->?1? r/wc 18 smi on cf this bit is set to ?1? whenever the configure flag (cf) transitions from ?1?->?0? or ?0?->?1?. r/wc 17 smi on hchalted this bit is set to ?1? whenever hchalted transitions to ?1? as a result of the run/stop bit being cleared. r/wc 16 smi on hcreset this bit is set to ?1? whenever hcreset transitions to ?1? r/wc 15:1 2 reserved reserved. hardwired to 00h. ro 11:1 0 reserved reserved. r/w 9:6 smi on portowner enable when any of these bits are ?1? and the corresponding smi on portowner bits are ?1?, the host controller will issue an smi. unused ports should have their corresponding bits cleared. r/w 5smi on pmscr enable when this bit is ?1? and smi on pmscr is ?1?, the host controller will issue an smi. r/w 4smi on async enable when this bit is ?1? and smi on async is ?1?, the host controller will issue an smi r/w 3 smi on periodic enable when this bit is ?1? and smi on periodic is ?1?, the host controller will issue an smi. r/w 2 smi on cf enable when this bit is ?1? and smi on cf is ?1?, then the host controller will issue an smi. r/w 1 smi on hchalted enable when this bit is a ?1? and smi on hchalted is ?1?, the host controller will issue an smi. r/w 0smi on hcreset enable when this bit is a ?1? and smi on hcreset is ?1?, host controller will issue an smi. r/w table 405. offset 70 - 73h: intel specific usb ehci smi (sheet 2 of 2) bits name description access device: 29 function: 7 offset: 70-73h attribute: read/write default value: 00000000h size: 32-bit power well: suspend
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 503 11?intel ? 6300ESB ich 11.1.28 offset 80h: access control 11.1.29 hs_ ref_v_usb hs reference voltage register 11.2 memory-mapped i/o registers the usb 2.0 ehci memory-mapped i/o space is composed of two sets of registers: capability registers and operational registers. note: when the usb ehci function is in the d3 pci power state, accesses to the usb ehci memory range are ignored and result a master abort. similarly, when the memory space enable (mse) bit is not set in the command register in configuration space, the memory range will not be decoded by the intel ? 6300ESB ich enhanced host controller (ehc). when the mse bit is not set, the intel ? 6300ESB ich must default to allowing any memory accesses for the range specified in the bar to go to pci. this is table 406. offset 80h: access control bits name description access 7:1 reserved reserved. 0wrt_rdonly when set to ?1?, this bit enables a select group of normally read-only registers in the ehc function to be written by software. registers that may only be written when this mode is entered are noted in the summary tables and detailed description as read/write-special. the registers fall into two categories: 1. system-configured parameters 2. status bits r/w table 407. hs_ ref_v_usb hs reference voltage register bits name description access 31:2 2 reserved reserved ro 21:1 6 usb2 hs ref voltage bios should always program this register to the recommended value of ?111111b?. all other values are reserved. rw 15:0 reserved reserved rw note: system bios should program a value of '111111b' into d29:f7:register offset dch, bits 21:16 during post and resume from s3(str)/s4(std) states on all steppings of the intel 6300ESB ich. device: 29 function: 7 offset: 80h attribute: read/write default value: 00h size: 8-bit device: 29 function: 7 offset: dch attribute: read/write default value: 00000000h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 504 order number: 300641-004us because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. 11.2.1 host controller capability registers these registers specify the limits, restrictions and capabilities of the host controller implementation. within the host controller capability registers, only the structural parameters register is writable. this register is implemented in the suspend well and is only reset by the standard suspend-well hardware reset, not by hcreset or the d3-to- d0 reset. 11.2.1.1 offset 00h: caplength?capability registers length offse t register default type 00h capabilities registers length 20h ro 02- 03h host controller interface version number 0100h ro 04- 07h structural parameters 00103206h rw-special 08- 0bh capability parameters 00006871h ro note: ?rw-special? means that the register is normally read-only, but may be written when the wrt_rdonly bit is set. since these registers are expected to be programmed by bios during initialization, their contents must not get modified by hcreset or d3-to- d0 internal reset. table 408. offset 00h: caplength?capability registers length bits name description access 7:0 this register is used as an offset to add to the memory base register to find the beginning of the operational register space. this is fixed at 20h, indicating that the operation registers begin at offset 20h. device: 29 function: 7 offset: 00h attribute: read-only default value: 20h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 505 11?intel ? 6300ESB ich 11.2.1.2 offset 02 - 03h: hciversion?host controller interface version number 11.2.1.3 offset 04 - 07h: hcsparams?host controller structural parameters note: this register is reset by a suspend well reset and not a d3-to-d0 reset or hcreset. note: this register is writable when the wrt_rdonly bit is set. table 409. offset 02 - 03h: hciversion?host controller interface version number bits name description access 15:0 host controller interface version number this is a two-byte register containing a bcd encoding of the version number of interface that this host controller interface conforms. ro table 410. offset 04 - 07h: hcsparams?host controller structural parameters (sheet 1 of 2) bits name description access 31:2 4 reserved reserved. default = 0h. ro 23:2 0 debug port number (dp_n) hardwired to 1h, indicating that the debug port is on the lowest numbered port on the intel ? 6300ESB ich. 19:1 7 reserved reserved. 16 reserved reserved. hardwired to 0. device: 29 function: 7 offset: 02 - 03h attribute: read-only default value: 0100h size: 16-bit device: 29 function: 7 offset: 04-07h attribute: read/write-special default value: 00102204h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 506 order number: 300641-004us 15:1 2 number of companion controllers (n_cc) this field indicates the number of companion controllers associated with this usb echi host controller. a ?0? in this field indicates there are no companion host controllers. port-ownership hand-off is not supported. only high-speed devices are supported on the host controller root ports. a value larger than ?1? in this field indicates there are companion usb uhci host controller(s). port-ownership hand-offs are supported. high, full- and low-speed devices are supported on the host controller root ports. the intel ? 6300ESB ich allows the default value of 2h to be over-written by bios. since the intel ? 6300ESB ich cannot support more than two companion host controllers, bits 15:14 are implemented as read-only 00b. when removing classic controllers, they should be disabled in the following order: function 1 and function 0, which correspond to ports 3:2 and 1:0, respectively. 11:8 number of ports per companion controller (n_pcc) this field indicates the number of ports supported per companion host controller. it is used to indicate the port routing configuration to system software. the intel ? 6300ESB ich hardwires this field to 2h. ro 7:4 reserved reserved. these bits are reserved and default to ?0?. 3:0 n_ports this field specifies the number of physical downstream ports implemented on this host controller. the value of this field determines how many port registers are addressable in the operational register space. valid values are in the range of 1h to fh. the intel ? 6300ESB ich reports 4h by default. however, software may write a value less than four for some platform configurations. a ?0? in this field is undefined. bit 3 is always hardwired to ?0?. table 410. offset 04 - 07h: hcsparams?host controller structural parameters (sheet 2 of 2) bits name description access device: 29 function: 7 offset: 04-07h attribute: read/write-special default value: 00102204h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 507 11?intel ? 6300ESB ich 11.2.1.4 offset 08 - 0bh: hccparams?host controller capability parameters table 411. offset 08 - 0bh: hccparams?host controller capability parameters bits name description access 31:1 6 reserved reserved. 15:8 ehci extended capabil- ities pointer (eecp) this field is hardwired to 68h, indicating that the ehci capabilities list exists and begins at offset 68h in the pci configuration space. ro 7:4 isochronous scheduling threshold this field indicates, relative to the current position of the executing host controller, where software may reliably update the isochronous schedule. when bit [7] is ?0?, the value of the least significant 3 bits indicates the number of micro-frames a host controller holds a set of isochronous data structures (one or more) before flushing the state. when bit [7] is a ?1?, then host software assumes the host controller may cache an isochronous data structure for an entire frame. refer to the ehci specification for details on how software uses this information for scheduling isochronous transfers. this field is hardwired to 7h. ro 3 reserved reserved. these bits are reserved and should be set to ?0?. 2 asynchronous schedule park capability this bit is hardwired to 0, indicating that the host controller does not support this optional feature. 1 programmable frame list flag 0 = system software must use a frame list length of 1024 elements with this host controller. the usbcmd register frame list size field is a read-only register and must be set to ?0?. 1 = system software may specify and use a smaller frame list and configure the host controller through the usbcmd register frame list size field. the frame list must always be aligned on a 4k page boundary. this requirement ensures that the frame list is always physically contiguous. ro 0 64-bit addressing capability this field documents the addressing range capability of this implementation. the value of this field determines whether software should use the 32-bit or 64-bit data structures. values for this field have the following interpretation: 0 = data structures using 32-bit address memory pointers 1 = data structures using 64-bit address memory pointers this bit is hardwired to 1. ro device: 29 function: 7 offset: 08-0bh attribute: read-only default value: 00006871h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 508 order number: 300641-004us 11.2.2 host controller operational registers this section defines the enhanced host controller operational registers. these registers are located after the capabilities registers. the operational register base must be dword-aligned and is calculated by adding the value in the first capabilities register (caplength=20h) to the base address of the enhanced host controller register address space. all registers are 32 bits in length. note: software must read and write these registers using only dword accesses. these registers are divided into two sets. the first set at offsets 20h to 3fh are implemented in the core power well. unless otherwise noted, the core-well registers are reset by the assertion of any of the following: ? core well hardware reset ? hcreset ? d3-to-d0 reset the second set at offsets 60h to the end of the implemented register space are implemented in the suspend power well. unless otherwise noted, the suspend-well registers are reset by the assertion of either of the following: ? suspend well hardware reset ? hcreset offset register default special notes type 00-03h usb ehci command 00080000h r/w 04-07h usb ehci status 00001000h r/w 08-0bh usb ehci interrupt enable 00000000h r/w 0c-0fh usb ehci frame index 00000000h r/w 10-13h control data structure segment 00000000h r/w 14-17h period frame list base address 00000000h r/w 18-1bh next asynchronous list address 00000000h r/w 1c-3fh reserved 0h ro 40- 43h configure flag register 00000000h suspend r/w 44-47h port 0 status and control 00003000h suspend r/w 48-4bh port 1 status and control 00003000h suspend r/w 4c-4fh port 2 status and control 00003000h suspend r/w 50-53h port 3 status and control 00003000h suspend r/w 54-5fh reserved undefined ro 60-73h debug port registers. undefined ro 74-3ffh reserved undefined ro
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 509 11?intel ? 6300ESB ich 11.2.2.1 offset caplength + 00 - 03h: usb ehci cmd?usb ehci command register table 412. offset caplength + 00 - 03h: usb ehci cmd?usb ehci command register (sheet 1 of 3) bits name description access 31:2 4 reserved reserved. these bits are reserved and should be set to ?0?. 23:1 6 interrupt threshold control default 04h. this field is used by system software to select the maximum rate at which the host controller will issue interrupts. the only valid values are defined below. when software writes an invalid value to this register, the results are undefined. value maximum interrupt interval 00h reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) r/w 15:8 reserved reserved. these bits are reserved and should be set to ?0?. 11:8 unimplemented asynchronous park mode bits this field is hardwired to 000b because the host controller does not support this optional feature. 7 light host controller reset the intel ? 6300ESB ich does not implement this optional reset and hardwires this bit to 0. ro 6 interrupt on async advance doorbell this bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. software must write a ?1? to this bit to ring the doorbell. when the host controller has evicted all appropriate cached schedule state, it sets the interrupt on async advance status bit in the usbsts register. when the interrupt on async advance enable bit in the usbintr register is a ?1?, the host controller will assert an interrupt at the next interrupt threshold. see the ehci specification for operational details. the host controller sets this bit to a ?0? after it has set the interrupt on async advance status bit in the usbsts register to a ?1?. software should not write a ?1 ?to this bit when the asynchronous schedule is inactive. doing so will yield undefined results. r/w 5 asynchronous schedule enable default 0b. this bit controls whether the host controller skips processing the asynchronous schedule. values mean: 0 = do not process the asynchronous schedule 1 = use the asynclistaddr register to access the asynchronous schedule. r/w device: 29 function: 7 offset: caplength + 00-03h attribute: read/write default value: 00080000h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 510 order number: 300641-004us 4 periodic schedule enable default 0b. this bit controls whether the host controller skips processing the periodic schedule. values mean: 0 = do not process the periodic schedule 1 = use the periodiclistbase register to access the periodic schedule. r/w 3:2 frame list size the intel ? 6300ESB ich hardwires this field to 00b because it only supports the 1024-element frame list size. ro table 412. offset caplength + 00 - 03h: usb ehci cmd?usb ehci command register (sheet 2 of 3) bits name description access device: 29 function: 7 offset: caplength + 00-03h attribute: read/write default value: 00080000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 511 11?intel ? 6300ESB ich 1 host controller reset (hcreset) this control bit is used by software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset (i.e., rsmrst# assertion and pwrok deassertion on the intel ? 6300ESB ich). when software writes a ?1? to this bit, the host controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. note: pci configuration registers and host controller capability registers are not effected by this reset . all operational registers, including port registers and port state machines are set to their initial values. port ownership reverts to the companion host controller(s), with the side effects described in the ehci spec. software must re-initialize the host controller in order to return the host controller to an operational state. this bit is set to ?0? by the host controller when the reset process is complete. software cannot terminate the reset process early by writing a ?0? to this register. software should not set this bit to a ?1? when the hchalted bit in the usbsts register is a ?0?. attempting to reset an actively running host controller will result in undefined behavior. this reset can be used to leave ehci port test modes. r/w 0 run/stop (rs) default 0b. 1=run. 0=stop. when set to a 1, the host controller proceeds with execution of the schedule. the host controller continues execution as long as this bit is set. when this bit is set to 0, the host controller completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. software should not write a ?1? to this field unless the host controller is in the halted state (i.e., hchalted in the usbsts register is a ?1?). the halted bit is cleared immediately when the run bit is set. the following table explains how the different combinations of run and halted should be interpreted: run/stop halted interpretation 0 0 valid - in the process of halting 0 1 valid - halted 1 0 valid - running 1 1 invalid - the hchalted bit clears immediately. memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being cleared. r/w note: the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. table 412. offset caplength + 00 - 03h: usb ehci cmd?usb ehci command register (sheet 3 of 3) bits name description access device: 29 function: 7 offset: caplength + 00-03h attribute: read/write default value: 00080000h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 512 order number: 300641-004us 11.2.2.2 offset caplength + 04 - 07h: usb ehci sts?usb ehci status note: this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. software sets a bit to ?0? in this register by writing a ?1? to it. see the interrupts description in section 4 of the ehci specification for additional information concerning usb ehci interrupt conditions. table 413. offset caplength + 04 - 07h: usb ehci sts?usb ehci status (sheet 1 of 2) bits name description access 31:1 6 reserved reserved. these bits are reserved and should be set to ?0?. 15 asynchronous schedule status 0 = default. this bit reports the current real status of the asynchronous schedule. when this bit is a ?0?, the status of the asynchronous schedule is disabled. when this bit is a ?1?, the status of the asynchronous schedule is enabled. the host controller is not required to immediately disable or enable the asynchronous schedule when software transitions the asynchronous schedule enable bit in the usbcmd register. when this bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). ro 14 periodic schedule status 0 = default. this bit reports the current real status of the periodic schedule. when this bit is a ?0?, the status of the periodic schedule is disabled. when this bit is a ?1?, the status of the periodic schedule is enabled. the host controller is not required to immediately disable or enable the periodic schedule when software transitions the periodic schedule enable bit in the usbcmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). ro 13 reclamation 0 = default. this is a read-only status bit used to detect an empty asynchronous schedule. the operational model and valid transitions for this bit are described in section 4 of the ehci specification. ro 12 hchalted (defaults to 1). this bit is a ?0? whenever the run/stop bit is a ?1?. the host controller sets this bit to ?1? after it has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (e.g., internal error). ro 11:6 reserved reserved. 5 interrupt on async advance 0 = default. system software may force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a ?1? to the interrupt on async advance doorbell bit in the usbcmd register. this bit indicates the assertion of that interrupt source. r/wc device: 29 function: 7 offset: caplength + 04-07h attribute: read/write clear default value: 00001000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 513 11?intel ? 6300ESB ich 4host system error the host controller sets this bit to ?1? when a serious error occurs during a host system access involving the host controller module. a hardware interrupt is generated to the system. memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being set. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system (when enabled in the interrupt enable register). r/wc 3 frame list rollover the host controller sets this bit to a ?1? when the frame list index rolls over from its maximum value to ?0?. since the intel ? 6300ESB ich only supports the 1024-entry frame list size, the frame list index rolls over every time frnum[13] toggles. r/wc 2port change detect the host controller sets this bit to a ?1? when any port for which the port owner bit is set to ?0? has a change bit transition from a ?0? to a ?1? or a force port resume bit transition from a ?0? to a ?1? as a result of a j-k transition detected on a suspended port. this bit is allowed to be maintained in the auxiliary power well. alternatively, it is also acceptable that on a d3 to d0 transition of the ehci hc device, this bit is loaded with the or of all of the portsc change bits (including: force port resume, over-current change, enable/disable change and connect status change). regardless of the implementation, whenever this bit is readable (i.e., in the d0 state), it must provide a valid view of the port status registers. r/wc 1 usb error interrupt (usberrint) the host controller sets this bit to ?1? when completion of a usb transaction results in an error condition (e.g., error counter underflow). when the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit ?0? are set. see the ehci specification for a list of the usb errors that will result in this interrupt being asserted. r/wc 0 usb interrupt (usbint) the host controller sets this bit to ?1? when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. the host controller also sets this bit to ?1? when a short packet is detected (actual number of bytes received was less than the expected number of bytes). r/wc table 413. offset caplength + 04 - 07h: usb ehci sts?usb ehci status (sheet 2 of 2) bits name description access device: 29 function: 7 offset: caplength + 04-07h attribute: read/write clear default value: 00001000h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 514 order number: 300641-004us 11.2.2.3 offset caplength + 08 - 0bh: usb ehci intr?usb ehci interrupt enable 11.2.2.4 offset caplength + 0c - 0fh: frindex?frame index note: this register is used by the host controller to index into the periodic frame list. the register updates every 125 microseconds (once each micro-frame). bits [12:3] are used to select a particular entry in the periodic frame list during periodic schedule execution. the number of bits used for the index is fixed at 10 for the intel ? 6300ESB ich since it only supports 1024-entry frame lists. this register must be written as a table 414. offset caplength + 08 - 0bh: usb ehci intr?usb ehci interrupt enable bits name description access 31:6 reserved reserved.these bits are reserved and should be ?0?. 5 interrupt on async advance enable when this bit is a ?1? and the interrupt on async advance bit in the usbsts register is a ?1?, the host controller will issue an interrupt at the next interrup t threshold. the interrupt is acknowledged by software clearing the interrupt on async advance bit. r/w 4 host system error enable when this bit is a ?1? and the host system error status bit in the usbsts register is a ?1?, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the host system error bit. r/w 3 frame list rollover enable when this bit is a ?1? and the frame list rollover bit in the usbsts register is a ?1?, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the frame list rollover bit. r/w 2 port change interrupt enable when this bit is a ?1? and the port change detect bit in the usbsts register is a ?1?, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the port change detect bit. r/w 1 usb error interrupt enable when this bit is a ?1? and the usberrint bit in the usbsts register is a ?1?, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by clearing the usberrint bit in the usbsts register. r/w 0usb interrupt enable when this bit is a ?1? and the usbint bit in the usbsts register is a ?1?, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by clearing the usbint bit in the usbsts register. r/w notes: 1. for all enable register bits, 1= enabled, 0= disabled. 2. this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that are disabled in this register still appear in the status register to allow the software to poll for events. each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism (see section 4 of the ehci specification), or not. device: 29 function: 7 offset: caplength + 08-0bh attribute: read/write default value: 00000000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 515 11?intel ? 6300ESB ich dword. word and byte writes produce undefined results. this register cannot be written unless the host controller is in the halted state as indicated by the hchalted bit (usb ehci sts register). a write to this register while the run/stop bit is set to a ?1? (usb ehci cmd register) produces undefined results. writes to this register also effect the sof value. see section 4 of the ehci specification for details. the sof frame number value for the bus sof token is derived or alternatively managed from this register. please refer to section 4 of the ehci specification for a detailed explanation of the sof value management requirements on the host controller. the value of frindex must be within 125 s (1 micro-frame) ahead of the sof token value. the sof value may be implemented as an 11-bit shadow register. for this discussion, this shadow register is 11 bits and is named sofv. sofv updates every 8 micro-frames. (1 millisecond). an example implementation to achieve this behavior is to increment sofv each time the frindex[2:0] increments from a ?0? to a ?1?. software must use the value of frindex to derive the current micro-frame number, both for high-speed isochronous scheduling purposes and to provide the get micro- frame number function required to client drivers. therefore, the value of frindex and the value of sofv must be kept consistent when the chip is reset or software writes to frindex. writes to frindex must also write-through frindex[13:3] to sofv[10:0]. to keep the update as simple as possible, software should never write a frindex value where the three least significant bits are 111b or 000b. 11.2.2.5 offset caplength + 10 - 13h: ctrldssegment?control data structure segment register note: this 32-bit register corresponds to the most significant address bits [63:32] for all ehci data structures. since the intel ? 6300ESB ich hardwires the 64-bit addressing capability field in hccparams to ?1?, then this register is used with the link pointers to construct 64-bit addresses to ehci control data structures. this register is concatenated with the link pointer from either the periodiclistbase, asynclistaddr, or any control data structure link field to construct a 64-bit address. this register allows the host software to locate all control data structures within the same 4 gbyte memory segment. table 415. offset caplength + 0c - 0fh: frindex?frame index bits name description access 31:1 4 reserved reserved. 13:0 frame list current index/frame number the value in this register increments at the end of each time frame (e.g., micro-frame). bits [12:3] are used for the frame list current index. this means that each location of the frame list is accessed eight times (frames or micro-frames) before moving to the next index. device: 29 function: 7 offset: caplength + 0c-0fh attribute: read/write default value: 00000000h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 516 order number: 300641-004us 11.2.2.6 offset caplength + 14 - 17h: periodiclistbase? periodic frame list base address note: this 32-bit register contains the beginning address of the periodic frame list in the system memory. since the intel ? 6300ESB ich host controller operates in 64-bit mode (as indicated by the ?1? in the 64-bit addressing capability field in the hccsparams register), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. hcd loads this register prior to starting the schedule execution by the host controller. the memory structure referenced by this physical memory pointer is assumed to be 4-kbyte aligned. the contents of this register are combined with the frame index register (frindex) to enable the host controller to step through the periodic frame list in sequence. 11.2.2.7 offset caplength + 18 - 1bh: asynclistaddr?current asynchronous list address note: this 32-bit register contains the address of the next asynchronous queue head to be executed. since the intel ? 6300ESB ich host controller operates in 64-bit mode (as indicated by a ?1? in 64-bit addressing capability field in the hccparams register), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. bits [4:0] of this register cannot be modified by system software and will always return ?0?s when read. the memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. table 416. offset caplength + 10 - 13h: ctrldssegment?control data structure segment register bits name description access 31:0 upper address[63:32] this 32-bit field corresponds to address bits 63:32 when forming a control data structure address. rw table 417. offset caplength + 14 - 17h: periodiclistbase?periodic frame list base address bits name description access 31:1 2 base address (low) these bits correspond to memory address signals [31:12], respectively. rw 11:0 reserved reserved. must be written as ?0?s. during runtime, the value of these bits are undefined. device: 29 function: 7 offset: caplength + 10-13h attribute: read/write default value: 00000000h size: 32-bit device: 29 function: 7 offset: caplength + 14-17h attribute: read/write default value: 00000000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 517 11?intel ? 6300ESB ich 11.2.2.8 offset caplength + 40 - 43h: configflag?configure flag register 11.2.2.9 portsc- port n status and control note: a host controller must implement one or more port registers. software uses the n_port information from the structural parameters register to determine how many ports need to be serviced. all ports have the structure defined below. software must not write to unreported port status and control registers. this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. the initial conditions of a port are: 1. no device connected. 2. port disabled. when a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. refer to section 4 of the ehci specification for operational requirements for how change events interact with port suspend mode 3. when a port is being used as the debug port, the port may report device connected and enabled when the configured flag is a ?0?. table 418. offset caplength + 18 - 1bh: asynclistaddr?current asynchronous list address bits name description access 31:5 link pointer low (lpl) these bits correspond to memory address signals [31:5], respectively. this field may only reference a queue head (qh). rw 4:0 reserved reserved. these bits are reserved and their value has no effect on operation. table 419. offset caplength + 40 - 43h: configflag?configure flag register bits name description access 31:1 reserved reserved. read from this field will always return 0. 0configure flag (cf) default 0b. host software sets this bit as the last action in its process of configuring the host controller. this bit controls the default port-routing control logic. bit values and side effects are listed below. see section 4 of the ehci specification for operational details. 0 = port routing control logic default?routes each port to the classic host controllers. 1 = port routing control logic default?routes all ports to this host controller. rw device: 29 function: 7 offset: caplength + 18-1bh attribute: read/write default value: 00000000h size: 32-bit device: 29 function: 7 offset: caplength + 40-43h attribute: read/write default value: 00000000h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 518 order number: 300641-004us table 420. portsc- port n status and control (sheet 1 of 4) bits name description access 31:2 3 reserved reserved. these bits are reserved for future use and will return a value of ?0? when read. 22 wake on over-current enable (wkoc_e) default = 0b. writing this bit to a ?1? enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the over-current active bit (bit 4 of this register) is set. r/w 21 wake on disconnect enable (wkdscnnt_e) default = 0b. writing this bit to a ?1? enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the current connect status changes from connected to disconnected (i.e., bit ?0? of this register changes from ?1? to ?0?). r/w 20 wake on connect enable (wkcnnt_e) default = 0b. writing this bit to a ?1? enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the current connect status changes from disconnected to connected (i.e., bit ?0? of this register changes from ?0? to ?1?). note: this feature is not supported. r/w 19:1 6 port test control default = 0000b. when this field is ?0?, the port is not operating in a test mode. a non-?0? value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. the encoding of the test mode bits is (0110b - 1111b are reserved): bits test mode 0000b test mode not enabled 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b test force_enable refer to chapter 7 of the usb specification, revision 2.0, for details on each test mode. r/w 15:1 4 reserved should be written to =00b; other values will result in unspecified behavior. r/w 13 port owner default = 1b. this bit unconditionally goes to a ?0? when the configured flag bit makes a ?0? to ?1? transition.this bit unconditionally goes to 1b whenever the configure flag bit is ?0? system software uses this field to release ownership of the port to a selected host controller in the event that the attached device is not a high-speed device. software writes a ?1? to this bit when the attached device is not a high-speed device. a ?1? in this bit means that a companion host controller owns and controls the port. see section 4 of the ehci specification for operational details. r/w 12 port power (pp) read-only with a value of ?1?. this indicates that the port does have power. ro device: 29 function: 7 offset: port 0:caplength+44-47h port 1: caplength+48-4bh port 2: caplength+4c-4fh port 3: caplength+50-53h attribute: read/write default value: 00003000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 519 11?intel ? 6300ESB ich 11:1 0 line status these bits reflect the current logical levels of the d+ (bit 11) and d- (bit 10) signal lines. these bits are used for detection of low-speed usb devices prior to the port reset and enable sequence. this field is valid only when the port enable bit is ?0? and the current connect status bit is set to a ?1?. the encoding of the bits are: bits[11:10] meaning 00 se0 - not low-speed device, perform ehci reset 10 j-state - not low-speed device, perform ehci reset 01 k-state - low speed device, release ownership of port 11 undefined - not low-speed device, perform ehci reset ro 9 reserved reserved. this bit will return a ?0? when read. 8port reset default = 0 1 = port is in reset. 0 = port is not in reset. when software writes a ?1? to this bit from a ?0?, the bus reset sequence as defined in the usb specification revision 2.0 is started. software writes a ?0? to this bit to terminate the bus reset sequence. software must keep this bit at a ?1? long enough to ensure the reset sequence, as specified in the usb specification revision 2.0, completes. note: when software writes this bit to a ?1?, it must also write a ?0? to the port enable bit. when software writes a ?0? to this bit there may be a delay before the bit status changes to a ?0?. the bit status will not read as a ?0? until after the reset has completed. when the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g., set the port enable bit to a ?1?). a host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a ?1? to a ?0?. for example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a ?0?. the hchalted bit in the usbsts register should be a ?0? before software attempts to use this bit. the host controller may hold port reset asserted to a ?1? when the hchalted bit is a ?1?. this field is ?0? if port power is ?0?. warning: system software should not attempt to reset a port when the hchalted bit in the usbsts register is a ?1?. doing so will result in undefined behavior. r/w table 420. portsc- port n status and control (sheet 2 of 4) bits name description access device: 29 function: 7 offset: port 0:caplength+44-47h port 1: caplength+48-4bh port 2: caplength+4c-4fh port 3: caplength+50-53h attribute: read/write default value: 00003000h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 520 order number: 300641-004us 7suspend 1 = port in suspend state. 0 = port not in suspend state. default = 0. port enabled bit and suspend bit of this register define the port states as follows: bits [port enabled, suspend] port state 0x disable 10 enable 11 suspend when in suspend state, downstream propagation of data is blocked on this port, except for port reset. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port depending on the activity on the port. the host controller will unconditionally set this bit to a ?0? when software sets the force port resume bit to a ?0? (from a ?1?). a write of ?0? to this bit is ignored by the host controller. when host software sets this bit to a ?1? when the port is not enabled (i.e., port enabled bit is a ?0?), the results are undefined. r/w 6force port resume 1 = resume detected/driven on port. 0 = no resume (k- state) detected/driven on port. default = 0. software sets this bit to a ?1? to drive resume signaling. the host controller sets this bit to a ?1? when a j-to-k transition is detected while the port is in the suspend state. when this bit transitions to a ?1? because a j-to-k transition is detected, the port change detect bit in the usbsts register is also set to a ?1?. when software sets this bit to a ?1?, the host controller must not set the port change detect bit. note that when the ehci controller owns the port, the resume sequence follows the defined sequence documented in the usb specification revision 2.0. the resume signaling (full-speed 'k') is driven on the port as long as this bit remains a ?1?. software must appropriately time the resume and set this bit to a ?0? when the appropriate amount of time has elapsed. writing a ?0? (from ?1?) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). this bit will remain a ?1? until the port has switched to the high-speed idle. r/w 5 overcurrent change default = 0. 1 = this bit gets set to a ?1? when there is a change to over-current active. software clears this bit by writing a ?1? to this bit position. the functionality of this bit is not dependent upon the port owner. r/wc table 420. portsc- port n status and control (sheet 3 of 4) bits name description access device: 29 function: 7 offset: port 0:caplength+44-47h port 1: caplength+48-4bh port 2: caplength+4c-4fh port 3: caplength+50-53h attribute: read/write default value: 00003000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 521 11?intel ? 6300ESB ich 4 overcurrent active default = 0. 1 = this port currently has an over-current condition. 0 = this port does not have an over-current condition. this bit will automatically transition from a ?1? to a ?0? when the over current condition is removed. the intel ? 6300ESB ich automatically disables the port when the over-current active bit is ?1?. ro 3 port enable/disable change 0 = no change in status. this is the default setting. 1 = port enabled/disabled status has changed. for the root hub, this bit gets set to a ?1? only when a port is disabled due to the appropriate conditions existing at the eof2 point. (see chapter 11 of the usb specification for the definition of a port error.) this bit is not set due to the disabled-to-enabled transition, nor due to a disconnect. software clears this bit by writing a ?1? to it. r/wc 2 port enabled/disabled 1 = enable. 0 = disable. default = 0. ports may only be enabled by the host controller as a part of the reset and enable. software cannot enable a port by writing a ?1? to this field. ports may be disabled by either a fault condition (disconnect event or other fault condition) or by host software. note that the bit status does not change until the port state actually changes. there may be a delay in disabling or enabling a port due to other host controller and bus events. r/w 1connect status change 1 = change in current connect status. 0 = no change. default = 0. indicates a change has occurred in the port?s current connect status. the host controller sets this bit for all changes to the port device connect status, even when system software has not cleared an existing connect status change. for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ?setting? an already-set bit (i.e., the bit will remain set). software sets this bit to ?0? by writing a ?1? to it. r/wc 0 current connect status 1 = device is present on port. 0 = no device is present. default = 0. this value reflects the current state of the port, and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. ro table 420. portsc- port n status and control (sheet 4 of 4) bits name description access device: 29 function: 7 offset: port 0:caplength+44-47h port 1: caplength+48-4bh port 2: caplength+4c-4fh port 3: caplength+50-53h attribute: read/write default value: 00003000h size: 32-bit
11? intel ? 6300ESB ich intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 522 11.2.3 usb 2.0-based debug port register the debug port?s registers are located in the same memory area, defined by the base address register (bar) as the standard ehci registers. the base offset for the debug port registers is declared in the debug port base offset capability register at configuration offset 5ah. the specific ehci port that supports this debug capability is indicated by a 4-bit field (bits 20-23) in the hcsparams register of the ehci controller. the map of the debug port registers is shown below. each register is defined individually. 11.2.3.1 offset 00h: control/status register offset register type 00h control/status register read/write 04h usb pids read/write 08h data buffer (bytes 3:0) read/write 0ch data buffer (bytes 7:4) read/write 10h config register read/write notes: 1. all of these registers are implemented in the core well and reset by pxpcirst#, ehc hcreset, and a ehc d3-to-d0 transition . 2. the hardware associated with this register provides no checks to ensure that software programs the interface correctly. how the hardware behaves when programmed illegally is undefined. table 421. offset 00h: control/status register (sheet 1 of 3) bits name description access 31 reserved. reserved. 30 owner_cnt when software writes a ?1? to this bit, the ownership of the debug port is forced to the ehci controller (i.e., immediately taken away from the companion classic usb host controller). when the port was already owned by the ehci controller, setting this bit has no effect. this bit overrides all of the ownership-related bits in the standard ehci registers. reset default is ?0?. r/w 29 reserved reserved. 28 enabled_cnt this bit = ?1? when the debug port is enabled for operation. software may clear this by writing a ?0? to it. the hardware clears the bit for the same conditions where the port enable/ disable change bit (in the portsc register) is set. software may directly set this bit when the port is already enabled in the associated port status and control register (this is enforced by the hardware). reset default is ?0?. 27:1 7 reserved reserved. device: 29 function: 7 offset: 00h attribute: read/write default value: 0000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 523 11?intel ? 6300ESB ich 16 done_sts this bit is set by hardware to indicate that the request is complete. writing a ?1? to this bit will clear it when it is set. writing a ?0? to this bit has no effect. reset default is ?0?. r/wc 15:1 2 link_id_sts this field identifies the link interface. it is hardwired to 0h to indicate that it is a usb debug port. ro 11 reserved reserved. this bit will return ?0? when read. writes will have no effect. 10 in_use_cnt set by software to indicate that the port is in use. cleared by software to indicate that the port is free and may be used by other software. this bit is cleared after reset. (this bit has no affect on hardware.) 9:7 exception_sts default=000b this field indicates the exception when the error_good#_sts bit is set. this field should be ignored when the error_good#_sts bit is 0. 000 no error. note: this should not be seen, since this field should only be checked when there is an error. 001 transaction error: indicates the usb ehci transaction had an error (crc, bad pid, timeout, etc.) 010 hardware error: request was attempted (or in progress) when port was suspended or reset. all others are reserved. ro 6 error_good#_sts the hardware clears this bit to ?0? upon the proper completion of a read or write. the hardware sets this bit to indicate that an error has occurred. details on the nature of the error are provided in the exception field. reset default = 0. ro 5go_cnt 0 = hardware clears this bit when hardware sets the done_sts bit. default is 0. 1 = causes hardware to perform a read or write request. writing a ?1? to this bit when it is already set may result in undefined behavior. wo table 421. offset 00h: control/status register (sheet 2 of 3) bits name description access device: 29 function: 7 offset: 00h attribute: read/write default value: 0000h size: 32-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 524 order number: 300641-004us 4write_read#_cnt: software sets this bit to indicate that the current request is a write. software clears this bit to indicate that the current request is a read. reset default is ?0?. r/w 3:0 data_len_cnt this field is used to indicate the size of the data to be transferred. reset default = 0h. for write operations, this field is set by software to indicate to the hardware how many bytes of data in data buffer are to be transferred to the console. a value of 0h indicates that a zero- length packet should be sent. a value of 1-8 indicates 1-8 bytes are to be transferred. values 9-fh are illegal, and how hardware behaves when used is undefined. for read operations, this field is set by hardware to indicate to software how many bytes in data buffer are valid in response to a read operation. a value of 0h indicates that a zero-length packet was returned and the state of data buffer is not defined. a value of 1-8 indicates 1-8 bytes were received. hardware is not allowed to return values 9-fh. the transferring of data always starts with byte ?0? in the data area and moves toward byte 7 until the transfer size is reached. r/w notes: 1. software should do read-modify-write operations to this register to preserve the contents of bits not being modified. this include reserved bits. 2. to preserve the usage of reserved bits in the future, software should always write the same value read from the bit until it is defined. reserved bits will always return ?0? when read. table 421. offset 00h: control/status register (sheet 3 of 3) bits name description access device: 29 function: 7 offset: 00h attribute: read/write default value: 0000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 525 11?intel ? 6300ESB ich 11.2.3.2 offset 04h: usb pids register 11.2.3.3 offset 08h: data buffer bytes 7:0 table 422. offset 04h: usb pids register bits name description access 31:2 4 reserved reserved. these bits will return ?0? when read. writes will have no effect. 23:1 6 received_pid_sts[23: 16] the hardware updates this field with the received pid for transactions in either direction. when the controller is writing data, this field is updated with the handshake pid that is received from the device. when the host controller is reading data, this field is updated with the data packet pid (when the device sent data), or the handshake pid (when the device naks the request). this field is valid when the hardware clears the go_done#_cnt bit. 15:8 send_pid_cnt[15:8] the hardware sends this pid to begin the data packet when sending data to usb (i.e., write_read#_cnt is asserted). software will typically set this field to either data0 or data1 pid values. 7:0 token_pid_cnt[7:0]: the hardware sends this pid as the token pid for each usb transaction. software will typically set this field to either in, out or setup pid values. note: this dword register is used to communicate pid information between the usb debug driver and the usb debug port. the debug port uses some of these fields to generate usb packets, and uses other fields to return pid information to the usb debug driver. table 423. offset 08h: data buffer bytes 7:0 bits name description access 63:0 databuffer[63:0 these are the 8 bytes of the data buffer. bits 7:0 correspond to least significant byte (byte 0). bits 63:56 correspond to the most significant byte (byte 7). the bytes in the data buffer must be written with data before software initiates a write request. for a read request, the data buffer contains valid data when done_sts bit is cleared by the hardware, error_good#_sts is cleared by the hardware, and the data_length_cnt field indicates the number of bytes that are valid. note: this register may be accessed as eight separate 8-bit registers or two separate 32-bit registers. device: 29 function: 7 offset: 04h attribute: read/write default value: tbd size: 32-bit device: 29 function: 7 offset: 08h attribute: read/write default value: 0000000000000000h size: 64-bit
intel ? 6300ESB ich?11 intel ? 6300ESB i/o controller hub ds november 2007 526 order number: 300641-004us 11.2.3.4 offset 10h: config register table 424. offset 10h: config register bits name description access 31:1 5 reserved reserved. 14:8 usb_address_cnf this 7-bit field identifies the usb device address used by the controller for all token pid generation. this is a r/w field that is set to 7fh after reset. 7:4 reserved reserved. 3:0 usb_endpoint_cnf this 4-bit field identifies the endpoint used by the controller for all token pid generation. this is a r/w field that is set to 01h after reset. device: 29 function: 7 offset: 10h attribute: read/write default value: tbd size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 527 12?intel ? 6300ESB ich smbus controller registers (d31:f3) 12 12.1 pci configuration registers (smbus? d31:f3) 12.1.1 offset 00 - 01h: vid?vendor identification register (smbus?d31:f3) offset mnemonic register name/ function default type 00-01h vid vendor id 8086 ro 02-03h did device id 25a4 ro 04-05h cmd command register 0000h r/w 06-07h sta device status 0280h r/w 08h rid revision id see note 1 ro 09h pi programming interface 00h ro 0ah scc sub class code 05h ro 0bh bcc base class code 0ch ro 20-23h smb_base smbus base address register 00000001h r/w 2c-2dh svid subsystem vendor id 0000h ro 2e-2fh sid subsystem id 0000h ro 3ch intr_ln interrupt line 00h r/w 3dh intr_pn interrupt pin 02h ro 40h hostc host configuration 00h r/w notes: 1. refer to the intel ? 6300ESB i/o controller hub specification update for the value of the revision id register. 2. registers that are not shown should be treated as reserved (see section 6.2, ?pci configuration map? on page 277 for details). table 425. offset 00 - 01h: vid?vendor identification register (smbus? d31:f3) bits name description access 15:0 vendor id value this is a 16-bit value assigned to intel. ro device: 31 function: 3 offset: 00-01h attribute: read-only default value: 8086h size: 16-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 528 order number: 300641-004us 12.1.2 offset 02 - 03h: did?device identification register (smbus?d31:f3) 12.1.3 offset 04 - 05h: cmd?command register (smbus?d31:f3) table 426. offset 02 - 03h: did?device identification register (smbus? d31:f3) bits name description access 15:0 device id value ro table 427. offset 04 - 05h: cmd?command register (smbus?d31:f3) bits name description access 15:1 0 reserved reserved. 9 fast back-to-back enable (fbe) reserved as ?0?. ro 8 serr# enable (serren) reserved as ?0?. ro 7 wait cycle control (wcc) reserved as ?0?. ro 6 parity error response (per) reserved as ?0?. ro 5 vga palette snoop (vps) reserved as ?0?. ro 4 postable memory write enable (pmwe) reserved as ?0?. ro 3 special cycle enable (sce) reserved as ?0?. ro 2 bus master enable (bme) reserved as ?0?. ro 1 memory space enable (mse) reserved as ?0?. ro 0 i/o space enable (iose) 0 = disable 1 = enables access to the sm bus i/o space registers as defined by the base address register. r/w device: 31 function: 3 offset: 02-03h attribute: read-only default value: 25a4h size: 16-bit device: 31 function: 3 offset: 04-05h attribute: read-only, read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 529 12?intel ? 6300ESB ich 12.1.4 offset 06 - 07h: sta?device status register (smbus?d31:f3) 12.1.5 offset 08h: rid?revision id register (smbus? d31:f3) table 428. offset 06 - 07h: sta?device status register (smbus?d31:f3) bits name description access 15 detected parity error (dpe) reserved as ?0?. ro 14 signaled system error (sse) reserved as ?0?. ro 13 received master abort (rma) reserved as ?0?. ro 12 received target abort (rta) reserved as ?0?. ro 11 signaled target-abort status reserved as ?0?. r/wc 10:9 devsel# timing status (devt) reserved as ?0?. ro 8 data parity error detected reserved as ?0?. ro 7 fast back-to-back capable reserved as ?0?. ro 6 user definable features (udf) reserved as ?0?. ro 5 66 mhz capable reserved as ?0?. ro 4:0 reserved reserved. table 429. offset 08h: rid?revision id register (smbus?d31:f3) bits name description access 7:0 revision id value refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. ro device: 31 function: 3 offset: 06-07h attribute: read-only, read/write clear default value: 0280h size: 16-bit device: 31 function: 3 offset: 08h attribute: read-only default value: see bit description size: 8-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 530 order number: 300641-004us 12.1.6 offset 09h: pi?programming interface (smbus? d31:f3) 12.1.7 offset 0ah: scc?sub class code register (smbus?d31:f3) 12.1.8 offset 0bh: bcc?base class code register (smbus?d31:f3) table 430. offset 09h: pi?programming interface (smbus?d31:f3) bits name description access 7:0 programming interface ro table 431. offset 0ah: scc?sub class code register (smbus?d31:f3) bits name description access 7:0 sub class code 05h = sm bus serial controller ro table 432. offset 0bh: bcc?base class code register (smbus?d31:f3) bits name description access 7:0 base class code 0ch = serial controller. ro device: 31 function: 3 offset: 09h attribute: read-only default value: 00h size: 8-bit device: 31 function: 3 offset: 0ah attribute: read-only default value: 05h size: 8-bit device: 31 function: 3 offset: 0bh attribute: read-only default value: 0ch size: 8bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 531 12?intel ? 6300ESB ich 12.1.9 offset 20 - 23h: smb_base?smbus base address register (smbus?d31:f3) 12.1.10 offset 2ch - 2dh: svid?subsystem vendor id (smbus?d31:f2/f4) table 433. offset 20 - 23h: smb_base?smbus base address register (smbus?d31:f3) bits name description access 31:1 6 reserved reserved. ro 15:5 base address provides the 32-byte system i/o base address for the intel ? 6300ESB ich smb logic. r/w 4:1 reserved reserved. ro 0io space indicator this read-only bit is always ?1?, indicating that the smb logic is i/o mapped. ro table 434. offset 2ch - 2dh: svid?subsystem vendor id (smbus?d31:f2/ f4) bits name description access 15:0 subsystem vendor id (svid) the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads from this register is the same as that which was written by bios into the ide_svid register. ro device: 31 function: 3 offset: 20-23h attribute: read/write default value: 00000001h size: 32-bit device: 31 function: 3 offset: 2ch-2dh attribute: read-only default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 532 order number: 300641-004us 12.1.11 offset 2eh - 2fh: sid?subsystem id (smbus? d31:f2/f4) 12.1.12 offset 3ch: intr_ln?interrupt line register (smbus?d31:f3) 12.1.13 offset 3dh: intr_pn?interrupt pin register (smbus?d31:f3) table 435. offset 2eh - 2fh: sid?subsystem id (smbus?d31:f2/f4) bits name description access 15:0 subsystem id (sid) the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads from this register is the same as that which was written by bios into the ide_sid register. ro table 436. offset 3ch: intr_ln?interrupt line register (smbus?d31:f3) bits name description access 7:0 interrupt line this data is not used by the intel ? 6300ESB ich. it is to communicate to software that the interrupt line is connected to pirqb#. r/w table 437. offset 3dh: intr_pn?interrupt pin register (smbus?d31:f3) bits name description access 7:0 interrupt pin 02h = indicates that the intel ? 6300ESB ich smbus controller will drive pirqb# as its interrupt line. ro device: 31 function: 3 offset: 2eh-2fh attribute: read-only default value: 0000h size: 16-bit lockable: no power well: core device: 31 function: 3 offset: 3ch attribute: read/write default value: 00h size: 8-bit device: 31 function: 3 offset: 3dh attribute: read-only default value: 02h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 533 12?intel ? 6300ESB ich 12.1.14 offset 40h: hostc?host configuration register (smbus?d31:f3) 12.2 smbus i/o registers table 438. offset 40h: hostc?host configuration register (smbus?d31:f3) bits name description access 7:3 reserved reserved. 2i 2 c_en 0 = smbus behavior. 1 = the intel ? 6300ESB ich is enabled to communicate with i 2 c devices. this will change the formatting of some commands. r/w 1 smb_smi_en 0 = smbus interrupts will not generate an smi#. 1 = any source of an smb interrupt will instead be routed to generate an smi#. refer to section 5.19.5, ?interrupts/ smi#? . this bit needs to be set for smbalert# to be enabled. r/w 0 hst_en: smbus host enable 0 = disable the smbus host controller. 1 = enable. the smb host controller interface is enabled to execute commands. the intren bit must be enabled for the smb host controller to interrupt or smi#. the smb host controller will not respond to any new requests until all interrupt requests have been cleared. r/w table 439. smb i/o registers (sheet 1 of 2) offset mnemonic register name/function default access 00h hst_sts host status 00h r/wc 02h hst_cnt host control 00h r/w 03h hst_cmd host command 00h r/w 04h xmit_slva transmit slave address 00h r/w 05h hst_d0 host data 0 00h r/w 06h hst_d1 host data 1 00h r/w 07h host_block_db host block data byte 00h r/w 08h pec packet error check 00h r/w 09h rcv_slva receive slave address 44h r/w 0a- 0bh slv_data slave data 0000h r/w 0ch aux_sts auxiliary status 00h r/wc 0dh aux_ctl auxiliary control 00h r/w device: 31 function: 3 offset: 40h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 534 order number: 300641-004us 12.2.1 offset 00h: hst_sts?host status register note: all status bits are set by hardware and cleared by the software writing a ?1? to the particular bit position. writing a ?0? to any bit position has no effect. 0eh smlink_pin_ctl smlink pin control see register description r/w 0fh smbus_pin_ctl smbus pin control see register description r/w 10h slv_sts slave status 00h r/wc 11h slv_cmd slave command 00h r/w 14h notify_daddr notify device address 00h ro 16h notify_dlow notify data low byte 00h ro 17h notify_dhigh notify data high byte 00h ro table 439. smb i/o registers (sheet 2 of 2) offset mnemonic register name/function default access
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 535 12?intel ? 6300ESB ich table 440. offset 00h: hst_sts?host status register (sheet 1 of 2) bits name description access 7byte_done_sts this bit will be set to ?1? when the host controller has received a byte (for block read commands) or when it has completed transmission of a byte (for block write commands) when the 32-byte buffer is not being used. note that this bit will be set even on the last byte of the transfer. software clears the bit by writing a ?1? to the bit position. this bit is not set when transmission is due to an external lan controller interface heartbeat. this bit has no meaning for block transfers when the 32-byte buffer is enabled. note: when the last byte of a block message is received, the host controller will set this bit. however, it will not immediately set the intr bit (bit 1 in this register). when the interrupt handler clears the byte_done_sts bit, another interrupt may be generated if the intr bit is set. thus, for a block message of n bytes, the intel ? 6300ESB ich will generate n+1 interrupts. the interrupt handler needs to be implemented to handle these cases. r/wc 6inuse_sts this bit is used as semaphore among various independent software threads that may need to use the intel ? 6300ESB ich?s smbus logic and has no other effect on hardware. 0 = after a full pci reset, a read to this bit returns a ?0?. 1 = after the first read, subsequent reads will return a ?1?. a write of a ?1? to this bit will reset the next read value to ?0?. writing a ?0? to this bit has no effect. software may poll this bit until it reads a 0 and will then own the usage of the host controller. r/wc (special) 5 smbalert_sts 0 = interrupt or smi# was not generated by smbalert#. 1 = the source of the interrupt or smi# was the smbalert# signal. this bit is only cleared by software writing a ?1? to the bit position or by rsmrst# going low. when the signal is programmed as a gpio, this bit will never be set. r/wc 4failed 0 = cleared by writing a ?1? to the bit position. 1 = the source of the interrupt or smi# was a failed bus transaction. this bit is set in response to the kill bit being set to terminate the host transaction. r/wc 3bus_err 0 = cleared by writing a ?1? to the bit position. 1 = the source of the interrupt of smi# was a transaction collision. r/wc device: 31 function: 3 offset: 00h attribute: read/write clear default value: 00h size: 8-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 536 order number: 300641-004us 2dev_err 0 = software resets this bit by writing a ?1? to this location. the intel ? 6300ESB ich will then deassert the interrupt or smi#. 1 = the source of the interrupt or smi# was due to one of the following: - illegal command field - unclaimed cycle (host initiated) - host device time-out error - crc error r/wc 1intr this bit may be set only by termination of a command. intr is not dependent on the intren bit of the host controller register (offset 02h). it is only dependent on the termination of the command. when the intren bit is not set, the intr bit will be set, although the interrupt will not be generated. software may poll the intr bit in this non-interrupt case. 0 = software resets this bit by writing ?1? to this location. the intel ? 6300ESB ich will then deassert the interrupt or smi#. 1 = the source of the interrupt or smi# was the successful completion of its last command. r/wc (special) 0host_busy 0 = cleared by the intel ? 6300ESB ich when the current transaction is completed. 1 = indicates that the intel ? 6300ESB ich is running a command from the host interface. no smb registers should be accessed while this bit is set, except the block data byte register. the block data byte register may be accessed when this bit is set only when the smb_cmd bits in the host control register are programmed for block command or i 2 c read command. this is necessary in order to check the byte_done_sts bit. ro table 440. offset 00h: hst_sts?host status register (sheet 2 of 2) bits name description access device: 31 function: 3 offset: 00h attribute: read/write clear default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 537 12?intel ? 6300ESB ich 12.2.2 offset 02h: hst_cnt?host control register note: a read to this register will clear the byte pointer of the 32-byte buffer. table 441. offset 02h: hst_cnt?host control register (sheet 1 of 3) bits name description access 7pec_en 0 = smbus host controller does not perform the transaction with the pec phase appended. 1 = causes the host controller to perform the smbus transaction with the packet error checking phase appended. for writes, the value of the pec byte is transferred from the pec register. for reads, the pec byte is loaded into the pec register. this bit must be written prior to the write in which the start bit is set. r/w 6start 0 = this bit will always return ?0? on reads. the host_busy bit in the host status register (offset 00h) may be used to identify when the intel ? 6300ESB ich has finished the command. 1 = writing a ?1? to this bit initiates the command described in the smb_cmd field. all registers should be setup prior to writing a ?1? to this bit position. wo 5 last_byte this bit is used for block read commands. 1 = software sets this bit to indicate that the next byte will be the last byte to be received for the block. this causes the intel ? 6300ESB ich to send a nack (instead of an ack) after receiving the last byte. note: once the second_to_sts bit in tco2_sts register (d31:f0, tcobase+6h, bit 1) is set, the last_byte bit also gets set. while the second_to_sts bit is set, the last_byte bit cannot be cleared. this prevents the intel ? 6300ESB ich from running some of the smbus commands (block read/write, i 2 c read, block i 2 c write). wo device: 31 function: 3 offset: 02h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 538 order number: 300641-004us 4:2 smb_cmd the bit encoding below indicates which command the intel ? 6300ESB ich is to perform. when enabled, the intel ? 6300ESB ich will generate an interrupt or smi# when the command has completed. when the value is for a non- supported or reserved command, the intel ? 6300ESB ich will set the device error (dev_err) status bit and generate an interrupt when the start bit is set. the intel ? 6300ESB ich will not operate until dev_err is cleared. 000 = quick: the slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = byte: this command uses the transmit slave address and command registers. bit 0 of the slave address register determines if this is a read or write command. 010 = byte data: this command uses the transmit slave address, command, and data0 registers. bit 0 of the slave address register determines if this is a read or write command. when it is a read, the data0 register will contain the read data. 011 = word data: this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. when it is a read, after the command completes, the data0 and data1 registers will contain the read data. 100 = process call: this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. after the command completes, the data0 and data1 registers will contain the read data. 101 = block: this command uses the transmit slave address, command, data0 registers, and the block data byte register. for block write, the count is stored in the data0 register and indicates how many bytes of data will be transferred. for block reads, the count is received and stored in the data0 register. bit 0 of the slave address register selects if this is a read or write command. for writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. 110 = i 2 c read: this command uses the transmit slave address, command, data0, data1 registers, and the block data byte register. the read data is stored in the block data byte register. the intel ? 6300ESB ich will continue reading data until the nak is received. 111 = block process: this command uses the transmit slave address, command, data0 and the block data byte register. for block write, the count is stored in the data0 register and indicates how many bytes of data will be transferred. for block read, the count is received and stored in the data0 register. bit 0 of the slave address register always indicate a write command. for writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. note: e32b bit in the auxiliary control register must be set for this command to work. r/w table 441. offset 02h: hst_cnt?host control register (sheet 2 of 3) bits name description access device: 31 function: 3 offset: 02h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 539 12?intel ? 6300ESB ich 12.2.3 offset 03h: hst_cmd?host command register 12.2.4 offset 04h: xmit_slva?transmit slave address register note: this register is transmitted by the host controller in the slave address field of the smbus protocol. 1kill 0 = normal smbus host controller functionality. 1 = when set, kills the current host transaction taking place, sets the failed status bit, and asserts the interrupt (or smi#). this bit, once set, must be cleared by software to allow the smbus host controller to function normally. r/w 0intren 0 = disable. 1 = enable the generation of an interrupt or smi# upon the completion of the command. r/w table 442. offset 03h: hst_cmd?host command register bits name description access 7:0 this 8-bit field is transmitted by the host controller in the command field of the smbus protocol during the execution of any command. r/w table 443. offset 04h: xmit_slva?transmit slave address register bits name description access address 7-bit address of the targeted slave. r/w rw direction of the host transfer. 0 = write 1 = read r/w table 441. offset 02h: hst_cnt?host control register (sheet 3 of 3) bits name description access device: 31 function: 3 offset: 02h attribute: read/write default value: 00h size: 8-bit device: 31 function: 3 offset: 03h attribute: read/write default value: 00h size: 8-bit device: 31 function: 3 offset: 04h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 540 order number: 300641-004us 12.2.5 offset 05h: hst_d0?data 0 register 12.2.6 offset 06h: hst_d1?data 1 register table 444. offset 05h: hst_d0?data 0 register bits name description access 7:0 data0/count this field contains the eight-bit data sent in the data0 field of the smbus protocol. for block write commands, this register reflects the number of bytes to transfer. this register should be programmed to a value between 1 and 32 for block counts. a count of 0 or a count above 32 will result in unpredictable behavior. the host controller does not check or log illegal block counts. r/w table 445. offset 06h: hst_d1?data 1 register bits name description access 7:0 data1 this eight-bit register is transmitted in the data1 field of the smbus protocol during the execution of any command. r/w device: 31 function: 3 offset: 05h attribute: read/write default value: 00h size: 8-bit device: 31 function: 3 offset: 06h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 541 12?intel ? 6300ESB ich 12.2.7 offset 07h: host_block_db?host block data byte register table 446. offset 07h: host_block_db?host block data byte register bits name description access 7:0 block data (bdta) this is either a register or a pointer into a 32-byte block array, depending upon whether the e32b bit is set in the auxiliary control register. when the e32b bit is cleared, this is a register containing a byte of data to be sent on a block write or read from on a block read. when the e32b bit is set, reads and writes to this register are used to access the 32-byte block data storage array. an internal index pointer is used to address the array, which is reset to ?0? by reading the hctl register (offset 02h). the index pointer then increments automatically upon each access to this register. the transfer of block data into (read) or out of (write) this storage array during an smbus transaction always starts at index address 0. when the e2b bit is set, for writes, software will write up to 32 bytes to this register as part of the setup for the command. after the host controller has sent the address, command, and byte count fields, it will send the bytes in the sram pointed to by this register. after the byte count has been exhausted, the controller will set the byte_done_sts bit . see section 12.2.1 ,hst_sts-host status register, bit 7. when the e2b bit is cleared for writes, software will place a single byte in this register. after the host controller has sent the address, command, and byte count fields, it will send the byte in this register. when there is more data to send, software will write the next series of bytes to the sram pointed to by this register and clear the byte_done_sts bit. the controller will then send the next byte. during the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait states on the interface. when the e2b bit is set for reads, after receiving the byte count into the data0 register, the first series of data bytes go into the sram pointed to by this register. when the byte count has been exhausted or the 32-byte sram has been filled, the controller will generate an smi# or interrupt (depending on configuration) and set the byte_done_sts bit. software will then read the data. during the time between when the last byte is read from the sram to when the byte_done_sts bit is cleared, the controller will insert wait states on the interface. r/w device: 31 function: 3 offset: 07h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 542 order number: 300641-004us 12.2.8 offset 08h: pec?packet error check register 12.2.9 offset 09h: rcv_slva?receive slave address register table 447. offset 08h: pec?packet error check register bits name description access 7:0 pec_data this 8-bit register is written with the 8-bit crc value that is used as the smbus pec data prior to a write transaction. for read transactions, the pec data is loaded from the smbus into this register and is then read by software. software must ensure that the inuse_sts bit is properly maintained to avoid having this field overwritten by a write transaction following a read transaction. r/w table 448. offset 09h: rcv_slva?receive slave address register bits name description access 7 reserved reserved. 6:0 slave_addr this field is the slave address that the intel ? 6300ESB ich decodes for read and write cycles. the default is not 0, so the smbus slave interface may respond even before the processor comes up or if the processor is dead. this register is cleared by rsmrst#, but not by pxpcirst#. r/w device: 31 function: 3 offset: 08h attribute: read/write default value: 00h size: 8-bit device: 31 function: 3 offset: 09h attribute: read/write default value: 44h size: 8-bit lockable: no power well: resume
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 543 12?intel ? 6300ESB ich 12.2.10 offset 0ah: slv_data?receive slave data register note: this register contains the 16-bit data value written by the external smbus master. the processor may then read the value from this register. this register is reset by rsmrst# but not pxpcirst#. 12.2.11 offset 0ch: aux_sts?auxiliary status register table 449. offset 0ah: slv_data?receive slave data register bits name description access 15:8 data_msg1: data message byte 1 see section 5.19.8, ?smbus slave interface? for a discussion of this field. ro 7:0 data_msg0: data message byte 0 see section 5.19.8, ?smbus slave interface? for a discussion of this field. ro table 450. offset 0ch: aux_sts?auxiliary status register bits name description access 7:2 reserved reserved. 1 smbus tco mode (stco) this is the status bit that reflects the strap setting of legacy tco mode vs. advanced tco mode. when set, it indicates that the intel ? 6300ESB ich is in the advanced tco mode. when cleared, the intel ? 6300ESB ich is in the legacy/ compatible tco mode. note: for the intel ? 6300ESB ich this bit is always 0, since advanced tco mode is not supported ro 0 crc error (crce) this bit is set when a received message contained a crc error. when this bit is set, the derr bit of the host status register will also be set. this bit will be set by the controller when a software abort occurs in the middle of the crc portion of the cycle or an abort happens after the intel ? 6300ESB ich has received the final data bit transmitted by an external slave. r/wc device: 31 function: 3 offset: 0ah attribute: read-only default value: 0000h size: 16-bit lockable: no power well: resume device: 31 function: 3 offset: 0ch attribute: read/write clear default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 544 order number: 300641-004us 12.2.12 offset 0dh: aux_ctl?auxiliary control register 12.2.13 offset 0eh: smlink_pin_ctl?smlink pin control register note: this register is in the resume well and is reset by rsmrst#. table 451. offset 0dh: aux_ctl?auxiliary control register bits name description access 7:2 reserved reserved. 1 enable 32-byte buffer (e32b) when set, the host block data register is a pointer into a 32-byte buffer, as opposed to a single register. this enables the block commands to transfer or receive up to 32 bytes before the intel ? 6300ESB ich generates an interrupt. r/w 0 automatically append crc (aac) when set, the intel ? 6300ESB ich will automatically append the crc. this bit must not be changed during smbus transactions, or undetermined behavior will result r/w table 452. offset 0eh: smlink_pin_ctl?smlink pin control register bits name description access 7:3 reserved reserved. 2 smlink_clk_ctl this read/write bit has a default of 1. 0 = the intel ? 6300ESB ich will drive the smlink[0] pin low, independent of what the other smlink logic would otherwise indicate for the smlink[0] pin. 1 = the smlink[0] pin is not overdriven low. the other smlink logic controls the state of the pin. r/w 1 smlink1_cur_sts this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smlink[1] pin. it will be ?1? to indicate high, ?0? to indicate low. this allows software to read the current state of the pin. ro 0 smlink0_cur_sts this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smlink[0] pin. it will be ?1? to indicate high, ?0? to indicate low. this allows software to read the current state of the pin. ro device: 31 function: 3 offset: 0dh attribute: read/write default value: 00h size: 8-bit lockable: no power well: resume device: 31 function: 3 offset: 0eh attribute: read/write default value: see note size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 545 12?intel ? 6300ESB ich 12.2.14 offset 0fh: smbus_pin_ctl?smbus pin control register note: this register is in the resume well and is reset by rsmrst#. 12.2.15 offset 10h: slv_sts?slave status register note: this register is in the resume well and is reset by rsmrst#. all bits in this register are implemented in the 64 khz clock domain. therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. table 453. offset 0fh: smbus_pin_ctl?smbus pin control register bits name description access 7:3 reserved reserved. 2 smbclk_ctl this read/write bit has a default of 1. 1 = the smbclk pin is not overdriven low. the other smbus logic controls the state of the pin. 0 = the intel ? 6300ESB ich will drive the smbclk pin low, independent of what the other smb logic would otherwise indicate for the smbclk pin. r/w 1 smbdata_cur_sts this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smbdata pin. it will be ?1? to indicate high, ?0? to indicate low. this allows software to read the current state of the pin. ro 0smbclk_cur_sts this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smbclk pin. it will be ?1? to indicate high, ?0? to indicate low. this allows software to read the current state of the pin. ro device: 31 function: 3 offset: 0fh attribute: read/write default value: see note size: 8-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 546 order number: 300641-004us 12.2.16 offset 11h: slv_cmd?slave command register note: this register is in the resume well and is reset by rsmrst#. table 454. offset 10h: slv_sts?slave status register bits name description access 7:1 reserved reserved. 0 host_notify_sts the intel ? 6300ESB ich sets this bit to a ?1? when it has completely received a successful host notify command on the smlink pins. software reads this bit to determine that the source of the interrupt or smi# was the reception of the host notify command. software clears this bit after reading any information needed from the notify address and data registers by writing a ?1? to this bit. note that the intel ? 6300ESB ich will allow the notify address and data registers to be overwritten once this bit has been cleared. when this bit is 1, the intel ? 6300ESB ich will nack the first byte (host address) of any new ?host notify? commands on the smlink. writing a ?0? to this bit has no effect. r/wc table 455. offset 11h: slv_cmd?slave command register bits name description access 7:3 reserved reserved. 2smbalert_dis 0 = allows the generation of the interrupt or smi#. 1 = software sets this bit to block the generation of the interrupt or smi# due to the smbalert# source. this bit is logically inverted and anded with the smbalert_sts bit. the resulting signal is distributed to the smi# and/or interrupt generation logic. this bit does not affect the wake logic. r/w 1 host_notify_wken software sets this bit to ?1? to enable the reception of a host notify command as a wake event. when enabled, this event is ?or?ed in with the other smbus wake events and is reflected in the smb_wak_sts bit of the general purpose event 0 status register. r/w 0 host_notify_intren software sets this bit to ?1? to enable the generation of interrupt or smi# when host_notify_sts is 1. this enable does not affect the setting of the host_notify_sts bit. when the interrupt is generated, either pirq[b]# or smi# is generated, depending on the value of the smb_smi_en bit (d31, f3, off40h, b1). if the host_notify_sts bit is set when this bit is written to a 1, then the interrupt (or smi#) will be generated. the interrupt (or smi#) is logically generated by ?and?ing the sts and intren bits. r/w device: 31 function: 3 offset: 10h attribute: read/write clear default value: 00h size: 8-bit device: 31 function: 3 offset: 11h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 547 12?intel ? 6300ESB ich 12.2.17 offset 14h: notify_daddr?notify device address note: this register is in the resume well and is reset by rsmrst#. table 456. offset 14h: notify_daddr?notify device address bits name description access 7:1 device_address this field contains the 7-bit device address received during the host notify protocol of the smbus 2.0 specification. software should only consider this field valid when the host_notify_sts bit is set to ?1?. ro 0 reserved reserved. device: 31 function: 3 offset: 14h attribute: read-only default value: 00h size: 8-bit
intel ? 6300ESB ich?12 intel ? 6300ESB i/o controller hub ds november 2007 548 order number: 300641-004us 12.2.18 offset 16h: notify_dlow?notify data low byte register note: this register is in the resume well and is reset by rsmrst#. 12.2.19 offset 17h: notify_dhigh?notify data high byte register note: this register is in the resume well and is reset by rsmrst#. table 457. offset 16h: notify_dlow?notify data low byte register bits name description access 7:0 data_low_byte this field contains the first (low) byte of data received during the host notify protocol of the smbus 2.0 specification. software should only consider this field valid when the host_notify_sts bit is set to ?1?. ro table 458. offset 17h: notify_dhigh?notify data high byte register bits name description access 7:0 data_high_byte this field contains the second (high) byte of data received during the host notify protocol of the smbus 2.0 specification. software should only consider this field valid when the host_notify_sts bit is set to ?1?. ro device: 31 function: 3 offset: 16h attribute: read-only default value: 00h size: 8-bit device: 31 function: 3 offset: 17h attribute: read-only default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 549 13?intel ? 6300ESB ich ac?97 audio controller registers (d31:f5) 13 13.1 ac?97 audio pci configuration space (d31:f5) note: registers that are not shown should be treated as reserved. table 459. pci configuration map (audio?d31:f5) offset mnemonic register default access 00-01h vid vendor identification 8086h ro 02-03h did device identification 25a6h ro 04-05h pcicmd pci command 0000 r/w 06-07h pcists pci device status 0290h r/wc 08h rid revision identification see note 1 ro 09h pi programming interface 00 ro 0ah scc sub class code 01h ro 0bh bcc base class code 04h ro 0eh hedt header type 00h ro 10-13h nambar native audio mixer base address 00000000h r/w 14-17h nabmbar native audio bus mastering base address 00000000h r/w 18-1bh mmbar mixer base address (mem) 00000000h r/w 1c-1fh mbbar bus master base address (mem) 00000000h r/w 2c-2dh svid subsystem vendor id 0000h write- once 2e-2fh sid subsystem id 0000h write- once 34h cap_ptr capabilities pointer 50h ro 3ch intr_ln interrupt line 00h r/w 3dh intr_pn interrupt pin 02h ro 40h pcid programmable codec id 09h r/w 41h cfg configuration 00h r/w 50-51h pid pci power management id 0001h ro 52-53h pc pc - power management capabilities c9c2h ro 54-55h pcs power management control and status 0000h r/w notes: 1. refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register.
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 550 order number: 300641-004us note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the following bios programmed registers as bios may not be invoked following the d3-to-d0 transition. resume well registers will not be reset by the d3 hot to d0 transition.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 551 13?intel ? 6300ESB ich core well registers not reset by the d3 hot to d0 transition: ? offset 2ch-2dh ? subsystem vendor id (svid) ? offset 2eh-2fh ? subsystem id (sid) ? offset 40h ? programmable codec id (pcid) ? offset 41h ? configuration (cfg) resume well registers will not be reset by the d3 hot to d0 transition: ? offset 54h-55h ? power management control and status (pcs) ? bus mastering register: global status register, bit[17:16] ? bus mastering register: sdata_in map register, bit[7:3] 13.1.1 offset 00 - 01h: vid?vendor identification register (audio?d31:f5) 13.1.2 offset 02 - 03h: did?device identification register (audio?d31:f5) table 460. offset 00 - 01h: vid?vendor identification register (audio? d31:f5) bits name description access 15:0 vendor id value this is a 16-bit value assigned to intel. ro table 461. offset 02 - 03h: did?device identification register (audio? d31:f5) bits name description access 15:0 device id value ro device: 31 function: 5 offset: 00-01h attribute: read-only default value: 8086h size: 16-bit lockable: no power well: core device: 31 function: 5 offset: 02-03h attribute: read-only default value: 25a6h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 552 order number: 300641-004us 13.1.3 offset 04 - 05h: pcicmd?pci command register (audio?d31:f5) note: pcicmd is a 16-bit control register. refer to the pci 2.2 specification for complete details on each bit. 13.1.4 offset 06 - 07h: pcists?pci device status register (audio?d31:f5) note: pcists is a 16-bit status register. refer to the pci 2.2 specification for complete details on each bit. note: when a master abort occurs on a memory read request performed by a particular channel, the run bit for that channel gets cleared immediately, and the corresponding dma engine halts. write requests are posted and hence aborts cannot be seen by the intel ? 6300ESB ich ac?97 controller for write requests. table 462. offset 04 - 05h: pcicmd?pci command register (audio?d31:f5) bits name description access 15:1 0 reserved reserved. read ?0? . 9 fast back-to-back enable (fbe) not implemented. hardwired to ?0?. 8 serr# enable (sen) not implemented. hardwired to ?0?. 7 wait cycle control (wcc) not implemented. hardwired to ?0?. 6 parity error response (per) not implemented. hardwired to ?0?. 5 vga palette snoop (vps) not implemented. hardwired to ?0?. 4 memory write and invalidate enable (mwi) not implemented. hardwired to ?0?. 3 special cycle enable (sce) not implemented. hardwired to ?0?. 2 bus master enable (bme) controls standard pci bus mastering capabilities. 0 = disable. 1 = enable r/w 1 memory space enable (mse) enables memory space addresses to the ac?97 audio controller. r/w device: 31 function: 5 offset: 04-05h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 553 13?intel ? 6300ESB ich table 463. offset 06 - 07h: pcists?pci device status register (audio? d31:f5) bits name description access 15 detected parity error (dpe) not implemented. hardwired to ?0?. 14 serr# status (serrs) not implemented. hardwired to ?0?. 13 master-abort status (mas) 0 = software clears this bit by writing a ?1? to the bit position. 1 = bus master ac '97 2.2 interface function, as a master, generates a master abort. r/wc 12 reserved reserved. will always read as ?0?. 11 signaled target-abort status (sta) not implemented. hardwired to ?0?. 10:9 devsel# timing status (devt) this 2-bit field reflects the intel ? 6300ESB ich's devsel# timing when performing a positive decode. 01b = medium timing. hardwired to ?01?. ro 8 data parity detected (dpd) not implemented. hardwired to ?0?. 7 fast back to back capable (fbc) hardwired to ?1?. this bit indicates that the intel ? 6300ESB ich as a target is capable of fast back-to-back transactions. 6 reserved reserved. hardwired to ?0?. 5 66 mhz capable hardwired to ?0?. 4 capabilities list exists (clist) indicates that the controller contains a capabilities pointer list. the first item is pointed to by looking at configuration offset 34h. 3:0 reserved reserved. device: 31 function: 5 offset: 06-07h attribute: read/write clear default value: 0290h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 554 order number: 300641-004us 13.1.5 offset 08h: rid?revision identification register (audio?d31:f5) 13.1.6 offset 09h: pi?programming interface register (audio?d31:f5) 13.1.7 offset 0ah: scc?sub class code register (audio?d31:f5) table 464. offset 08h: rid?revision identification register (audio?d31:f5) bits name description access 7:0 revision id value refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. ro table 465. offset 09h: pi?programming interface register (audio?d31:f5) bits name description access 7:0 programming interface ro table 466. offset 0ah: scc?sub class code register (audio?d31:f5) bits name description access 7:0 sub class code 01h = audio device this indicates the device is an audio device, in the context of a multimedia device (base class code = 04h). ro device: 31 function: 5 offset: 08h attribute: read-only default value: see bit description size: 8-bit lockable: no power well: core device: 31 function: 5 offset: 09h attribute: read-only default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 5 offset: 0ah attribute: read-only default value: 01h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 555 13?intel ? 6300ESB ich 13.1.8 offset 0bh: bcc?base class code register (audio?d31:f5) 13.1.9 offset 0eh: hedt?header type register (audio? d31:f5) 13.1.10 offset 10 - 13h: nambar?native audio mixer base address register (audio?d31:f5) the native pci mode audio function uses pci base address register 1 to request a contiguous block of i/o space that is to be used for the native audio mixer software interface. the mixer requires 256 bytes of i/o space. this 256 bytes space is divided into 128 bytes for the primary codec (offsets 00-7fh) and 128 bytes for the secondary codec (offsets 80-ffh). access to these registers will be decoded by the ac?97 controller and forwarded over the ac-link to the codec. the codec will then respond with the register value. in the case of split codec implementation, accesses to the different codecs are differentiated by the controller by using address offsets 00h - 7fh for the primary codec and address offsets 80h - feh for the secondary codec. note: the tertiary codec cannot be addressed through this address space. the tertiary space is only available from the new mmbar register. this register powers up as read only and only becomes writeable when the iose bit in offset 41h is set. for descriptions of these i/o registers, refer to the ac?97 specification. table 467. offset 0bh: bcc?base class code register (audio?d31:f5) bits name description access 7:0 base class code 04h = multimedia device ro table 468. offset 0eh: hedt?header type register (audio?d31:f5) bits name description access 7:0 header type value hardwired to 00h. device: 31 function: 5 offset: 0bh attribute: read-only default value: 04h size: 8-bit lockable: no power well: core device: 31 function: 5 offset: 0eh attribute: read-only default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 556 order number: 300641-004us 13.1.11 offset 14 - 17h: nabmbar?native audio bus mastering base address register (audio?d31:f5) the native pci mode audio function uses pci base address register 1 to request a contiguous block of i/o space that is to be used for the native mode audio software interface. this bar creates 64 bytes of i/o space to signify the base address of the bus master i/o space. note: the dma registers for s/pdif and microphone in 2 cannot be addressed through this address space. these dma functions are only available from the new mbbar register. this register powers up as read only and only becomes writeable when the iose bit in offset 41h is set. table 469. offset 10 - 13h: nambar?native audio mixer base address register (audio?d31:f5) bits name description access 31:1 6 reserved reserved. all bits are hardwired to ?0?. 15:8 base address these bits are used in the i/o space decode of the native audio mixer interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for the ac?97 mixer, the upper 16 bits are hardwired to ?0?, while bits 15:8 are programmable. this configuration yields a maximum i/o block size of 256 bytes for this base address. r/w 7:1 reserved reserved. read as ?0?s. 0 resource type indicator (rte) this read-only bit defaults to ?0? and flips to ?1? if bit ?0? of offset 41h is set. when this bit is set to ?1?, it indicates a request for i/o space. ro device: 31 function: 5 offset: 10-13h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 557 13?intel ? 6300ESB ich 13.1.12 offset 18 - 1bh: mmbar?mixer base address register (audio?d31:f5) this bar creates 512 bytes of memory space to signify the base address of the register space. the lower 256 bytes of this space map to the same registers as the 256-byte i/ o space pointed to by nambar. the lower 384 bytes are divided as follows: ? 128 bytes for the primary codec (offsets 00 ? 7fh) ? 128 bytes for the secondary codec (offsets 80h ? ffh) ? 128 bytes for the tertiary codec (offsets 100h ? 17fh). ? 128 bytes of reserved space (offsets 180h ? 1ffh), returning all ?0?. table 470. offset 14 - 17h: nabmbar?native audio bus mastering base address register (audio?d31:f5) bits name description access 31:1 6 reserved reserved. hardwired to ?0?. 15:6 base address these bits are used in the i/o space decode of the native audio bus mastering interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for ac?97 bus mastering, the upper 16 bits are hardwired to ?0?, while bits 15:6 are programmable. this configuration yields a maximum i/o block size of 64 bytes for this base address. r/w 5:1 reserved reserved. read as ?0?s. 0 resource type indicator (rte) this read-only bit defaults to ?0? and flips to ?1? if bit ?0? of offset 41h is set. when this bit is set to ?1?, it indicates a request for i/o space. ro device: 31 function: 5 offset: 14-17h attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core table 471. offset 18 - 1bh: mmbar?mixer base address register (audio? d31:f5) (sheet 1 of 2) bits name description access 31:9 base address lower 32 bits of the 512-byte memory offset to use for decoding the primary, secondary, and tertiary codec?s mixer spaces. r/w device: 31 function: 5 offset: 18-1bh attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 558 order number: 300641-004us 13.1.13 offset 1c - 1fh: mbbar?bus master base address register (audio?d31:f5) note: this bar creates 256 bytes of memory space to signify the base address of the bus master memory space. the lower 64 bytes of the space pointed to by this register point to the same registers as the nabmbar. 8:3 reserved reserved. read as ?0?s. ro 2:1 type indicates the base address exists in 32-bit address space ro 0 resource type indicator (rte) this bit is set to ?0?, indicating a request for memory space. ro table 472. offset 1c - 1fh: mbbar?bus master base address register (audio?d31:f5) bits name description access 31:8 base address i/o offset to use for decoding the pcm in, pcm out, and microphone 1 dma engines. r/w 7:3 reserved reserved. read as ?0?s. ro 2:1 type indicates the base address exists in 32-bit address space. ro 0 resource type indicator (rte) this bit is set to ?0?, indicating a request for memory space. ro table 471. offset 18 - 1bh: mmbar?mixer base address register (audio? d31:f5) (sheet 2 of 2) bits name description access device: 31 function: 5 offset: 18-1bh attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core device: 31 function: 5 offset: 1c-1fh attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 559 13?intel ? 6300ESB ich 13.1.14 offset 2d - 2ch: svid?subsystem vendor id register (audio?d31:f5) the svid register, in combination with the subsystem id register, enable the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value may be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. 13.1.15 offset 2e - 2fh: sid?subsystem id register (audio?d31:f5) the sid register, in combination with the subsystem vendor id register make it possible for the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value may be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. table 473. offset 2d - 2ch: svid?subsystem vendor id register (audio? d31:f5) bits name description access 15:0 subsystem vendor id value r/wo device: 31 function: 5 offset: 2d-2ch attribute: read/write once default value: 0000h size: 16-bit lockable: no power well: core table 474. offset 2e - 2fh: sid?subsystem id register (audio?d31:f5) bits name description access 15:0 subsystem id value r/wo device: 31 function: 5 offset: 2e-2fh attribute: read/write once default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 560 order number: 300641-004us 13.1.16 offset 34h: cap_ptr?capabilities pointer (audio?d31:f5) note: this register indicates the offset for the capability pointer. 13.1.17 offset 3ch: intr_ln?interrupt line register (audio?d31:f5) note: this register indicates which pci interrupt line is used for the ac?97 module interrupt. the ac?97 interrupt is internally ored to the interrupt controller with the pirq[b]# signal. table 475. offset 34h: cap_ptr?capabilities pointer (audio?d31:f5) bits name description access 7:0 capability pointer (cp) indicates that the firs t capability pointer offset is offset 50h. ro table 476. offset 3ch: intr_ln?interrupt line register (audio?d31:f5) bits name description access 7:0 interrupt line this data is not used by the intel ? 6300ESB ich. it is used to communicate to software the in terrupt line that the interrupt pin is connected to. r/w device: 31 function: 5 offset: 34h attribute: read-only default value: 50h size: 8-bit lockable: no power well: core device: 31 function: 5 offset: 3ch attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 561 13?intel ? 6300ESB ich 13.1.18 offset 3dh: intr_pn?interrupt pin register (audio?d31:f5) note: this register indicates which pci interrupt pin is used for the ac?97 module interrupt. the ac?97 interrupt is internally or?d to the interrupt controller with the pirqb# signal. 13.1.19 offset 40h: pcid?programmable codec id register (audio?d31:f5) note: this register is used to specify the id for the secondary and tertiary codecs for i/o accesses. this register is not affected by the d3 hot to d0 transition. note: the value in this register must only be modified prior to any ac?97 codec accesses. table 477. offset 3dh: intr_pn?interrupt pin register (audio?d31:f5) bits name description access 7:3 reserved reserved. 2:0 ac'97 interrupt routing hardwired to 010b to select pirqb#. ro table 478. offset 40h: pcid?programmable codec id register (audio? d31:f5) bits name description access 7:4 reserved reserved. 3:2 tertiary codec id (tid) these bits define the encoded id that is used to address the tertiary codec i/o space. bit ?1? is the first bit sent and bit ?0? is the second bit sent on ac_sdata_out during slot 0. r/w 1:0 secondary codec id (scid) these two bits define the encoded id that is used to address the secondary codec i/o space. the two bits are the id that will be placed on slot 0, bits ?0? and ?1?, upon an i/o access to the secondary codec. bit ?1? is the first bit sent and bit ?0? is the second bit sent on ac_sdata_out during slot 0. r/w device: 31 function: 5 offset: 3dh attribute: read-only default value: 3dh size: 8-bit lockable: no power well: core device: 31 function: 5 offset: 40h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 562 order number: 300641-004us 13.1.20 offset 41h: cfg?configuration register (audio? d31:f5) note: this register is used to specify the id for the secondary and tertiary codecs for i/o accesses. this register is not affected by the d3 hot to d0 transition. 13.1.21 offset 50h: pid?pci power management capability id register (audio?d31:f5) table 479. offset 41h: cfg?configuration register (audio?d31:f5) bits name description access 7:1 reserved reserved. ro 0 i/o space enable (iose) when cleared, the iose bit at offset 04h and the i/o space bars at offset 10h and 14h become read-only registers. this is the default state for the i/o bars. bios must explicitly set this bit to allow a legacy driver to work. r/w table 480. offset 50h: pid?pci power management capability id register (audio?d31:f5) bits name description access 15:8 next capability (next) indicates that the next item in the list is at offset 00h. ro 7:0 cap id (cap) indicates that this pointer is a message signaled interrupt capability. ro device: 31 function: 5 offset: 41h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 5 offset: 50h attribute: read-only default value: 0001h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 563 13?intel ? 6300ESB ich 13.1.22 offset 52h: pc?power management capabilities register (audio?d31:f5) note: this register is not affected by the d3 hot to d0 transition. 13.1.23 offset 54h: pcs?power management control and status register (audio?d31:f5) table 481. offset 52h: pc?power management capabilities register (audio? d31:f5) bits name description access 15:1 1 pme_support indicates pme# may be generated from all d states. ro 10:9 reserved reserved. ro 8:6 aux_current reports 375ma maximum suspend well current required when in the d3 cold state. ro 5 device specific initial- ization (dsi) indicates that no device-specific initialization is required. ro 4 reserved reserved. ro 3 pme clock (pmec) indicates that pci clock is not required to generate pme#. ro 2:0 version (vs) indicates support for revision 1.1 of the pci power management specification. ro table 482. offset 54h: pcs?power management control and status register (audio?d31:f5) (sheet 1 of 2) bits name description access 15 pme status (pmes) this bit is set when the ac?97 controller would normally assert the pme# signal independent of the state of the pme_en bit. this bit resides in the resume well. r/wc 14:9 reserved reserved. ro device: 31 function: 5 offset: 52h attribute: read-only default value: c9c2h size: 16-bit lockable: no power well: core device: 31 function: 5 offset: 54h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: resume
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 564 order number: 300641-004us 13.2 ac?97 audio i/o space (d31:f5) the ac?97 i/o space includes native audio bus master registers and native mixer registers. for the intel ? 6300ESB ich, the offsets are important as they will determine bits[1:0] of the tag field (codec id). audio mixer i/o space may be accessed as a 16-bit field only since the data packet length on ac-link is a word. any s/w access to the codec will be done as a 16-bit access starting from the first active byte. in case no byte enables are active, the access will be done at the first word of the qword that contains the address of this request. 8 power management event enable (pmee) when set, and if corresponding pmes is also set, the ac'97 controller sets the ac97_sts bit in the gpe0_sts register. r/w 7:2 reserved reserved. ro 1:0 power state (ps) this field is used both to determine the current power state of the ac?97 controller and to set a new power state. the values are: 00 ? d0 state 01 ? not supported 10 ? not supported 11 ? d3 hot state when in the d3 hot state, the ac?97 controller?s configuration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. when software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally. however, the data is discarded and no state change occurs. r/w table 482. offset 54h: pcs?power management control and status register (audio?d31:f5) (sheet 2 of 2) bits name description access device: 31 function: 5 offset: 54h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: resume
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 565 13?intel ? 6300ESB ich table 483. intel ? 6300ESB i/o controller hub audio mixer register configuration (sheet 1 of 2) primary offset (codec id =00) secondary offset (codec id =01) tertiary offset (codec id =10) nambar exposed registers (d31:f5) 00h 80h 100h reset 02h 82h 102h master volume 04h 84h 104h aux out volume 06h 86h 106h mono volume 08h 88h 108h master tone (r and l) 0ah 8ah 10ah pc_beep volume 0ch 8ch 10ch phone volume 0eh 8eh 10eh mic volume 10h 90h 110h line in volume 12h 92h 112h cd volume 14h 94h 114h video volume 16h 96h 116h aux in volume 18h 98h 118h pcm out volume 1ah 9ah 11ah record select 1ch 9ch 11ch record gain 1eh 9eh 11eh record gain mic 20h a0h 120h general purpose 22h a2h 122h 3d control 24h a4h 124h ac?97 reserved 26h a6h 126h powerdown ctrl/stat 28h a8h 128h extended audio 2ah aah 12ah extended audio ctrl/stat 2ch ach 12ch pcm front dac rate 2eh aeh 12eh pcm surround dac rate 30h b0h 130h pcm lfe dac rate 32h b2h 132h pcm lr adc rate 34h b4h 134h mic adc rate 36h b6h 136h 6ch vol: c, lfe 38h b8h 138h 6ch vol: l, r surround 3ah bah 13ah s/pdif control 3c-56h bc-d6h 13c-156h intel reserved 58h d8h 158h ac?97 reserved notes: 1. software should not try to access reserved registers. 2. primary codec id cannot be changed. secondary codec id may be changed through bits 1:0 of configuration register 40h. tertiary codec id may be changed through bits 3:2 of configuration register 40h. 3. the tertiary offset is only available through the memory space defined by the mmbar register.
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 566 order number: 300641-004us the bus master registers are located from offset + 00h to offset + 51h and reside in the ac?97 controller. accesses to these registers do not cause the cycle to be forwarded over the ac-link to the codec. s/w could access these registers as bytes, word, or dword quantities, but reads must not cross dword boundaries. in the case of split codec implementation, accesses to the different codecs are differentiated by the controller by using address offsets 00h - 7fh for the primary codec, address offsets 80h - ffh for the secondary codec and address offsets 100h - 17fh for the tertiary codec. the global control (glob_cnt) and global status (glob_sta) registers are aliased to the same global registers in the audio and modem i/o space. therefore a read/write to these registers in either audio or modem i/o space affects the same physical register. bus mastering registers exist in i/o space and reside in the ac?97 controller. the six channels, pcm in, pcm in 2, pcm out, mic in, mic 2, and s/pdif out, each have their own set of bus mastering registers. the following register descriptions apply to all six channels. the register definition section titles use a generic ?x_? in front of the register to indicate that the register applies to all six channels. the naming prefix convention used in table 484 and in the register description i/o address is as follows: pi = pcm in channel po = pcm out channel mc = mic in channel. mc2 = mic 2 channel pi2 = pcm in 2 channel sp = s/pdif out channel. 5ah dah 15ah vendor reserved 7ch fch 17ch vendor id1 7eh feh 17eh vendor id2 table 483. intel ? 6300ESB i/o controller hub audio mixer register configuration (sheet 2 of 2) primary offset (codec id =00) secondary offset (codec id =01) tertiary offset (codec id =10) nambar exposed registers (d31:f5) notes: 1. software should not try to access reserved registers. 2. primary codec id cannot be changed. secondary codec id may be changed through bits 1:0 of configuration register 40h. tertiary codec id may be changed through bits 3:2 of configuration register 40h. 3. the tertiary offset is only available through the memory space defined by the mmbar register. table 484. native audio bus master control registers (sheet 1 of 3) offset mnemonic name default access 00h pi_bdbar pcm in buffer descriptor list base address register 00000000h r/w 04h pi_civ pcm in current index value 00h ro 05h pi_lvi pcm in last valid index 00h r/w 06h pi_sr pcm in status register 0003h r/w 08h pi_picb pcm in position in current buffer 0000h ro 0ah pi_piv pcm in prefetched index value 00h ro 0bh pi_cr pcm in control register 00h r/w
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 567 13?intel ? 6300ESB ich 10h po_bdbar pcm out buffer descriptor list base address register 00000000h r/w 14h po_civ pcm out current index value 00h ro 15h po_lvi pcm out last valid index 00h r/w 16h po_sr pcm out status register 0001h r/w 18h po_picb pcm out position in current buffer 0000h ro 1ah po_piv pcm out prefetched index value 00h ro 1bh po_cr pcm out control register 00h r/w 20h mc_bdbar mic. in buffer descriptor list base address register 00000000h r/w 24h mc_civ mic. in current index value 00h ro 25h mc_lvi mic. in last valid index 00h r/w 26h mc_sr mic. in status register 0001h r/w 28h mc_picb mic. in position in current buffer 0000h ro 2ah mc_piv mic. in prefetched index value 00h ro 2bh mc_cr mic. in control register 00h r/w 2ch glob_cnt global control 00000000h r/w 30h glob_sta global status 00700000h ro 34h acc_sema codec write semaphore register 00h r/w 40-43h mc2_bdbar mic. 2 buffer descriptor list base address register 00h ro 44h mc2_civ mic. 2 current index value 00h r/w 45h mc2_lvi mic. 2 last valid index 0001h r/w 46-47h mc2_sr mic. 2 status register 0000h ro 48-49h mc2_picb mic. 2 position in current buffer 00h ro 4ah mc2_piv mic. 2 prefetched index value 00h r/w 4bh mc2_cr mic. 2 control register 00h ro 50-53h pi2_bdbar pcm in 2 buffer descriptor list base address register 00000000h r/w 54h pi2_civ pcm in 2 current index value 00h ro 55h pi2_lvi pcm in 2 last valid index 00h r/w 56-57h pi2_sr pcm in 2 status register 0001h r/w 58-59h pi2_picb pcm in 2 position in current buffer 0000h ro 5ah pi2_piv pcm in 2 prefetched index value 00h ro 5bh pi2_cr pcm in 2 control register 00h r/w 60-63 sp_bar s/pdif buffer descriptor list base address register 00000000h r/w 64h sp_civ s/pdif current index value 00h ro 65h sp_lvi s/pdif last valid index 00h r/w 66-67h sp_sr s/pdif status register 0001h r/w table 484. native audio bus master control registers (sheet 2 of 3) offset mnemonic name default access
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 568 order number: 300641-004us note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the registers shared with the ac?97 modem (gcr, gsr, casr). resume well registers will not be reset by the d3 hot to d0 transition. core well registers and bits not reset by the d3 hot to d0 transition: ? offset 2ch-2fh ? bits[15,6:0] global control (glob_cnt) ? offset 30h-33h ? bits[29,15,11:10,0] global status (glob_sta) ? offset 34h ? codec access semaphore register (cas) resume well registers and bits will not be reset by the d3 hot to d0 transition: ? offset 30h-33h ? bits[17:16] global status (glob_sta) 13.2.1 x _bdbar?buffer descriptor base address register note: software may read the register at offset 00h by performing a single 32-bit read from address offset 00h. reads across dword boundaries are not supported. 13.2.2 x _civ?current index value register note: software may read the registers at offsets 04h, 05h and 06h simultaneously by performing a single 32-bit read from address offset 04h. software may also read this register individually by doing a single 8-bit read to offset 04h. reads across dword boundaries are not supported. 68-69h sp_picb s/pdif position in current buffer 0000h ro 6ah sp_piv s/pdif prefetched index value 00h ro 6bh sp_cr s/pdif control register 00h r/w 80h sdm sdata_in map 00h r/w table 484. native audio bus master control registers (sheet 3 of 3) offset mnemonic name default access table 485. x_bdbar?buffer descriptor base address register bits name description access 31:3 buffer descriptor base address[31:3] these bits represent address bits 31:3. the data should be aligned on 8 byte boundaries. each buffer descriptor is 8 bytes long, and the list may contain a maximum of 32 entries. r/w 2:0 hardwired to ?0?. device: 31 function: 5 i/o address: nabmbar + 00h (pibdbar), nabmbar + 10h (pobdbar), nabmbar + 20h (mcbdbar), mbbar + 40h (mc2bdbar), mbbar + 50h (pi2bdbar), mbbar + 60h (spbar) attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 569 13?intel ? 6300ESB ich 13.2.3 x _lvi?last valid index register 13.2.4 x _sr?status register note: software may read the registers at offsets 04h, 05h and 06h simultaneously by performing a single 32-bit read from address offset 04h. software may also read this register individually by doing a single 8-bit read to offset 05h. reads across dword boundaries are not supported. table 486. x_civ?current index value register bits name description access 7:5 hardwired to ?0?. 4:0 current index value[4:0] these bits represent which buffer descriptor within the list of 32 descriptors is currently being processed. as each descriptor is processed, this value is incremented. the value rolls over after it reaches 31. ro table 487. x_lvi?last valid index register bits name description access 7:5 hardwired to ?0?. 4:0 last valid index[4:0] this value represents the last valid descriptor in the list. this value is updated by the software each time it prepares a new buffer and adds it to the list. r/w device: 31 function: 5 i/o address: nabmbar + 04h (piciv), nabmbar + 04h (piciv), nabmbar + 04h (piciv), mbbar + 44h (mc2civ), mbbar + 54h (pi2civ), mbbar + 64h (spciv) attribute: read-only default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 5 i/o address: nabmbar + 05h (pilvi), nabmbar + 15h (polvi), nabmbar + 15h (polvi), nabmbar + 15h (polvi), mbbar + 55h (pi2lvi), mbbar + 65h (splvi) attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 570 order number: 300641-004us table 488. x_sr?status register bits name description access 15:5 reserved reserved. ro 4 fifo error (fifoe) 0 = cleared by writing a ?1? to this bit position. 1 = fifo error occurs. pisr register: fifo error indicates a fifo overrun. the fifo pointers don't increment; the incoming data is not written into the fifo, thus is lost. posr register: fifo error indicates a fifo underrun. the sample transmitted in this case should be the last valid sample. the intel ? 6300ESB ich will set the fifoe bit if the underrun or overrun occurs when there are more valid buffers to process. r/wc 3 buffer completion interrupt status (bcis) 0 = cleared by writing a ?1? to this bit position. 1 = set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion (ioc) bit is set in the command byte of the buffer descriptor. it remains active until cleared by software. r/wc 2 last valid buffer completion interrupt (lvbci) 0 = cleared by writing a ?1? to this bit position. 1 = last valid buffer has been processed. it remains active until cleared by software. this bit indicates the occurrence of the event signified by the last valid buffer being processed. thus, this is an event status bit that may be cleared by software once this event has been recognized. this event will cause an interrupt when the enable bit in the control register is set. the interrupt is cleared when the software clears this bit. in the case of transmits (pcm out, modem out) this bit is set after the last valid buffer has been fetched, not after transmitting it. in the case of receives , this bit is set after the data for the last buffer has been written to memory. r/wc 1 current equals last valid (celv) 0 = cleared by hardware when controller exits state (i.e., until a new value is written to the lvi register.) 1 = current index is equal to the value in the last valid index register, and the buffer pointed to by the civ has been processed (i.e., after the last valid buffer has been processed). this bit is very similar to bit 2, except this bit reflects the state rather than the event. this bit reflects the state of the controller and remains set until the controller exits this state. ro 0 dma controller halted (dch) 0 = running. 1 = halted. this could happen because of the start/stop bit being cleared and the dma engines are idle, or it could happen once the controller has processed the last valid buffer. ro device: 31 function: 5 i/o address: nabmbar + 06h (pisr), nabmbar + 16h (posr), nabmbar + 26h (mcsr), mbbar + 46h (mc2sr), mbbar + 56h (pi2sr), mbbar + 66h (spsr) attribute: read/write clear, read-only default value: 0001h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 571 13?intel ? 6300ESB ich 13.2.5 x _picb?position in current buffer register 13.2.6 x _piv?prefetched index value register note: software may read the registers at offsets 08h, 0ah, and 0bh by performing a 32-bit read from address offset 08h. software may also read this register individually by doing a single 8-bit read to offset 0ah. reads across dword boundaries are not supported. table 489. x_picb?position in current buffer register bits name description access 15:0 position in current buffer[15:0] these bits represent the number of samples left to be processed in the current buffer. this means the number of samples not yet read from memory (in the case of reads from memory) or not yet written to memory (in the case of writes to memory) irrespective of the number of samples that have been transmitted/received across ac-link. ro table 490. x_piv?prefetched index value register bits name description access 7:5 hardwired to 0. 4:0 prefetched index value[4:0] these bits represent which buffer descriptor in the list has been prefetched. the bits in this register are also modulo 32 and roll over after they reach 31. ro device: 31 function: 5 i/o address: nabmbar + 08h (pipicb), nabmbar + 18h (popicb), nabmbar + 28h (mcpicb), mbbar + 48h (mc2picb), mbbar + 58h (pi2picb), mbbar + 68h (sppicb) attribute: read-only default value: 0000h size: 16-bit lockable: no power well: core device: 31 function: 5 i/o address: nabmbar + 0ah (pipiv), nabmbar + 1ah (popiv), nabmbar + 2ah (mcpiv), mbbar + 4ah (mc2piv), mbbar + 5ah (pi2piv), mbbar + 6ah (sppiv) attribute: read-only default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 572 order number: 300641-004us 13.2.7 x _cr?control register note: software may read the registers at offsets 08h, 0ah, and 0bh by performing a 32-bit read from address offset 08h. software may also read this register individually by doing a single 8-bit read to offset 0bh. reads across dword boundaries are not supported. 13.2.8 glob_cnt?global control register note: reads across dword boundaries are not supported. table 491. x_cr?control register bits name description access 7:5 reserved reserved. 4 interrupt on completion enable (ioce) this bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. 0 = disable. interrupt will not occur. 1 = enable. r/w 3 fifo error interrupt enable (feie) this bit controls whether the occurrence of a fifo error will cause an interrupt or not. 0 = disable. bit 4 in the status register will be set, but the interrupt will not occur. 1 = enable. interrupt will occur. r/w 2 last valid buffer interrupt enable (lvbie) this bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = disable. bit 2 in the status register will still be set, but the interrupt will not occur. 1 = enable. r/w 1 reset registers (rr) 0 = removes reset condition. 1 = contents of all bus master related registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). software needs to set this bit but need not clear it since the bit is self clearing. this bit must be set only when the run/pause bit is cleared. setting it when the run bit is set will cause undefined consequences. r/w (special) 0 run/pause bus master (rpbm) 0 = pause bus master operation. this results in all state information being retained (i.e., master mode operation may be stopped and then resumed). 1 = run. bus master operation starts. r/w device: 31 function: 5 i/o address: nabmbar + 0bh (picr), nabmbar + 1bh (pocr), nabmbar + 2bh (mccr), mbbar + 4bh (mc2cr), mbbar + 5bh (pi2cr), mbbar + 6bh (spcr) attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 573 13?intel ? 6300ESB ich table 492. glob_cnt?global control register (sheet 1 of 2) bits name description access 31:3 0 s/pdif slot map (ssm) when the run/pause bus master bit (bit ?0? of offset 2bh) is set, the value in these bits indicates which slots s/pdif data is transmitted on. software must ensure that the programming here does not conflict with the pcm channels being used. when there is a conflict, unpredictable behavior will result; the hardware will not check for a conflict. 00 - reserved 01 - slots 7 and 8 10 - slots 6 and 9 11 - slots 10 and 11 r/w 29:2 4 reserved reserved. 23:2 2 pcm out mode (pom) enables the pcm out channel to use 16 or 20-bit audio on pcm out. this does not affect the microphone of s/pdif dma. when greater than 16-bit audio is used, the data structures are aligned as 32 bits per sample, with the highest order bits representing the data and the lower order bits as ?do not care?. 00 = 16 bit audio (default) 01 = 20 bit audio 10 = reserved. when set, indeterminate behavior will result. 11 = reserved. when set, indeterminate behavior will result. r/w 21:2 0 pcm 4/6 enable configures pcm output for 2, 4 or 6 channel mode. 00 = 2-channel mode (default) 01 = 4-channel mode 10 = 6-channel mode 11 = reserved r/w 19:7 reserved reserved. 6 ac_sdin2 interrupt enable (s2re) 0 = disable. 1 = enable an interrupt to occur when the codec on ac_sdin[2] causes a resume event on the ac-link. r/w 5 ac_sdin1 resume interrupt enable (s1re) 0 = disable. 1 = enable an interrupt to occur when the codec on ac_sdin[1] causes a resume event on the ac-link. r/w 4 ac_sdin0 resume interrupt enable (s0re) 0 = disable. 1 = enable an interrupt to occur when the codec on ac_sdin[0] causes a resume event on the ac-link. r/w 3 aclink shut off (lso) 0 = normal operation. 1 = controller disables all outputs which will be pulled low by internal pull down resistors. r/w device: 31 function: 5 i/o address: nabmbar + 2ch attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 574 order number: 300641-004us 13.2.9 glob_sta?global status register note: reads across dword boundaries are not supported. 2ac?97 warm reset 0 = normal operation. 1 = writing a ?1? to this bit causes a warm reset to occur on the ac-link. the warm reset will awaken a suspended codec without clearing its internal registers. when software attempts to perform a warm reset while bit_clk is running, the write will be ignored and the bit will not change. this bit is self-clearing; it remains set until the reset completes and bit_clk is seen on the aclink, after which it clears itself. r/w (special) 1 ac?97 cold reset# 0 = writing a ?0? to this bit causes a cold reset to occur throughout the ac?97 circuitry. all data in the controller and the codec will be lost. software must clear this bit no sooner than the minimum number of ms have elapsed. 1 = this bit defaults to ?0? and hence, after reset, the driver needs to set this bit to a ?1?. the value of this bit is retained after suspends; hence, when this bit is set to a ?1? prior to suspending, a cold reset is not generated automatically upon resuming. note: this bit is in the core well. r/w 0 gpi interrupt enable (gie) this bit controls whether the change in status of any gpi causes an interrupt. 0 = bit ?0? of the global status register is set, but no interrupt is generated. 1 = the change on value of a gpi causes an interrupt and sets bit ?0? of the global status register. r/w table 492. glob_cnt?global control register (sheet 2 of 2) bits name description access device: 31 function: 5 i/o address: nabmbar + 2ch attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 575 13?intel ? 6300ESB ich table 493. glob_sta?global status register (sheet 1 of 3) bits name description access 31:3 0 reserved reserved. 29 ac_sdin2 resume interrupt (s2ri) this bit indicates that a resume event occurred on ac_sdin[2]. 0 = cleared by writing a ?1? to this bit position. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. r/wc 28 ac_sdin2 codec ready (s2cr) reflects the state of the codec ready bit in ac_sdin[2]. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. ro 27 bit clock stopped (bcs) indicates that the bit clock is not running. this bit is set when the intel ? 6300ESB ich detects that there has been no transition on bit_clk for four consecutive pci clocks. it is cleared when a transition is found on bit_clk. ro 26 s/pdif interrupt (spint) indicates that the s/pdif out channel interrupt status bits have been set. when the specific status bit is cleared, this bit will be cleared. ro 25 pcm in 2 interrupt (p2int) indicates that one of the pcm in 2 channel status bits have been set. when the specific status bit is cleared, this bit will be cleared. ro 24 microphone 2 in interrupt (m2int) indicates that one of the mic in channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 23:2 2 sample capabilities indicates the capability to support greater than 16-bit audio. 00 = reserved 01 = 16 and 20-bit audio supported (intel ? 6300ESB ich value) 10 = reserved 11 = reserved ro 21:2 0 multichannel capabilities indicates the capability to support more 4 and 6 channels on pcm out. ro 19:1 8 reserved reserved. 17 md3 power down semaphore for modem. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the ad3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. r/w device: 31 function: 5 i/o address: nabmbar + 30h attribute: read-only, read/write, read/write clear default value: 00700000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 576 order number: 300641-004us 16 ad3 power down semaphore for audio. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the md3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. r/w 15 read completion status (rcs) this bit indicates the status of codec read completions. 0 = a codec read completes normally. 1 = a codec read results in a time-out. the bit remains set until being cleared by software writing a ?1? to the bit location. this bit is not affected by d3 hot to d0 reset. r/wc 14 bit 3 of slot 12 display bit 3 of the most recent slot 12. ro 13 bit 2 of slot 12 display bit 2 of the most recent slot 12. ro 12 bit 1 of slot 12 display bit 1 of the most recent slot 12. ro 11 ac_sdin1 resume interrupt (s1ri) this bit indicates that a resume event occurred on ac_sdin[1]. 0 = cleared by writing a ?1? to this bit position. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. r/wc 10 ac_sdin0 resume interrupt (s0ri) this bit indicates that a resume event occurred on ac_sdin[0]. 0 = cleared by writing a ?1? to this bit position. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. r/wc 9 ac_sdin1 codec ready (s1cr) reflects the state of the codec ready bit in ac_sdin[1]. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. ro 8 ac_sdin0 codec ready (s0cr) reflects the state of the codec ready bit in ac_sdin [0]. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. ro 7 mic in interrupt (mint) this bit indicates that one of the mic in channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro table 493. glob_sta?global status register (sheet 2 of 3) bits name description access device: 31 function: 5 i/o address: nabmbar + 30h attribute: read-only, read/write, read/write clear default value: 00700000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 577 13?intel ? 6300ESB ich 6 pcm out interrupt (point) this bit indicates that one of the pcm out channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 5 pcm in interrupt (piint) this bit indicates that one of the pcm in channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 4:3 reserved reserved. 2 modem out interrupt (moint) this bit indicates that one of the modem out channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 1 modem in interrupt (miint) this bit indicates that one of the modem interrupt status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 0 gpi status change interrupt (gsci) this bit reflects the state of bit ?0? in slot 12 and is set whenever bit ?0? of slot 12 is set. this indicates that one of the gpis changed state and that the new values are available in slot 12. the bit is cleared by software writing a ?1? to this bit location. this bit is not affected by d3 hot to d0 reset. r/wc table 493. glob_sta?global status register (sheet 3 of 3) bits name description access device: 31 function: 5 i/o address: nabmbar + 30h attribute: read-only, read/write, read/write clear default value: 00700000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 578 order number: 300641-004us 13.2.10 cas?codec access semaphore register note: reads across dword boundaries are not supported. 13.2.11 sdm?sdata_in map register note: reads across dword boundaries are not supported. table 494. cas?codec access semaphore register bits name description access 7:1 reserved reserved. 0 codec access semaphore (cas) this bit is read by software to check whether a codec access is currently in progress. 0 = no access in progress. 1 = the act of reading this register sets this bit to 1. the driver that read this bit may then perform an i/o access. once the access is completed, hardware automatically clears this bit. r/w (special) table 495. sdm?sdata_in map register (sheet 1 of 2) bits name description access 7:6 pcm in 2, microphone in 2 data in line (di2l) when the se bit is set, these bits indicates which ac_sdin line should be used by the hardware for decoding the input slots for pcm in 2 and microphone in 2. when the se bit is cleared, the value of these bits is irrelevant, and pcm in 2 and mic in 2 dma engines are not available. 00 ac_sdin0 01 ac_sdin1 10 ac_sdin2 11 reserved r/w 5:4 pcm in 1, microphone in 1 data in line (di1l) when the se bit is set, these bits indicates which ac_sdin line should be used by the hardware for decoding the input slots for pcm in 1 and microphone in 1. when the se bit is cleared, the value of these bits is irrelevant, and the pcm in 1 and mic in 1 engines use the or?d ac_sdin lines. 00 ac_sdin0 01 ac_sdin1 10 ac_sdin2 11 reserved r/w device: 31 function: 5 offset: nabmbar + 34h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 5 offset: nabmbar + 80h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 579 13?intel ? 6300ESB ich 3 steer enable (se) when set, the ac_sdin lines are treated separately and not or?d together before being sent to the dma engines. when cleared, the ac_sdin lines are or?d together, and the microphone in 2 and pcm in 2 dma engines are not available. r/w 2 reserved reserved. ro 1:0 last codec read data input (ldi) when a codec register is read, this indicates which ac_sdin the read data returned on. software may use this to determine how the codecs are mapped. the values are: 00 ac_sdin0 01 ac_sdin1 10 ac_sdin2 11 reserved ro table 495. sdm?sdata_in map register (sheet 2 of 2) bits name description access device: 31 function: 5 offset: nabmbar + 80h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?13 intel ? 6300ESB i/o controller hub ds november 2007 580 order number: 300641-004us
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 581 14?intel ? 6300ESB ich ac?97 modem controller registers (d31:f6) 14 14.1 ac?97 modem pci configuration space (d31:f6) note: registers that are not shown should be treated as reserved. note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the following bios programmed registers as bios may not be invoked following the d3-to-d0 transition. resume well registers will not be reset by the d3 hot to d0 transition. core well registers not reset by the d3 hot to d0 transition: ? offset 2ch-2dh ? subsystem vendor id (svid) ? offset 2eh-2fh ? subsystem id (sid) table 496. pci configuration map (modem?d31:f6) offset mnemonic register default access 00-01h vid vendor identification 8086h ro 02-03h did device identification 25a7h ro 04-05h pcicmd pci command 0000h r/w 06-07h pcista pci device status 0290h r/wc 08h rid revision identification see note 1 ro 09h pi programming interface 00h ro 0ah scc sub class code 03h ro 0bh bcc base class code 07h ro 0eh hedt header type 00h ro 10-13h mmbar modem mixer base address 00000001 h r/w 14-17h mbar modem base address 00000001 h r/w 2c-2dh svid subsystem vendor id 0000h write-once 2e-2fh sid subsystem id 0000h write-once 34h cap_ptr capabilities pointer 50h ro 3ch intr_ln interrupt line 00h ro 3dh int_pn interrupt pin 02h ro 50-51h pid pci power management id 0001h ro 52-53h pc pc - power management capabilities c9c2h ro 54-55h pcs power management control and status 0000h r/w notes: 1. refer to the intel ? 6300ESB i/o controller hub specification update f or the most up-to-date value of the revision id register.
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 582 order number: 300641-004us resume well registers will not be reset by the d3 hot to d0 transition: ? offset 54h-55h ? power management control and status (pcs) 14.1.1 offset 00 - 01h: vid?vendor identification register (modem?d31:f6) 14.1.2 offset 02 - 03h: did?device identification register (modem?d31:f6) table 497. offset 00 - 01h: vid?vendor identification register (modem? d31:f6) bits name description access 15:0 vendor id value 16-bit field indicating the company vendor as intel ro table 498. offset 02 - 03h: did?device identification register (modem?d31:f6) bits name description access 15:0 device id value indicates the device number assigned by the sig ro device: 31 function: 6 offset: 01 - 01h attribute: read-only default value: 8086 size: 16-bit lockable: no power well: core device: 31 function: 6 offset: 02 - 03h attribute: read-only default value: 25a7h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 583 14?intel ? 6300ESB ich 14.1.3 offset 04 - 05h: pcicmd?pci command register (modem?d31:f6) note: pcicmd is a 16-bit control register. refer to the pci 2.2 specification for complete details on each bit.pcista?device status register (modem?d31:f6). table 499. offset 04 - 05h: pcicmd?pci command register (modem?d31:f6) bits name description access 15:1 0 reserved reserved. read 0. 9 fast back-to-back enable (fbe) not implemented. hardwired to ?0?. 8 serr# enable (sen) not implemented. hardwired to ?0?. 7 wait cycle control (wcc) not implemented. hardwired to ?0?. 6 parity error response (per) not implemented. hardwired to ?0?. 5 vga palette snoop (vps) not implemented. hardwired to ?0?. 4 memory write and invalidate enable (mwi) not implemented. hardwired to ?0?. 3 special cycle enable (sce) not implemented. hardwired to ?0?. 2 bus master enable (bme) controls standard pci bus mastering capabilities. 0 = disable 1 = enable r/w 1 memory space (ms) hardwired to ?0?; ac ?97 does not respond to memory accesses. 0 i/o space (ios) this bit controls access to the i/o space registers. 0 = disable access (default = 0). 1 = enable access to i/o space. the native pci mode base address register should be programmed prior to setting this bit. r/w device: 31 function: 6 offset: 04 - 05h attribute: read-only default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 584 order number: 300641-004us 14.1.4 offset 06 - 07h: pcista?device status register (modem?d31:f6) note: pcista is a 16-bit status register. refer to the pci 2.2 specification for complete details on each bit. table 500. offset 06 - 07h: pcista?device status register (modem?d31:f6) bits name description access 15 dpe (detected parity error) not implemented. hardwired to ?0?. ro 14 serrs (serr# status) not implemented. hardwired to ?0?. ro 13 mas (master-abort status) 0 = software clears this bit by writing a ?1? to the bit position. 1 = bus master ac ?97 interface function, as a master, generates a master abort. r/wc 12 reserved reserved. read as ?0?. ro 11 sta (signaled target- abort status) not implemented. hardwired to ?0?. ro 10:9 devt (devsel# timing status) this 2-bit field reflects the intel ? 6300ESB ich's devsel# timing parameter. these read-only bits indicate the intel ? 6300ESB ich's devsel# timing when performing a positive decode. ro 8 dpd (data parity detected) not implemented. hardwired to ?0?. ro 7 fbc (fast back to back capable) hardwired to ?1?. this bit indicates that the intel ? 6300ESB ich as a target is capable of fast back-to-back transactions. ro 6 udf supported not implemented. hardwired to ?0?. ro 5 66 mhz capable hardwired to ?0?. ro 4 capabilities list exists (clist) indicates that the controller contains a capabilities pointer list. the first item is pointed to by looking at configuration offset 34h. ro 3:0 reserved reserved. device: 31 function: 6 offset: 06 - 07h attribute: read/write clear default value: 0290h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 585 14?intel ? 6300ESB ich 14.1.5 offset 08h: rid?revision identification register (modem?d31:f6) 14.1.6 offset 09h: pi?programming interface register (modem?d31:f6) 14.1.7 offset 0ah: scc?sub class code register (modem?d31:f6) table 501. offset 08h: rid?revision identification register (modem?d31:f6) bits name description access 7:0 revision id value refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. ro table 502. offset 09h: pi?programming interface register (modem?d31:f6) bits name description access 7:0 programming interface value ro table 503. offset 0ah: scc?sub class code register (modem?d31:f6) bits name description access 7:0 sub class code value 03h = generic modem. ro device: 31 function: 6 offset: 08h attribute: read-only default value: see bit description size: 8-bit lockable: no power well: core device: 31 function: 6 offset: 09h attribute: read-only default value: 00h size: 8-bit lockable: no power well: core device: 31 function: 6 offset: 0ah attribute: read-only default value: 03h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 586 order number: 300641-004us 14.1.8 offset 0bh: bcc?base class code register (modem?d31:f6) 14.1.9 offset 0eh: hedt?header type register (modem?d31:f6) 14.1.10 offset 10 - 13h: mmbar?modem mixer base address register (modem?d31:f6) note: the native pci mode modem uses pci base address register 1 to request a contiguous block of i/o space that is to be used for the modem mixer software interface. the mixer requires 256 bytes of i/o space. all accesses to the mixer registers are forwarded over the ac- link to the codec where the registers reside. in the case of split codec implementation, accesses to the different codecs are differentiated by the controller by using address offsets 00h - 7fh for the primary codec and address offsets 80h - feh for the secondary codec. table 504. offset 0bh: bcc?base class code register (modem?d31:f6) bits name description access 7:0 base class code value 07h = simple communications controller. ro table 505. offset 0eh: hedt?header type register (modem?d31:f6) bits name description access 7:0 header value ro device: 31 function: 6 offset: 0bh attribute: read-only default value: 07h size: 8-bit lockable: no power well: core device: 31 function: 6 offset: 0eh attribute: read-only default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 587 14?intel ? 6300ESB ich 14.1.11 offset 14 - 17h: mbar?modem base address register (modem?d31:f6) note: the modem function uses pci base address register 1 to request a contiguous block of i/o space that is to be used for the modem software interface. the modem bus mastering register space requires 128 bytes of i/o space. all modem registers reside in the controller; therefore cycles are not forwarded over the ac-link to the codec. table 506. offset 10 - 13h: mmbar?modem mixer base address register (modem?d31:f6) bits name description access 31:1 6 reserved hardwired to ?0?. 15:8 base address these bits are used in the i/o space decode of the modem interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for the ac ?97 modem, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. this configuration yields a maximum i/o block size of 256 bytes for this base address. r/w 7:1 reserved read as 0. 0 resource type indicator (rte) this bit is set to one, indicating a request for i/o space. ro table 507. offset 14 - 17h: mbar?modem base address register (modem? d31:f6) bits name description access 31:1 6 reserved hardwired to ?0?. 15:7 base address these bits are used in the i/o space decode of the modem interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for the ac ?97 modem, the upper 16 bits are hardwired to ?0?, while bits 15:7 are programmable. this configuration yields a maximum i/o block size of 128 bytes for this base address. r/w 6:1 reserved reserved. read as ?0?. 0 resource type indicator (rte) this bit is set to ?1?, indicating a request for i/o space. ro device: 31 function: 6 offset: 10 - 13h attribute: read/write default value: 00000001h size: 32-bit lockable: no power well: core device: 31 function: 6 offset: 14 - 17h attribute: read/write default value: 00000001h size: 32-bit
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 588 order number: 300641-004us 14.1.12 offset 2c - 2dh: svid?subsystem vendor id (modem?d31:f6) note: this register should be implemented for any function that could be instantiated more than once in a given system. for example, a system with two audio subsystems, one on the motherboard and the other plugged into a pci expansion slot, should have the svid register implemented. the svid register, in combination with the subsystem id register, enable the operating environment to distinguish one audio subsystem from the other(s). note: software (bios) will write the value to this register. after that, the value may be read, but writes to the register will have no effect. the write to this register should be combined with the write to the sid to create one 32-bit write. this register is not affected by d3hot to d0 reset. 14.1.13 offset 2e - 2fh: sid?subsystem id (modem? d31:f6) note: this register should be implemented for any function that could be instantiated more than once in a given system; for example, a system with two audio subsystems, one on the motherboard and the other plugged into a pci expansion slot. the sid register, in combination with the subsystem vendor id register, make it possible for the operating environment to distinguish one audio subsystem from the other(s). note: software (bios) will write the value to this register. after that, the value may be read, but writes to the register will have no effect. the write to this register should be combined with the write to the svid to create one 32-bit write. this register is not affected by d3hot to d0 reset. table 508. offset 2c - 2dh: svid?subsystem vendor id (modem?d31:f6) bits name description access 31:1 6 reserved hardwired to ?0?s. 15:7 base address these bits are used in the i/o space decode of the modem interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for the ac ?97 modem, the upper 16 bits are hardwired to ?0?, while bits 15:7 are programmable. this configuration yields a maximum i/o block size of 128 bytes for this base address. r/w 6:1 reserved reserved. read as ?0?. ro 0 resource type indicator (rte) this bit is set to ?1?, indicating a request for i/o space. ro device: 31 function: 6 offset: 2c - 2dh attribute: write-once default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 589 14?intel ? 6300ESB ich 14.1.14 offset 34h: cap_ptr?capabilities pointer (modem?d31:f6) note: this register indicates the offset for the capability pointer. 14.1.15 offset 3ch: intr_ln?interrupt line register (modem?d31:f6) note: this register indicates which pci interrupt line is used for the ac?97 module interrupt. table 509. offset 2e - 2fh: sid?subsystem id (modem?d31:f6) bits name description access 15:0 subsystem id value r/wo table 510. offset 34h: cap_ptr?capabilities pointer (modem?d31:f6) bits name description access 7:0 capability pointer (cp) indicates that the first capability pointer offset is offset 50h. ro table 511. offset 3ch: intr_ln?interrupt line register (modem?d31:f6) bits name description access 7:0 interrupt line this data is not used by the intel ? 6300ESB ich. it is used to communicate to software the interrupt line that the interrupt pin is connected to. r/w device: 31 function: 6 offset: 2e-2fh attribute: write-once default value: 0000h size: 16-bit lockable: no power well: core device: 31 function: 6 offset: 34h attribute: read-only default value: 50h size: 8-bit lockable: no power well: core device: 31 function: 6 offset: 3ch attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 590 order number: 300641-004us 14.1.16 offset 3dh: int_pin?interrupt pin (modem? d31:f6) note: this register indicates which pci interrupt pin is used for the ac?97 modem interrupt. the ac?97 interrupt is internally or?d to the interrupt controller with the pirqb# signal. 14.1.17 offset 50h: pid?pci power management capability id register (modem?d31:f6) table 512. offset 3dh: int_pin?interrupt pin (modem?d31:f6) bits name description access 7:3 reserved reserved. 2:0 ac?97 interrupt routing hardwired to 010b to select pirqb#. ro table 513. offset 50h: pid?pci power management capability id register (modem?d31:f6) bits name description access 15:8 next capability (next) indicates that this is the last item in the list. ro 7:0 cap id (cap) indicates that this pointer is a message signaled interrupt capability. ro device: 29 function: 5 offset: 3dh attribute: read-only default value: 02h size: 8-bit lockable: no power well: core device: 29 function: 5 offset: 0001h attribute: read-only default value: 0001h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 591 14?intel ? 6300ESB ich 14.1.18 offset 52h: pc?power management capabilities register (modem?d31:f6) 14.1.19 offset 54h: pcs?power management control and status register (modem?d31:f6) note: this register is not affected by the d3 hot to d0 transition. table 514. offset 52h: pc?power management capabilities register (modem? d31:f6) bits name description access 15:1 1 pme_support indicates pme# may be generated from all d states. ro 10:9 reserved reserved. ro 8:6 aux_current reports 375 ma maximum suspend well current required when in the d3cold state. ro 5 device specific initial- ization (dsi) indicates that no device-specific initialization is required. ro 4 reserved reserved. ro 3 pme clock (pmec) indicates that pci clock is not required to generate pme#. ro 2:0 version (vs) indicates support for revision 1.1 of the pci power management specification. ro table 515. offset 54h: pcs?power management control and status register (modem?d31:f6) (sheet 1 of 2) bits name description access 15 pme status (pmes) this bit is set when the ac?97 controller would normally assert the pme# signal independent of the state of the pme_en bit. this bit resides in the resume well. rw/c 14:9 reserved reserved. ro device: 29 function: 5 offset: 52h attribute: read-only default value: c9c2h size: 16-bit lockable: no power well: core device: 29 function: 5 offset: 54h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: resume
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 592 order number: 300641-004us 8 power management event enable (pmee) when set, and if corresponding pmes is also set, the ac'97 controller sets the ac97_sts bit in the gpe0_sts register. r/w 7:2 reserved reserved. ro 1:0 power state (ps) this field is used both to determine the current power state of the ac?97 controller and to set a new power state. the values are: 00 ? d0 state 01 ? not supported 10 ? not supported 11 ? d3 hot state when in the d3 hot state, the ac?97 controller?s configuration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. when software attempts to write a value of 10b or 01b to this field, the write operation must complete normally. however, the data is discarded and no state change occurs. r/w table 515. offset 54h: pcs?power management control and status register (modem?d31:f6) (sheet 2 of 2) bits name description access device: 29 function: 5 offset: 54h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: resume
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 593 14?intel ? 6300ESB ich 14.2 ac?97 modem i/o space (d31:f6) in the case of split codec implementation, accesses to the modem mixer registers in different codecs are differentiated by the controller by using address offsets 00h - 7fh for the primary codec and address offsets 80h - feh for the secondary codec. ta b l e 5 1 6 shows the register addresses for the modem mixer registers. the global control (glob_cnt) and global status (glob_sta) registers are aliased to the same global registers in the audio and modem i/o space. therefore a read/write to these registers in either audio or modem i/o space affects the same physical register. s/w could access these registers as bytes, word, or dword quantities, but reads must not cross dword boundaries. these registers exist in i/o space and reside in the ac ?97 controller. the two channels, modem in and modem out, each have their own set of bus mastering registers. the following register descriptions apply to both channels. the naming prefix convention table 516. intel ? 6300ESB i/o controller hub modem mixer register configuration register mmbar exposed registers (d31:f6) primary secondary name 00h:38h 80h:b8h intel reserved 3ch bch extended modem id 3eh beh extended modem stat/ctrl 40h c0h line 1 dac/adc rate 42h c2h line 2 dac/adc rate 44h c4h handset dac/adc rate 46h c6h line 1 dac/adc level mute 48h c8h line 2 dac/adc level mute 4ah cah handset dac/adc level mute 4ch cch gpio pin config 4eh ceh gpio polarity/type 50h d0h gpio pin sticky 52h d2h gpio pin wake up 54h d4h gpio pin status 56h d6h misc. modem afe stat/ctrl 58h d8h ac?97 reserved 5ah dah vendor reserved 7ch fch vendor id1 7eh feh vendor id2 notes: 1. registers in italics are for functions not supported by the intel ? 6300ESB ich. 2. software should not try to access reserved registers. 3. the intel ? 6300ESB ich supports a modem codec connected to ac_sdin[2:0] as long as the codec id is 00 or 01. however, the intel ? 6300ESB ich does not support more than one modem codec. for a complete list of topologies, see the intel ? 875p/e7210/6300ESB chipset platform design guide.
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 594 order number: 300641-004us used is as follows: mi = modem in channel mo = modem out channel table 517 presents the modem registers. note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the registers shared with the ac?97 audio controller (gcr, gsr, casr). resume well registers will not be reset by the d3 hot to d0 transition. core well registers and bits not reset by the d3 hot to d0 transition: ? offset 3ch-3fh ? bits[6:0] global control (glob_cnt) ? offset 40h-43h ? bits[29,15,11:10] global status (glob_sta) ? offset 44h ? codec access semaphore register (cas) resume well registers and bits will not be reset by the d3 hot to d0 transition: ? offset 40h-43h ? bits[17:16] global status (glob_sta) table 517. modem registers offset mnemonic name default access 00h mi_bdbar modem in buffer descriptor list base address register 00000000 h r/w 04h mi_civ modem in current index value register 00h r 05h mi_lvi modem in last valid index register 00h r/w 06h mi_sr modem in status register 0001h r/w 08h mi_picb modem in position in current buffer register 00h r 0ah mi_piv modem in prefetch index value register 00h ro 0bh mi_cr modem in control register 00h r/w 10h mo_bdbar modem out buffer descriptor list base address register 00000000 h r/w 14h mo_civ modem out current index value register 00h ro 15h mo_lvi modem out last valid register 00h r/w 16h mo_sr modem out status register 0001h r/w 18h mi_picb modem in position in current buffer register 00h ro 1ah mo_piv modem out prefetched index register 00h ro 1bh mo_cr modem out control register 00h r/w 3ch glob_cnt global control 00000000 h r/w 40h glob_sta global status 00000000 h ro 44h acc_sema codec write semaphore register 00h r/w note: mi = modem in channel; mo = modem out channel
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 595 14?intel ? 6300ESB ich 14.2.1 x _bdbar?buffer descriptor list base address register note: software may read the register at offset 00h by performing a single 32-bit read from address offset 00h. reads across dword boundaries are not supported. 14.2.2 x _civ?current index value register note: software may read the registers at offsets 04h, 05h and 06h simultaneously by performing a single 32-bit read from address offset 04h. software may also read this register individually by doing a single 8-bit read to offset 04h. reads across dword boundaries are not supported. table 518. x_bdbar?buffer descriptor list base address register bits name description access 31:3 buffer descriptor list base address[31:3] these bits represent address bits 31:3. the entries should be aligned on 8-byte boundaries. r/w 2:0 hardwired to ?0?. table 519. x_civ?current index value register bits name description access 7:5 hardwired to ?0?. 4:0 current index value [4:0] these bits represent which buffer descriptor within the list of 16 descriptors is being processed currently. as each descriptor is processed, this value is incremented. ro device: 29 function: 5 i/o address: mbar + 00h (mibdbar), mbar + 10h (mobdbar) attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core device: 29 function: 5 i/o address: mbar + 04h (miciv), mbar + 14h (mociv) attribute: read-only default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 596 order number: 300641-004us 14.2.3 x _lvi?last valid index register note: software may read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software may also read this register individually by doing a single, 8-bit read to offset 05h. reads across dword boundaries are not supported. 14.2.4 x _sr?status register note: software may read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software may also read this register individually by doing a single, 16-bit read to offset 06h. reads across dword boundaries are not supported. table 520. x_lvi?last valid index register bits name description access 7:5 hardwired to 0 hardwired to 0. 4:0 last valid index [4:0] these bits indicate the last valid descriptor in the list. this value is updated by the software as it prepares new buffers and adds to the list. r/w table 521. x_sr?status register (sheet 1 of 2) bits name description access 15:5 reserved reserved. 4 fifo error (fifoe) 0 = cleared by writing a ?1? to this bit position. 1 = fifo error occurs. modem in: fifo error indicates a fifo overrun. the fifo pointers don't increment, the incoming data is not written into the fifo, thereby being lost. modem out: fifo error indicates a fifo underrun. the sample transmitted in this case should be the last valid sample. the intel ? 6300ESB ich will set the fifoe bit if the under- run or overrun occurs when there are more valid buffers to process. r/wc 3 buffer completion interrupt status (bcis) 0 = cleared by writing a ?1? to this bit position. 1 = set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion (ioc) bit is set in the command byte of the buffer descriptor. remains active until software clears bit. r/wc device: 29 function: 5 i/o address: mbar + 05h (milvi), mbar + 15h (molvi) attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 29 function: 5 i/o address: mbar + 06h (misr), mbar + 16h (mosr) attribute: read/write clear default value: 0001h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 597 14?intel ? 6300ESB ich 14.2.5 x _picb?position in current buffer register note: software may read the registers at the offsets 08h, 0ah, and 0bh by performing a 32- bit read from address offset 08h. software may also read this register individually by doing a single 16-bit read to offset 08h. reads across dword boundaries are not supported. 2 last valid buffer completion interrupt (lvbci) 0 = cleared by writing a ?1? to this bit position 1 = set by hardware when last valid buffer has been processed. it remains active until cleared by software. this bit indicates the occurrence of the event signified by the last valid buffer being processed. thus, this is an event status bit that may be cleared by software once this event has been recognized. this event will cause an interrupt if the enable bit in the control register is set. the interrupt is cleared when the software clears this bit. in the case of transmits (pcm out, modem out), this bit is set after the last valid buffer has been fetched (not after transmitting it). in the case of receives, this bit is set after the data for the last buffer has been written to memory. r/wc 1 current equals last valid (celv) 0 = hardware clears when controller exits state (i.e., until a new value is written to the lvi register). 1 = current index is equal to the value in the last valid index register, and the buffer pointed to by the civ has been processed (i.e., after the last valid buffer has been processed). this bit is very similar to bit 2, except this bit reflects the state rather than the event. this bit reflects the state of the controller and remains set until the controller exits this state. ro 0 dma controller halted (dch) 0 = running. 1 = halted. this could happen because of the start/stop bit being cleared and the dma engines are idle, or it could happen once the controller has processed the last valid buffer. ro table 522. x_picb?position in current buffer register bits name description access 15:0 position in current buffer[15:0] these bits represent the number of samples left to be processed in the current buffer. ro table 521. x_sr?status register (sheet 2 of 2) bits name description access device: 29 function: 5 i/o address: mbar + 06h (misr), mbar + 16h (mosr) attribute: read/write clear default value: 0001h size: 16-bit lockable: no power well: core device: 29 function: 5 i/o address: mbar + 08h (mipicb), mbar + 18h (mopicb) attribute: read-only default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 598 order number: 300641-004us
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 599 14?intel ? 6300ESB ich 14.2.6 x _piv?prefetch index value register note: software may read the registers at offsets 08h, 0ah, and 0bh by performing a 32-bit read from address offset 08h. software may also read this register individually by doing a single 8-bit read to offset 0ah. reads across dword boundaries are not supported. 14.2.7 x _cr?control register note: software may read the registers at offsets 08h, 0ah, and 0bh by performing a 32-bit read from address offset 08h. software may also read this register individually by doing a single 8-bit read to offset 0bh. reads across dword boundaries are not supported. table 523. x_piv?prefetch index value register bits name description access 15:0 position in current buffer[15:0] these bits represent the number of samples left to be processed in the current buffer. ro table 524. x_cr?control register (sheet 1 of 2) bits name description access 7:5 reserved reserved. 4 interrupt on completion enable (ioce) this bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. 0 = disable 1 = enable r/w 3 fifo error interrupt enable (feie) this bit controls whether the occurrence of a fifo error will cause an interrupt or not. 0 = disable. bit 4 in the status register will be set, but the interrupt will not occur. 1 = enable. interrupt will occur. r/w device: 29 function: 5 i/o address: mbar + 0ah (mipiv), mbar + 1ah (mopiv) attribute: read-only default value: 00h size: 8-bit lockable: no power well: core device: 29 function: 5 i/o address: mbar + 0bh (micr), mbar + 1bh (mocr) attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 600 order number: 300641-004us 14.2.8 glob_cnt?global control register note: reads across dword boundaries are not supported. 2 last valid buffer interrupt enable (lvbie) this bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = disable. bit 2 in the status register will still be set, but the interrupt will not occur. 1 = enable r/w 1 reset registers(rr) 0 = removes reset condition. 1 = contents of all registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). software must set this bit. it must be set only when the run/pause bit is cleared. setting it when the run bit is set will cause undefined consequences. this bit is self-clearing (software needs not clear it). r/w (special) 0 run/pause bus master (rpbm) 0 = pause bus master operation. this results in all state information being retained (i.e., master mode operation may be stopped and then resumed). 1 = run. bus master operation starts. r/w table 525. glob_cnt?global control register (sheet 1 of 2) bits name description access 31:7 reserved reserved 6 ac_sdin2 interrupt enable (s2re) 0 = disable. 1 = enable an interrupt to occur when the codec on ac_sdin[2] causes a resume event on the ac-link. r/w 5 ac_sdin1 resume interrupt enable (s1re) 0 = disable. 1 = enable an interrupt to occur when the codec on ac_sdin[1] causes a resume event on the ac-link. r/w 4 ac_sdin0 resume interrupt enable (s0re) 0 = disable. 1 = enable an interrupt to occur when the codec on ac_sdin[0] causes a resume event on the ac-link. r/w 3 aclink shut off (lso) 0 = normal operation. 1 = controller disables all outputs which will be pulled low by internal pull down resistors. r/w table 524. x_cr?control register (sheet 2 of 2) bits name description access device: 29 function: 5 i/o address: mbar + 0bh (micr), mbar + 1bh (mocr) attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 29 function: 5 i/o address: mbar + 3ch attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 601 14?intel ? 6300ESB ich 14.2.9 glob_sta?global status register note: on reads from a codec, the controller will give the codec a maximum of four frames to respond, after which, if no response is received, it will return a dummy read completion to the processor (with all ?f?s on the data) and also set the read completion status bit in the global status register. reads across dword boundaries are not supported. 2 ac?97 warm reset 0 = normal operation. 1 = writing a ?1? to this bit causes a warm reset to occur on the ac-link. the warm reset will awaken a suspended codec without clearing its internal registers. when software attempts to perform a warm reset while bit_clk is running, the write will be ignored and the bit will not change. this bit is self-clearing; it remains set until the reset completes and bit_clk is seen on the aclink, after which it clears itself. r/w (special) 1ac?97 cold reset# 0 = writing a ?0? to this bit causes a cold reset to occur throughout the ac ?97 circuitry. all data in the controller and the codec will be lost. software must clear this bit no sooner than the minimum number of ms have elapsed. 1 = this bit defaults to ?0? and hence after reset, the driver needs to set this bit to a ?1?. the value of this bit is retained after suspends; hence, when this bit is set to a ?1? prior to suspending, a cold reset is not generated automatically upon resuming. note: this bit is in the core well. r/w 0 gpi interrupt enable (gie) this bit controls whether the change in status of any gpi causes an interrupt. 0 = bit ?0? of the global status register is set, but no interrupt is generated. 1 = the change on value of a gpi causes an interrupt and sets bit ?0? of the global status register. r/w table 525. glob_cnt?global control register (sheet 2 of 2) bits name description access device: 29 function: 5 i/o address: mbar + 3ch attribute: read/write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 602 order number: 300641-004us table 526. glob_sta?global status register (sheet 1 of 3) bits name description access 31:3 0 reserved reserved. 29 ac_sdin2 resume interrupt (s2ri) this bit indicates that a resume event occurred on ac_sdin[2]. 0 = cleared by writing a ?1? to this bit position. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. r/wc 28 ac_sdin2 codec ready (s2cr) reflects the state of the codec ready bit in ac_sdin[2]. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. ro 27 bit clock stopped (bcs) indicates that the bit clock is not running. this bit is set when the intel ? 6300ESB ich detects that there has been no transition on bit_clk for four consecutive pci clocks. it is cleared when a transition is found on bit_clk. ro 26 s/pdif interrupt (spint) indicates that the s/pdif out channel interrupt status bits have been set. when the specific status bit is cleared, this bit will be cleared. ro 25 pcm in 2 interrupt (p2int) indicates that one of the pcm in 2 channel status bits have been set. when the specific status bit is cleared, this bit will be cleared. ro 24 microphone 2 in interrupt (m2int) indicates that one of the mic in channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 23:2 2 sample capabilities indicates the capability to support more greater than 16-bit au- dio. 00 = reserved 01 = 16 and 20-bit audio supported (intel ? 6300ESB ich value) 10 = reserved 11 = reserved ro 21:2 0 multichannel capabilities indicates the capability to support more 4 and 6 channels on pcm out. ro 19:1 8 reserved reserved. device: 29 function: 5 i/o address: mbar + 40h attribute: read-only, read/write, read/write clear default value: 00300000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 603 14?intel ? 6300ESB ich 17 md3 power down semaphore for modem. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the ad3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. r/w 16 ad3 power down semaphore for audio. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the md3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. r/w 15 read completion status (rcs) this bit indicates the status of codec read completions. 0 = a codec read completes normally. 1 = a codec read results in a time-out. the bit remains set until being cleared by software writing a ?1? to the bit location. this bit is not affected by d3 hot to d0 reset. r/wc 14 bit 3 of slot 12 display bit 3 of the most recent slot 12. ro 13 bit 2 of slot 12 display bit 2 of the most recent slot 12. ro 12 bit 1 of slot 12 display bit 1 of the most recent slot 12. ro 11 ac_sdin1 resume interrupt (s1ri) this bit indicates that a resume event occurred on ac_sdin[1]. 0 = cleared by writing a ?1? to this bit position. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. r/wc 10 ac_sdin0 resume interrupt (s0ri) this bit indicates that a resume event occurred on ac_sdin[0]. 0 = cleared by writing a ?1? to this bit position. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. r/wc 9 ac_sdin1 codec ready (s1cr) reflects the state of the codec ready bit in ac_sdin[1]. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. ro 8 ac_sdin0 codec ready (s0cr) reflects the state of the codec ready bit in ac_sdin [0]. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. ro table 526. glob_sta?global status register (sheet 2 of 3) bits name description access device: 29 function: 5 i/o address: mbar + 40h attribute: read-only, read/write, read/write clear default value: 00300000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?14 intel ? 6300ESB i/o controller hub ds november 2007 604 order number: 300641-004us 14.2.10 cas?codec access semaphore register note: reads across dword boundaries are not supported. 7 mic in interrupt (mint) this bit indicates that one of the mic in channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 6 pcm out interrupt (point) this bit indicates that one of the pcm out channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 5 pcm in interrupt (piint) this bit indicates that one of the pcm in channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 4:3 reserved reserved. ro 2 modem out interrupt (moint) this bit indicates that one of the modem out channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 1 modem in interrupt (miint) this bit indicates that one of the modem in channel interrupts status bits has been set. when the specific status bit is cleared, this bit will be cleared. ro 0 gpi status change interrupt (gsci) this bit reflects the state of bit ?0? in slot 12, and is set whenever bit ?0? of slot 12 is set. this indicates that one of the gpis changed state, and that the new values are available in slot 12. the bit is cleared by software writing a ?1? to this bit location. this bit is not affected by d3 hot to d0 reset. r/wc table 527. cas?codec access semaphore register bits name description access 7:1 reserved reserved. 0 codec access semaphore (cas) this bit is read by software to check whether a codec access is currently in progress. 0 = no access in progress. 1 = the act of reading this register sets this bit to 1. the driver that read this bit may then perform an i/o access. once the access is completed, hardware automatically clears this bit. r/w (special) table 526. glob_sta?global status register (sheet 3 of 3) bits name description access device: 29 function: 5 i/o address: mbar + 40h attribute: read-only, read/write, read/write clear default value: 00300000h size: 32-bit lockable: no power well: core device: 29 function: 5 i/o address: nabmbar + 44h attribute: read/write default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 605 15?intel ? 6300ESB ich multimedia timer registers 15 15.1 memory mapped registers the timer registers are memory mapped in a non-indexed scheme. this allows the processor to directly access each register without having to use an index register. the timer register space is 1024 bytes. the registers are generally aligned on 64-bit boundaries to simplify implementation with ia64 processors. there are four possible memory address ranges beginning at 1) fed0_0000h, 2) fed0_1000h, 3) fed0_2000h., 4) fed0_3000h. the choice of address range will be selected by configuration bits in general control register (offset d0h) in device 31, function 0. 15.1.1 behavioral rules 1. software must not attempt to read or write across register boundaries. for example, a 32-bit access should be to offset x0h, x4h, x8h, or xch. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0ah, 0bh, 0dh, 0eh, or 0fh. any accesses to these offsets will result in unexpected behavior and may result in a master abort. however, these accesses will not result in system hangs. 64-bit accesses may only be to x0h and must not cross 64-bit boundaries. 2. software should not write to read-only registers. 3. reads or writes to unimplemented timers should not be attempted. timers 3:31 are not implemented. 4. all registers are implemented in the core well, and all bits are reset by pxpcirst#. 5. reads to reserved registers or bits will return a value of ?0?. 6. software must not attempt locks to the memory mapped i/o ranges for multimedia timers. when attempted, the lock is not honored, which means potential deadlock conditions may occur. table 528. memory-mapped registers (sheet 1 of 2) offset register type 000-007h general capabilities and id read only 008-00fh reserved 010-017h general config read-write 018-01fh reserved 020-027h general interrupt status read/write clear 028-0efh reserved 0f0-0f7h main counter value read/write 0f8-0ffh reserved 100-107h timer 0 config and capabilities read/write 108-10fh timer 0 comparator value read/write 110-11fh reserved 120-127h timer 1 config and capabilities read/write 128-12fh timer 1 comparator value read/write
intel ? 6300ESB ich?15 intel ? 6300ESB i/o controller hub ds november 2007 606 order number: 300641-004us 15.1.2 offset 000-007h: general capabilities and id register 130-13fh reserved 140-147h timer 2 config and capabilities read/write 148-14fh timer 2 comparator value read/write 150-15fh reserved 160-3ffh reserved table 529. offset 000-007h: general capabilities and id register bits name description access 63:3 2 counter_clk_per_ca p main counter tick period: this read-only field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). this will return 0429b17f when read. this indicates a period of 69841279 fs (69.841279 ns). ro 31:1 6 vendor_id_cap this is a 16-bit value assigned to intel. these bits will return 8086h when read. ro 15 leg_rt_cap legacy rout capable: this bit will return a ?1? when read, indicating that the legacy interrupt rout option is supported. ro 14 reserved reserved. this bit will return ?0? when read. 13 count_size_cap counter size: this bit will return a ?1? when read, indicating that the counter is 64-bit wide. ro 12:8 num_tim_cap number of timers: this indicates the number of timers in this block. the value in this field is 02h, indicating that there are three timers. ro 7:0 rev_id this indicates which revision of the function is implemented. default value will be 01h. ro table 528. memory-mapped registers (sheet 2 of 2) offset register type offset: 000-007h attribute: read-only default value: 0429 b17f 8086 a201h size: 64-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 607 15?intel ? 6300ESB ich 15.1.3 offset 010-017h: general config register table 530. offset 010-017h: general config register bits name description access 63:2 reserved reserved. these bits will return ?0? when read. 1leg_rt_cnf legacy rout: when the enable_cnf bit and the leg_rt_cnf bit are both set, the interrupts will be routed as follows: ? timer 0 will be routed to irq0 in 8259 or irq2 in the i/o apic. ? timer 1 will be routed to irq8 in 8259 or irq8 in the i/o apic. ? timer 2-n will be routed as per the routing in the timer n config registers. ? when the legacy rout bit is set, the individual routing bits for timers 0 and 1 (apic) will have no impact. ? when the legacy rout bit is not set, the individual routing bits for each of the timers are used. ? this bit will default to ?0?. bios may set it to ?1? to enable the legacy routing or ?0? to disable the legacy routing. r/w 0 enable_cnf: overall enable this bit must be set to enable any of the timers to generate interrupts. when this bit is ?0?, the main counter will halt (will not increment) and no interrupts will be caused by any of these timers. for level-triggered interrupts, if an interrupt is pending when the enable_cnf bit is changed from ?1? to ?0?, the interrupt status indications in the various txx_int_sts bits will not be cleared. software must write to the txx_int_sts bits to clear the interrupts. note: this bit will default to ?0?. bios may set it to ?1? or ?0?. r/w offset: 010-017h attribute: read/write default value: 0000 0000 0000 0000h size: 64-bit
intel ? 6300ESB ich?15 intel ? 6300ESB i/o controller hub ds november 2007 608 order number: 300641-004us 15.1.4 offset 020-027h: general interrupt status register table 531. offset 020-027h: general interrupt status register bits name description access 63:3 reserved reserved. these bits will return ?0? when read. 2 t02_int_sts: timer 2 interrupt active same functionality as timer 0. r/w 1 t01_int_sts: timer 1 interrupt active same functionality as timer 0. r/w 0 t00_int_sts: timer 0 interrupt active the functionality of this bit depends on whether the edge or level-triggered mode is used for this timer: when set to level-triggered mode: this bit defaults to ?0?. this bit will be set by hardware when the corresponding timer interrupt is active. once the bit is set, it may be cleared by software writing a ?1? to the same bit position. writes of ?0? to this bit will have no effect. for example, if the bit is already set, a write of ?0? will not clear the bit. when set to edge-triggered mode: this bit should be ignored by software. software should always write ?0? to this bit. note: defaults to ?0?. in edge-triggered mode, this bit will always read as ?0? and writes will have no effect. r/w offset: 020-027h attribute: read/write default value: 0000 0000 0000 0000h size: 64-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 609 15?intel ? 6300ESB ich 15.1.5 offset 0f0 - 0f7h: main counter value 15.1.6 timer n config and capabilities note: the letter n may be 0, 1, or 2, referring to timer 0, 1 or 2. table 532. offset 0f0 - 0f7h: main counter value bits name description access 63:0 counter_val[63:0] reads return the current value of the counter. writes load the new value to the counter. notes: 1. software can access the various bytes in this register using 32-bit or 64-bit accesses. 32-bit accesses can be done to offset 0f0h or 0f4h. 64-bit accesses can be done to 0f0h. 32-bit accesses must not be done starting at: 0f1h, 0f2h, 0f3h, 0f5h, 0f6h, or 0f7h. 2. writes to this register should only be done while the counter is halted. 3. reads to this register return the current value of the main counter. 4. 32-bit counters will always return ?0? for the upper 32 bits of this register. 5. if 32-bit software attempts to read a 64-bit counter, it should first halt the counter. since this will delay the interrupts for all of the timers, this should be done only if the consequences are understood. it is strongly recommended that 32-bit software only operate the timer in 32-bit mode. 6. reads to this register are monotonic. no two consecutive reads will return the same value. the second of two reads will always return a larger value (unless the timer has rolled over to ?0?). r/w offset: 0f0-0f7h attribute: read/write default value: n/a size: 64-bit
intel ? 6300ESB ich?15 intel ? 6300ESB i/o controller hub ds november 2007 610 order number: 300641-004us table 533. timer n config and capabilities (sheet 1 of 3) bits name description access 64:5 6 reserved reserved. these bits will return ?0? when read. 63:3 2 timern_int_rout_cap : timern_int_rout[31: 0]_cap this 32-bit read-only field indicates which interrupts in the i/ o (x) apic this timer?s interrupt may be routed to. this is used in conjunction with the timern_int_rout_cnf field. each bit in this field corresponds to a particular interrupt. for example, when this timer?s interrupt may be mapped to interrupts 16, 18, 20, 22, or 24, bits 16, 18, 20, 22, and 24 in this field will be set to ?1?. all other bits will be ?0?. intel ? 6300ESB ich and timer 0, 1 specific: bits 20, 21, 22, and 23 in this field (corresponding to bits 52, 53, 54, and 55 in this register) will have a value of ?1?. all other bits will be ?0?. writes will have no effect. intel ? 6300ESB ich and timer 2 specific: bits 11, 20, 21, 22, and 23 in this field (corresponding to bits 43, 52, 53, 54, and 55 in this register) will have a value of ?1?. all other bits will be ?0?. writes will have no effect. when irq 11 is used for mmt#2, software should ensure irq11 is not shared with any other devices to ensure the proper operation of mmt#2. 31:1 6 reserved reserved. these bits will return ?0? when read. 15 timern_fsb_int_del_ cap: fsb interrupt delivery (where n is the timer number: 00 to 31) if this read-only bit is 1, then the hardware supports a direct processor side bus delivery of this timer?s interrupt. note: this bit will always read as 0, since the intel ? 6300ESB ich multimedia timer implementation does not support the direct fsb interrupt delivery. 14 timern_fsb_en_cnf (where n is the timer number: 00 to 31). if the timern_fsb_int_del_cap bit is set for this timer, then the software can set the timern_fsb_en_cnf bit to force the interrupts to be delivered directly as fsb messages, rather than using the i/o (x) apic. in this case, the timern_int_rout_cnf field in this register will be ignored. the timern_fsb_rout register will be used instead. offset: timer 0: 100-107h, timer 1: 120-127h, timer 2: 140-147h attribute: read/write default value: n/a size: 64-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 611 15?intel ? 6300ESB ich 13:9 timern_int_rout_cnf interrupt rout: this 5-bit field indicates the routing for the interrupt to the i/o (x) apic. a maximum value of 32 interrupts is supported; default is 00h. software writes to this field to select which interrupt in the i/o (x) will be used for this timer?s interrupt. when the value is not supported by this particular timer, the value read back will not match what is written. the software must only write valid values. notes: 1. when the legacy rout bit is set, timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. 2. timer 0,1 specific: software is responsible to make sure it programs a valid value (20, 21, 22, or 23) for this field. the intel ? 6300ESB ich logic does not check the validity of the value written. 3. timer 2 specific: software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23) for this field. the intel ? 6300ESB ich logic does not check the validity of the value written. 8 timern_32mode_cnf timer n 32-bit mode: software may set this bit to force a 64- bit timer to behave as a 32-bit timer. for timer 0, this bit will be read/write and default to ?0?. for timers 1 and 2, this bit will always read as ?0?, and writes will have no effect, since these two timers are 32 bits. 7 reserved reserved. this bit will return ?0? when read. 6 timern_val_set_cnf timer n value set: software uses this bit only for timer 0 when it has been set to periodic mode. by writing this bit to a ?1?, the software is then allowed to directly set the timer?s accumulator. software does not have to write this bit back to ?0?; it automatically clears. software should not write a ?1? to this bit position when the timer is set to non-periodic mode. note: this bit will return ?0? when read. writes will only have an effect for timer 0 when it is set to periodic mode. writes will have no effect for timers 1 and 2. 5 timern_size_cap timer n size: this read-only field indicates the size of the timer. value is ?1? (64 bits) for timer 0. value is ?0? (32 bits) for timers 1 and 2. 4 timern_per_int_cap periodic interrupt capable: when this read-only bit is ?1?, the hardware supports a periodic mode for this timer?s interrupt. timer 0 will support the periodic interrupt, so the bit will always read as a ?1?. timers 1 and 2 will not support periodic interrupts, so the bit will always read as ?0?. table 533. timer n config and capabilities (sheet 2 of 3) bits name description access offset: timer 0: 100-107h, timer 1: 120-127h, timer 2: 140-147h attribute: read/write default value: n/a size: 64-bit
intel ? 6300ESB ich?15 intel ? 6300ESB i/o controller hub ds november 2007 612 order number: 300641-004us 3timern_type_cnf timer n type: for timers 1 and 2, this bit will always return ?0? when read and writes will have no impact. for timer 0, this bit is read/write, and may be used to enable the timer to generate a periodic interrupt. writing a 1 to this bit enables the timer to generate a periodic interrupt. note: for timer 0, this bit will be read/write, with default of ?0?. for timers 1:2, this bit will be read-only, with a fixed value of ?0?. 2 timern_int_enb_cnf timer n interrupt enable: this bit must be set to enable timer n to cause an interrupt when it times out. when this bit is ?0?, the timer may still count and generate appropriate status bits but will not cause an interrupt. default value is ?0?. 1 timern_int_type_cnf timer interrupt type: 0 = the timer interrupt is edge triggered. this means that an edge-type interrupt is generated. when another interrupt occurs, another edge will be generated. 1 = the timer interrupt is level triggered. this means that a level-triggered interrupt is generated. the interrupt will be held active until it is cleared by writing to the bit in the general interrupt status register. when another interrupt occurs before the interrupt is cleared, the interrupt will remain active. note: the default value is ?0?, edge-triggered. the interrupt type is not expected to be changed dynamically. the interrupt type for any timer should be set before any interrupts are generated by that timer. if the interrupt type is changed dynamically, there will be some delay before the new type takes effect. that delay is not known at this time. supports edge and level triggered modes for all three timers. 0 reserved reserved. these bits will return ?0? when read. table 533. timer n config and capabilities (sheet 3 of 3) bits name description access offset: timer 0: 100-107h, timer 1: 120-127h, timer 2: 140-147h attribute: read/write default value: n/a size: 64-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 613 15?intel ? 6300ESB ich 15.1.7 timer n comparator value table 534. timer n comparator value bits name description access 63:0 1. reads to this register return the current value of the comparator. 2. when timers 0,1, or 2 are configured to non-periodic mode: a. writes to this register load the value against which the main counter will be compared for this timer. b. when the main counter equals the value last written to this register, the corresponding interrupt will be generated (when enabled). c. the value in this register does not change based on the interrupt being generated. 3. when timer 0 is configured to periodic mode: a. when the main counter equals the value last written to this register, the corresponding interrupt will be generated (when enabled). b. after the main counter equals the value in this register, the value in this register is increased by the value last written to the register. for example, if the value written to the register is 00000123h, then: 1. an interrupt will be generated when the main counter reaches 00000123h. 2. the value in this register will be adjusted by the hardware to 00000246h. 3. another interrupt will be generated when the main counter reaches 00000246h. 4. the value in this register will be adjusted by the hardware to 00000369h. c. as each periodic interrupt occurs, the value in this register will increment. when the incremented value is greater than the maximum value possible for this register (ffffffffh for a 32-bit timer or ffffffffffffffffh for a 64-bit timer), the value will wrap around through 0. for example, if the current value in a 32-bit timer is ffff0000h and the last value written to this register is 20000, then after the next interrupt the value will change to 00010000h. 4. default value for each timer is all ones for the bits that are implemented. for example, a 32-bit timer will have a default value of 00000000ffffffffh. a 64-bit timer will have a default value of ffffffffffffffffh. offset: timer 0: 108h ? 10fh, timer 1: 128h ? 12fh, timer 2: 148h ? 14fh attribute: read/write default value: n/a size: 64-bit
intel ? 6300ESB ich?15 intel ? 6300ESB i/o controller hub ds november 2007 614 order number: 300641-004us
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 615 16?intel ? 6300ESB ich watchdog timer (wdt) (d29:f4) 16 16.1 product features the watchdog timer (wdt) supports the following features and functions: ? selectable prescaler ? approximately 1 mhz and approximately 1 khz ? 33 mhz clock (30 ns clock ticks) ? multiple modes: wdt and free-running ? free-running mode: ? one stage timer. ? toggles wdt_out# after programmable time. ?wdt mode: ? two stage timer: 1. first stage generates irq and smi interrupt after programmable time. 2. second stage drives wdt_out# low or inverts the previous value. *used only after first timeout occurs. *status bit preserved in rtc well for possible error detection and correction. *drives wdt_tout# when output is enabled. ? timer may be disabled (default state) or locked (hard reset required to disable wdt) ? wdt automatic reload of preload value when wdt reload sequence is performed note: the wdt device (dev 29:f4) cannot be hidden by using bit 12 of the d31:f0 func_dis register. the wdt will always be present as a pci device in pci config space.
intel ? 6300ESB ich?16 intel ? 6300ESB i/o controller hub ds november 2007 616 order number: 300641-004us 16.2 product overview the timer uses a 35-bit down-counter. the counter is loaded with the value from the first preload register. the timer is then enabled and starts counting down. the time at which the wdt first starts counting down is called the first stage. when the host fails to reload the wdt before the 35-bit down-counter reaches zero, the wdt generates an internal interrupt. after the interrupt is generated, the wdt loads the value from the second preload register into the wdt?s 35-bit down-counter and starts counting down. the wdt is now in the second stage. when the host still fails to reload the wdt before the second timeout, the wdt drives the wdt_tout# pin low and sets the timeout bit (wdt_timeout). this bit indicates that the system has become unstable. the wdt_tout# pin is held low until the system is reset or the wdt times out again (depending on tout_cnf). the process of reloading the wdt involves the following sequence of writes: 1. write 80 to offset bar + 0ch. 2. write 86 to offset bar + 0ch. 3. write 1 to wdt_reload in reload register. the same process is used for setting the values in the preload registers. the only difference exists in step 3. instead of writing a ?1? to the wdt_reload, write the desired preload value into the corresponding preload register. this value is not loaded into the 35-bit down-counter until the next time the wdt reenters the stage. for example, when preload value 2 is changed, it is not loaded into the 35-bit down- counter until the next time the wdt enters the second stage. figure 29. wdt block diagram pci configuration registers reset/interrupt control logic down - counter irq/smi (internal) wdt_tout# (external) pci preload value 1 preload value 2
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 617 16?intel ? 6300ESB ich 16.3 signal descriptions the following signals are driven from the wdt. 16.4 device 29: function 4 configuration registers 16.4.1 configuration registers table 535. wdt interface signal type name and description wdt_tout#/ gpio[32] o watchdog timer timeout: the wdt_tout# signal is driven low from the intel ? 6300ESB ich to an external pin. the signal is driven low when the main 35-bit down-counter reaches zero during the second stage. the wdt_tout_cnf bit in the configuration register determines if the output is to change from the previous state when another timeout occurs, or wdt_out# is driven low until the system is reset or power is cycled. driven active to indicate the second stage of the wdt has overflowed. this signal will toggle states for each overflow in periodic mode. in non-periodic mode, this signal will go active low and remain in this state until a system reset or power cycle. this signal is muxed with gpio[32]. wdt_int (internal only signal) o interrupt: the wdt_int# is an internal signal that is used to generate an interrupt when the first stage has been allowed to reach zero. the wdt is capable of generating sci, smi, and irq (apic 1, int 10) based interrupts. interrupts are not generated when wdt_tout_cnf is set to change output after every timeout (see configuration register). the wdt int# signal is an active low interrupt. table 536. configuration registers (sheet 1 of 2) offset register default type 00-01h vendor id 8086h read only 02-03h device id 25abh read only 04-05h command register (com) 0000h read/write 06-07h device status register (ds) 0280h read/write clear 08h revision id register (rid) see note: read only 09h programming interface register (pi) 00h read only 0ah sub class code register (scc) 80h read only 0bh base class code register (bcc) 08h read only 0eh header type register (hedt) 00h read only 10-13h base address register (bar) 00000000h read/write note: refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to- date value of the revision id register.
intel ? 6300ESB ich?16 intel ? 6300ESB i/o controller hub ds november 2007 618 order number: 300641-004us 16.4.2 memory mapped registers 16.4.3 offset 00h: vid?vendor identification register 14-2bh reserved 00h 2c-2dh subsystem vendor id 00h read/write once 2e-2f subsystem id 00h read/write once 30-5f reserved 00h 60-61h wdt configuration 00h read/write 64-67h reserved 0000h 68h wdt lock register 00h read/write 6c-f7 reserved 00h f8-fbh manufacturer?s id 00000f66h read only fc-ffh reserved 00h table 537. memory mapped registers offset register default type base + 00h preload value 1 fffffh read/write base + 04h preload value 2 fffffh read/write base + 08h general interrupt status 00h read/write/clear base + 0ch reload register 0000h write table 538. offset 00h: vid?vendor identification register bits name description access 15:0 vendor id table 536. configuration registers (sheet 2 of 2) offset register default type note: refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to- date value of the revision id register. device: 29 function: 4 offset: 00h attribute: read-only default value: 8086h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 619 16?intel ? 6300ESB ich 16.4.4 offset 02h: did?device identification register 16.4.5 offset 04 - 05h: com?command register table 539. offset 02h: did?device identification register bits name description access 15:0 device id table 540. offset 04 - 05h: com?command register bits name description access 15:1 0 reserved reserved. na 9 fast back-to-back enable (fbe) reserved as ?0?. ro 8 serr# enable reserved as ?0?. ro 7 wait cycle control reserved as ?0?. ro 6 parity error response reserved as ?0?. ro 5 vga palette snoop reserved as ?0?. ro 4 pmwe - postable memory write enable reserved as ?0?. ro 3 sce - special cycle enable reserved as ?0?. ro 2 bme - bus master enable reserved as ?0?. ro 1 mse - memory space enable this bit controls access to the wdt?s memory mapped registers. if this bit is set, accesses to the wdt?s memory mapped registers are enabled. the base address register for wdt should be programmed before this bit is set. r/w 0 iose - i/o space enable reserved as ?0?. ro device: 29 function: 4 offset: 02h attribute: read-only default value: 25abh size: 16-bit lockable: no power well: core device: 29 function: 4 offset: 04 - 05h attribute: read-only default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?16 intel ? 6300ESB i/o controller hub ds november 2007 620 order number: 300641-004us 16.4.6 offset 06h - 07h: ds?device status register table 541. offset 06h - 07h: ds?device status register bits name description access 15 dpe - detected parity error reserved as ?0?. ro 14 sse - signaled system error reserved as ?0?. ro 13 rma - received master abort reserved as ?0?. ro 12 rta - received target abort reserved as ?0?. ro 11 sta - signaled target- abort status this bit is set when the function is targeted with a transaction that the intel ? 6300ESB ich terminates with a target abort. software resets sta to ?0? by writing a ?1? to this bit location. r/wc 10:9 devt - devsel# timing status this 2-bit field defines the timing for devsel# assertion. these read only bits indicate intel ? 6300ESB ich?s devsel# timing when performing a positive decode. the intel ? 6300ESB ich generates devsel# with medium time. ro 8 data parity error detected reserved as ?0?. ro 7 fast back-to-back capable reserved as ?1?. ro 6 udf - user definable features reserved as ?0?. ro 5 66 mhz capable reserved as ?0?. ro 4:0 reserved reserved. ro device: 29 function: 4 offset: 06h - 07h attribute: read/write clear default value: 0280h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 621 16?intel ? 6300ESB ich 16.4.7 offset 08h: rid?revision identification register note: refer to the intel ? 6300ESB i/o controller hub specification update for the most up- to-date value of the revision id. table 542. offset 08h: rid?revision identification register bits name description access 15 dpe - detected parity error reserved as ?0?. ro 14 sse - signaled system error reserved as ?0?. ro 13 rma - received master abort reserved as ?0?. ro 12 rta - received target abort reserved as ?0?. ro 11 sta - signaled target- abort status this bit is set when the function is targeted with a transaction that intel ? 6300ESB ich terminates with a target abort. software resets sta to ?0? by writing a ?1? to this bit location. r/wc 10:9 devt - devsel# timing status this two-bit field defines the timing for devsel# assertion. these read-only bits indicate the intel ? 6300ESB ich?s devsel# timing when performing a positive decode. the intel ? 6300ESB ich generates devsel# with medium time. ro 8 data parity error detected reserved as ?0?. ro 7 fast back-to-back capable reserved as ?1?. ro 6 udf - user definable features reserved as ?0?. ro 5 66 mhz capable reserved as ?0?. ro 4:0 reserved reserved. ro device: 29 function: 4 offset: 08h attribute: read-only default value: see note size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?16 intel ? 6300ESB i/o controller hub ds november 2007 622 order number: 300641-004us 16.4.8 offset 09h: pi?programming interface register 16.4.9 offset 0ah: scc?sub class code register 16.4.10 offset 0bh: bcc?base code class register 16.4.11 offset 0eh: hedt?header type register note: the base address register points to several memory mapped registers for the watchdog timer. it decodes the smallest possible region of 16 bytes. table 543. offset 09h: pi?programming interface register bits name description access 7:0 programming interface table 544. offset 0ah: scc?sub class code register bits name description access 7:0 sub class code table 545. offset 0bh: bcc?base code class register bits name description access 7:0 base code class device: 29 function: 4 offset: 09h attribute: read-only default value: 00h size: 8-bit lockable: no power well: core device: 29 function: 4 offset: 0ah attribute: read-only default value: 80h size: 8-bit lockable: no power well: core device: 29 function: 4 offset: 0bh attribute: read-only default value: 08h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 623 16?intel ? 6300ESB ich 16.4.12 offset 10h: bar?base address register 16.4.13 offset 2dh - 2ch: svid?subsystem vendor id note: software (bios) will write the value to this register. after that, the value may be read, but writes to the register will have no effect. the write to this register should be combined with the write to the sid to create one 32-bit write. table 546. offset 0eh: hedt?header type register bits name description access 7:0 header type table 547. offset 10h: bar?base address register bits name description access 31:4 base address these bits are used to determine the size of the memory- mapped region being requested. r/w 3prefetchable hard-wired to ?0?, indicating that this range is not pre- fetchable. ro 2:1 type hard-wired to ?00?, indicating that this range can be mapped anywhere in 32-bit address space. ro 0 rte - resource type indicator hard-wired to ?0?, indicating a request for memory space. ro device: 29 function: 4 offset: 0eh attribute: read-only default value: 00h size: 8-bit lockable: no power well: core device: 29 function: 4 offset: 10h attribute: read-write default value: 00000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?16 intel ? 6300ESB i/o controller hub ds november 2007 624 order number: 300641-004us 16.4.14 offset 2eh - 2fh: sid?subsystem id note: software (bios) will write the value to this register. after that, the value may be read, but writes to the register will have no effect. the write to this register should be combined with the write to the svid to create one 32-bit write. table 548. offset 2dh - 2ch: svid?subsystem vendor id bits name description access 31:4 base address these bits are used to determine the size of the memory- mapped region being requested. r/w 3prefetchable hard-wired to ?0?, indicating that this range is not pre- fetchable. ro 2:1 type hard-wired to ?00?, indicating that this range can be mapped anywhere in 32-bit address space. ro 0 rte - resource type indicator hard-wired to ?0?, indicating a request for memory space. ro table 549. offset 2eh - 2fh: sid?subsystem id bits name description access 15:0 subsystem id device: 29 function: 4 offset: 2dh - 2ch attribute: read, write once default value: 00h size: 16-bit lockable: no power well: core device: 29 function: 4 offset: 2eh-2fh attribute: read, write once default value: 00h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 625 16?intel ? 6300ESB ich 16.4.15 offset 60 - 61h: wdt configuration register 16.4.16 offset 68h: wdt lock register table 550. offset 60 - 61h: wdt configuration register bits name description access 15:6 reserved reserved. ro 5 wdt_output: output enable this bit indicates whether or not the wdt will toggle the external wdt_tout# pin when the wdt times out. 0 = enabled (default) 1 = disabled this signal is muxed with gpio32. r/w 4:3 reserved reserved. ro 2 wdt_pre_sel: prescaler select the wdt provides two options for prescaling the main down- counter. the preload values are loaded into the main down- counter right justified. the prescaler adjusts the starting point of the 35-bit down counter. 0 = the 20-bit preload value is loaded into bits 34:15 of the main down counter. the resulting timer clock is the pci clock (33 mhz) divided by 2 15 . the approximate clock generated is 1 khz, (default) 1 = the 20-bit preload value is loaded into bits 24:5 of the main down counter. the resulting timer clock is the pci clock (33 mhz) divided by 2 5 . the approximate clock generated is 1 mhz. note: timeout value is determined by the preload value multiplied by the clock period. r/w 1:0 wdt_int_type the wdt timer supports programmable routing of interrupts. the set of bits allows the user to choose the type of interrupt desired when the wdt reached the end of the first stage without being reset. 00 = irq (apic 1, int 10) (default) 01 = reserved 10 = smi 11 = disabled irq is active low, level triggered r/w device: 29 function: 4 offset: 60 - 61h attribute: read, write default value: 00h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?16 intel ? 6300ESB i/o controller hub ds november 2007 626 order number: 300641-004us table 551. offset 68h: wdt lock register bits name description access 7:3 reserved reserved. ro 2wdt_tout_cnf timeout configuration: this register is used to choose the functionality of the timer. 0 = watchdog timer mode: when enabled (i.e., wdt_enable goes from ?0? to ?1?) the timer will reload preload value 1 and start decrementing. (default) upon reaching the second stage timeout, the wdt_tout# is driven low once and will not change again until power is cycled or a hard reset occurs. 1 = free running mode: wdt_tout# will change from previous state when the next timeout occurs. the timer ignores the first stage. the timer only uses preload value 2. in this mode the timer is restarted whenever wdt_enable goes from a ?0? to a 1. this means that the timer will reload preload value 2 and start decrementing every time it is enabled. in free running mode it is not necessary to reload the timer as it is done automatically every time the decrementer reaches zero. r/w 1wdt_enable the following bit enables or disables the wdt. 0 = disabled (default) 1 = enabled note: this bit cannot be modified if wdt_lock has been set. note: in free-running mode, preload value 2 is reloaded into the down-counter every time wdt_enable goes from ?0? to ?1?. in wdt mode, preload value 1 is reloaded every time wdt_enable goes from ?0? to ?1? or the wdt_reload bit is written using the proper sequence of writes (see register unlocking sequence). warning: software should ensure that a timeout is not about to occur before disabling the timer. a reload sequence is suggested. r/w 0wdt_lock setting this bit will lock the values of this register until a hard reset occurs or power is cycled. 0 = unlocked (default) 1 = locked this is a write-once bit. it cannot be changed until either power is cycled or a hard reset occurs. r/wo device: 29 function: 4 offset: 68h attribute: read-write/write once default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 627 16?intel ? 6300ESB ich 16.4.17 offset f8 - fbh: manufacturer?s id 16.4.18 offset base + 00h: preload value 1 register preload value 2 register table 552. offset f8 - fbh: manufacturer?s id bits name description access 31:1 6 reserved reserved. ro 15:8 manufacturer 0fh = intel ro 7:0 process/dot 66h ro table 553. offset base + 00h: preload value 1 register bits name description access 31:2 0 reserved reserved. ro 19:0 preload_value_1 [19:0] use this register to hold the preload value for the wdt timer. the value in the preload register is automatically transferred into the 35-bit down-counter every time the wdt enters the first stage. note: the value loaded into the preload register needs to be one less than the intended period, as the timer makes use of zero-based counting (i.e., zero is counted as part of the decrement). please refer to section 16.5.2, ?register unlocking sequence? for details on how to change the value of this register. r/w device: 29 function: 4 offset: f8 - fbh attribute: read-only default value: 00000f66h size: 32-bit lockable: no power well: core device: 29 function: 4 offset: base + 00h attribute: read-write default value: fffffh size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?16 intel ? 6300ESB i/o controller hub ds november 2007 628 order number: 300641-004us 16.4.19 offset base + 04h: preload value 2 register preload value 2 register 16.4.20 offset base + 08h: general interrupt status register preload value 2 register table 554. offset base + 04h: preload value 2 register bits name description access 31:2 0 reserved reserved. ro 19:0 preload_value_2 [19:0] use this register to hold the preload value for the wdt timer. the value in the preload register is automatically transferred into the 35-bit down-counter every time the wdt enters the second stage. note: the value loaded into the preload register needs to be one less than the intended period, as the timer makes use of zero-based counting (i.e., zero is counted as part of the decrement). please refer to section 16.5.2, ?register unlocking sequence? for details on how to change the value of this register. r/w table 555. offset base + 08h: general interrupt status register bits name description access 7:1 reserved reserved. ro 0 watchdog timer interrupt active: (1 st stage) this bit is set when the first stage of the 35-bit down-counter reaches zero. an interrupt will be generated if wdt_int_type is configured to do so (see wdt configuration register). this is a sticky bit and is only cleared by writing a 1. 0 = no interrupt 1 = interrupt active note: this bit is not set in free-running mode. rwc device: 29 function: 4 offset: base + 04h attribute: read-write default value: fffffh size: 32-bit lockable: no power well: core device: 29 function: 4 offset: base + 08h attribute: read-write clear default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 629 16?intel ? 6300ESB ich 16.4.21 offset base + 0ch: reload register 16.5 theory of operation 16.5.1 rtc well and wdt_tout# functionality the wdt_timeout bit is set to a ?1? when the wdt 35-bit down counter reaches zero for the second time in a row. the wdt_tout# pin is then toggled low by the wdt from the intel ? 6300ESB ich. the board designer should attach the wdt_tout# to the appropriate external signal. when wdt_tout_cnf is a ?1? the wdt toggles wdt_tout# again when the next timeout occurs. otherwise, wdt_tout# is driven low until the system is reset or power is cycled. 16.5.2 register unlocking sequence the register unlocking sequence is necessary whenever writing to the reload register or either preload_value registers. the host must write a sequence of two writes to offset bar + 0ch before attempting to write to either the wdt_reload and wdt_timeout bits of the reload register or the preload_value registers. the first writes are 80 and 86, in that order, to offset bar + 0ch. the next write will be to the proper register (e.g., reload, preload_value_1, preload_value_2) table 556. offset base + 0ch: reload register bits name description access 15:1 0 reserved reserved. ro 9wdt_timeout this bit resides in the rtc well and its value is not lost if the host resets the system. it is set to '1' if the host fails to reset the wdt before the 35-bit down-counter reaches zero for the second time in a row. this bit is cleared by performing the register unlocking sequence followed by a '1' to this bit. 0 = normal (default). 1 = system has become unstable. note: in free running mode this bit is set every time the down counter reaches zero. r/w 8wdt_reload to prevent a timeout, the host must perform the register unlocking sequence followed by a '1' to this bit (see register unlocking sequence). note: refer to register unlocking sequence for details on how to write to this bit. r/w 7:0 reserved reserved. w note: the reload sequence is only necessary for the reload register and preload_value registers and is not used in free running mode. device: 29 function: 4 offset: base + 0ch attribute: read-write default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?16 intel ? 6300ESB i/o controller hub ds november 2007 630 order number: 300641-004us the following is an example of how to prevent a timeout: 1. write 80 to offset bar + 0ch. 2. write 86 to offset bar + 0ch. 3. write a ?1? to reload [8] (wdt_reload) of the reload register. note: any subsequent writes require that this sequence be performed again. 16.5.3 reload sequence to keep the timer from causing an interrupt or driving wdt tout#, the timer must be updated periodically. other timers refer to updating the timer as ?kicking? the timer. the frequency of updates required is dependent on the value of the preload values. to update the timer, the register unlocking sequence must be performed followed by writing a ?1? to bit 8 at offset bar+ 0ch within the watchdog timer memory mapped space. this sequence of events is referred to as the ?reload sequence?. 16.5.4 low power state the watchdog timer does not operate when pciclk is stopped.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 631 17?intel ? 6300ESB ich apic1 configuration registers (d29:f5) 17 apic1?s direct registers are assigned with base address fec1xxxxh. to support legacy device/driver on external pci bus used with the intel ichx, apic1 has an alternate base address fec0xxxxh. this means external pci devices may write to irq pin assertion register (either fec0_0020h or fec1_0020h) to generate interrupt from apic1. devices on the primary pci bus can write to irq pin assertion register fec0_0020h to generate an apic0 interrupt. devices/drivers on the pci-x segment have write access only on the apic1 irq pin assertion register. devices/drivers on the pci segment can access only apic0 registers. since the intel ? 6300ESB ich does not implement hub interface eoi special cycle, mch will translate eoi special cycle to a memory write cycle to eoi register at address fec0_0040h and pass it to the intel ? 6300ESB ich. this memory write cycle will be passed to both apic0 and apic1 internally. from cpu/mch point of view, it should always use address fec0xxxxh to access apic0 registers and address fec1xxxxh to access apic1 registers. apic1 will not respond to cpu/mcu?s access to address fec0xxxxh other than the eoi cycle stated above. apic1 also includes an xapic_en config bit. this bit must be set to enable the i/o (x) apic extension to the i/o apic. for apic1, this extension is always enabled. 17.1 apic1 configuration registers (d29:f5) note: registers that are not shown should be treated as reserved. see ?pci configuration map? on page 277 for details. . table 557. apic1 configuration map (d29:f5) (sheet 1 of 2) offset mnemonic register name default type 00-03h vid_did vendor id/device id 25ach/8086h ro 04-05h apic1cmd apic1 command register 0000h r/w 06-07h apic1sta apic1 device status register 0010h ro 08h rid revision id see note 1 ro 09-0bh cc class code 080020h ro 0c-0fh headtyp header type 00000000h ro 2c-2f ss subsystem identifiers 00000000h rwo 34h cap capabilities pointer 50h ro 3ch iline interrupt line 00h r/w 3dh ipin interrupt pin 00h ro 40-41h abar alternate base address register 8000h r/w notes: 1. refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register.
intel ? 6300ESB ich?17 intel ? 6300ESB i/o controller hub ds november 2007 632 order number: 300641-004us 17.1.1 offset 00 - 03h: vid_did?vendor/id register (apic1?d29:f5) 17.1.2 offset 04 - 05h: apic1cmd?apic1 command register (apic1?d29:f5) 44-47h mbar memory base register fec10000h ro 50-51h xid pci-x identifiers 0007h ro 54-57h xsr pci-x status 000100edh ro table 558. offset 00 - 03h: vid_did?vendor/id register (apic1?d29:f5) bits name description access 15:0 device id value this is a 16-bit value assigned to the apic1. did = 25ach 15:0 vendor id value this is a 16-bit value assigned to intel. intel vid = 8086h table 559. offset 04 - 05h: apic1cmd?apic1 command register (apic1? d29:f5) (sheet 1 of 2) bits name description access 15:9 reserved reserved. 8 serr_en: serr# enable serr# enable controls the enable for the do_serr special cycle on the hub interface. 0 = disable special cycle. 1 = enable special cycle. r/w 7 reserved reserved. table 557. apic1 configuration map (d29:f5) (sheet 2 of 2) offset mnemonic register name default type notes: 1. refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. device: 29 function: 5 offset: 00 - 03h attribute: read-only default value: 25ach-8086h size: 32-bit lockable: no power well: core device: 29 function: 5 offset: 04-05h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 633 17?intel ? 6300ESB ich 17.1.3 offset 06 - 07h: apic1sta?apic1 device status (apic1?d29:f5) 6 pere: parity error response enable 0 = no action is taken when detecting a parity error. 1 = the intel ? 6300ESB ich will take normal action when a parity error is detected. note: d30fo offset f4h, bit #2 must be set to a ?1? and d28fo offset f4h, bit #2 must be set to a ?1? in order for pere to have any effect. r/w 5:3 reserved reserved. 2 bme: bus master enable controls the i/o apic1?s ability to act as a master on hub interface when forwarding processor side bus interrupt messages. r/w 1 mse: memory space enable controls the i/o apic1?s response as a target to memory accesses that address the i/o apic1. r/w 0 reserved reserved. table 560. offset 06 - 07h: apic1sta?apic1 device status (apic1?d29:f5) bits name description access 15:1 1 reserved reserved. 10:9 dev_sts: devsel# timing status 00 = fast decode. note: these bits are set for fast decode ?00?, but a true device select does not exist, so they have no effect. ro 8:6 reserved reserved. 5 66mhz_cap: 66 mhz capable hardwired to 1. not 66 mhz capable. ro 4 capabilities list this bit is hardwired to ?1?, indicating the presence of a valid capabilities pointer at offset 34h. 3:0 reserved reserved. table 559. offset 04 - 05h: apic1cmd?apic1 command register (apic1? d29:f5) (sheet 2 of 2) bits name description access device: 29 function: 5 offset: 04-05h attribute: read/write default value: 0000h size: 16-bit lockable: no power well: core device: 29 function: 5 offset: 06 - 07h attribute: read-only default value: 0010h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?17 intel ? 6300ESB i/o controller hub ds november 2007 634 order number: 300641-004us 17.1.4 offset 08h: rid?revision id register (apic1? d29:f5) 17.1.5 offset 09 - 0bh: cc?class code register (apic1? d29:f5) table 561. offset 08h: rid?revision id register (apic1?d29:f5) bits name description access 7:0 revision id value refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. ro table 562. offset 09 - 0bh: cc?class code register (apic1?d29:f5) bits name description access 23:1 6 bcc: base class code the value of 08h indicates that this is a generic system peripheral. ro 15:8 scc: sub class code the value of 00h indicates that this generic peripheral is an interrupt controller. ro 7:0 pif: programming interface the value of 20h indicates that this interrupt peripheral is an i/oxapic. ro device: 29 function: 5 offset: 08h attribute: read-only default value: see bit description size: 8-bit device: 29 function: 5 offset: 09-0bh attribute: read-only default value: 080020h size: 24-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 635 17?intel ? 6300ESB ich 17.1.6 offset 0c - 0fh: headtyp?header type register (apic1?d29:f5) 17.1.7 offset 2c - 2fh: ss?apic1 subsystem identifiers (apic1?d29:f5) note: this register is initialized to logic ?0? by the assertion of pxpcirst#. this register may be written only once after pxpcirst# deassertion. table 563. offset 0c - 0fh: headtyp?header type register (apic1?d29:f5) bits name description access 31:2 4 reserved reserved. 23:1 6 header type this indicates that it is a type ?00? header (normal pci device) and that it is a single function device. ro 15:0 reserved reserved. table 564. offset 2c - 2fh: ss?apic1 subsystem identifiers (apic1?d29:f5) bits name description access 31:1 6 ssid: subsystem id write once register for subsystem id. rwo 15:0 ssvid: subsystem vendor id write once register for holding the subsystem vendor id. rwo device: 29 function: 5 offset: 0c - 0fh attribute: read-only default value: 00000000h size: 32-bit device: 29 function: 5 offset: 2c - 2fh attribute: read/write once default value: 0000000h size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?17 intel ? 6300ESB i/o controller hub ds november 2007 636 order number: 300641-004us 17.1.8 offset 34h: cap_ptr?apic1 capabilities pointer (apic1?d29:f5) 17.1.9 offset 3ch: iline?interrupt line (apic1? d29:f5) 17.1.10 offset 3dh: ipin?interrupt pin (apic1?d29:f5) table 565. offset 34h: cap_ptr?apic1 capabilities pointer (apic1?d29:f5) bits name description access 7:0 cap: capabilities pointer this register points to the starting offset (50h) of the i/o apic1 capabilities range. ro table 566. offset 3ch: iline?interrupt line (apic1?d29:f5) bits name description access 17:0 iline: interrupt line this data is not used by the intel ? 6300ESB ich. it is used as a scratchpad register to communicate to software the interrupt line that the inte rrupt pin is connected to. r/w table 567. offset 3dh: ipin?interrupt pin (apic1?d29:f5) bits name description access 7:0 ipin: interrupt pin the value of 00h indicates that i/o apic1 does not connect to pirq#. ro device: 29 function: 5 offset: 34h attribute: read-only default value: 50h size: 8-bit lockable: no power well: core device: 29 function: 5 offset: 3ch attribute: read/write default value: 00h size: 8-bit lockable: no power well: core device: 29 function: 5 offset: 3dh attribute: read-only default value: 00h size: 8-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 637 17?intel ? 6300ESB ich 17.1.11 offset 40 - 41h: abar?apic1 alternate base address register (apic1?d29:f5) note: this register contains an alternate base address in the legacy apic range. this range may coexist with the bar register range. this range is needed for oss that support the apic but do not yet support remapping the apic anywhere in the 4 gbyte address space. note: on downstream writes, only abar + offset 40h (eoi) is claimed. on upstream cycles, only abar + offset 20h are claimed. 17.1.12 offset 44 - 47h: mbar?apic1 memory base register (apic1?d29:f5) note: this register contains the apic1 base address for the memory space. table 568. offset 40 - 41h: abar?apic1 alternate base address register (apic1?d29:f5) bits name description access 15 en: enable when set, the range fecx_yz00 to fecx_yzff is enabled as an alternate access method to the ioxapic registers. bits ?xyz? are defined below. ro 14 bie: boot interrupt enable 0 = boot interrupt is enabled. 1 = boot interrupt is disabled. note: for details on the boot interrupt, see section 5.7.3, ?boot interrupt? . rw 13:1 2 reserved reserved. 11:8 base address [19:16] (xbad) these bits determine the high order bits of the i/o apic address map. when a memory address is recognized by the intel ? 6300ESB ich that matches fecx_yz00 or fecx_yz10, the intel ? 6300ESB ich will respond to the cycle and access the internal i/o apic1. 7:4 base address [15:12] (ybad) these bits determine the low order bits of the i/o apic address map. when a memory address is recognized by the intel ? 6300ESB ich that matches fecx_yz00 or fecx_yz10, the intel ? 6300ESB ich will respond to the cycle and access the internal i/o apic1. 3:0 base address [11:8] (zbad) these bits determine the low order bits of the i/o apic address map. when a memory address is recognized by the intel ? 6300ESB ich that matches fecx_yz00 or fecx_yz10, the intel ? 6300ESB ich will respond to the cycle and access the internal i/o apic1 device: 29 function: 5 offset: 40-41h attribute: read/write default value: 8000h size: 16-bit lockable: no power well: core
intel ? 6300ESB ich?17 intel ? 6300ESB i/o controller hub ds november 2007 638 order number: 300641-004us table 569. offset 44 - 47h: mbar?apic1 memory base register (apic1? d29:f5) bits name description access 31:1 2 addr: address these bits determine the base address of the i/o apic1. ro 11:4 reserved reserved. 3 pf: prefetchable indicates that the bar is not pre-fetchable. ro 2:1 loc: location '00' indicates that the address may be located anywhere in the 32-bit address space. ro 0 si: space indicator indicates that the bar is in memory space. ro device: 29 function: 5 offset: 44-47h attribute: read-only default value: fec10000h size: 32-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 639 17?intel ? 6300ESB ich 17.1.13 offset 50 - 51h: xid?pci-x identifiers register (apic1?d29:f5) 17.1.14 offset 52h: xsr?pci-x status register (apic1? d29:f5) table 570. offset 50 - 51h: xid?pci-x identifiers register (apic1?d29:f5) bits name description access 15:8 xnptr: next pointer points to the next capabilities list pointer (empty). ro 7:0 xcid: capability id capabilities id indicates pci-x (07h). ro table 571. offset 52h: xsr?pci-x status register (apic1?d29:f5) bits name description access 31:2 1 reserved reserved. 20 device complexity hardwired to logic ?0? to indicate that this is a simple device. ro 19 unexpected split completion this device will never see an unexpected split completion, as it never generates any master cycles besides posted writes for msi. ro 18 split completion discarded this device does not support split completion. ro 17 133 mhz capable hardwired to logic ?0? to indicate this device is not 133 mhz capable. ro 16 64-bit device hardwired to logic ?1? to indicate that this is a 64-bit device. ro 15:8 bus number indicates the bus number of the bus segment for this device. this value will match the primary bus number field from the attached bridge. ro 7:3 device number reflects the device number that has been hard-coded for the device. this number will be 1dh (29) for apic1. ro 2:0 function number reflects the function number for the device. ro device: 29 function: 5 offset: 50-51h attribute: read-only default value: 0007h size: 16-bit lockable: no power well: core device: 29 function: 5 offset: 52h attribute: read-only default value: 000300edh size: 32-bit lockable: no power well: core
intel ? 6300ESB ich?17 intel ? 6300ESB i/o controller hub ds november 2007 640 order number: 300641-004us 17.2 advanced interrupt controller (apic) there are two apics in the intel? 6300ESB ich: apic0 and apic1 (in device 29, function 5). apic0?s direct registers are assigned with base address fec0xxxxh; however, no external pci device may write to these registers. apic1?s direct registers are assigned with base address fec1xxxxh. to support legacy device/ drivers on external pci bus used with the intel ichx, apic1 has an alternate base address, fec0xxxxh. this means external pci devices may write to irq pin assertion register (either fec0_0020h or fec1_0020h) to generate interrupt from apic1. apic0 also includes an xapic_en config bit. this bit must be set to enable the i/o (x) apic extension to the i/o apic. for apic1, this extension is always enabled. 17.2.1 apic1 direct register map the apic is accessed through an indirect addressing scheme. two registers are visible by software for manipulation of most of the apic registers. these registers are mapped into memory space. the registers are shown in ta b l e 5 7 2 . table 573 lists the registers which may be accessed within the apic through the index register. when accessing these registers, accesses must be done a dword at a time. for example, software should never access byte 2 from the data register before accessing bytes 0 and 1. the hardware will not attempt to recover from a bad programming model in this case. 17.2.2 ind?index register note: the index register will select which apic indirect register to be manipulated by software. the selector values for the indirect registers are listed in table 573 . software will program this register to select the desired apic internal register. table 572. apic1 direct registers address register size type fec1_0000h index register 8 bits r/w fec1_0010h data register 32 bits r/w fec1_0020h irq pin assertion register 32 bits r/w fec1_0040h eoi register 32 bits r/w table 573. apic indirect registers index register size type 00 id 32 bits r/w 01 version 32 bits ro 02 arbitration id 32 bits ro 03 boot configuration 32 bits r/w 04-0f reserved ro 10 -11 redirection table 0 64 bits r/w 12 - 13 redirection table 1 64 bits r/w 3e-3f redirection table 23 64 bits r/w 40-ff reserved ro
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 641 17?intel ? 6300ESB ich 17.2.3 dat?data register note: this is a 32-bit register specifying the data to be read or written to the register pointed to by the index register. this register may only be accessed in dword quantities. 17.2.4 irqpa?irq pin assertion register the irq pin assertion register is present to provide a mechanism to scale the number of interrupt inputs into the i/o apic without increasing the number of dedicated input pins. when a device that supports this interrupt assertion protocol requires interrupt service, that device will issue a write to this register. bits 4:0 written to this register contain the irq number for this interrupt. the only valid values are 0-23. bits 31:5 are ignored. to provide for future expansion, peripherals should always write a value of 0 for bits 31:5. note: writes to this register are only allowed by the processor and by masters on the intel ? 6300ESB ich?s pci bus. writes by devices on pci buses above the intel ? 6300ESB ich (e.g., a pci segment on a p64h) are not supported. table 574. ind?index register bits name description access 7:0 apic index this is an 8-bit pointer into the i/o apic register table. r/w table 575. dat?data register bits name description access 7:0 apic data this is a 32-bit register for the data to be read or written to the apic indirect register pointed to by the index register. r/w device: 29 function: 5 memory address: fec0_0000h attribute: read/write default value: 00h size: 8-bit device: 29 function: 5 memory address: fec0_0010h attribute: read/write default value: 00000000h size: 32-bit
intel ? 6300ESB ich?17 intel ? 6300ESB i/o controller hub ds november 2007 642 order number: 300641-004us 17.2.5 eoir?eoi register the eoi register is present to provide a mechanism to maintain the level-triggered semantics for level-triggered interrupts issued on the parallel bus. when a write is issued to this register, the i/o apic will check the lower 8 bits written to this register and compare them with the vector field for each entry in the i/o redirection table. when a match is found, the remote_irr bit for that i/o redirection entry will be cleared. note: when there are multiple i/o redirection entries, assign the same vector for more than one interrupt input. each of those entries will have the remote_irr bit reset to ?0?. the interrupt that was prematurely reset will not be lost because if its input remained active when the remote_irr bit is cleared, the interrupt will be reissued and serviced at a later time. only bits 7:0 are actually used. bits 31:8 are ignored. table 576. irqpa?irq pin assertion register bits name description access 31:5 reserved reserved. to provide for future expansion, the processor should always write a value of ?0? to bits 31:5. 4:0 irq number bits 4:0 written to this register contain the irq number for this interrupt. the only valid values are 0-23. wo device: 29 function: 5 memory address: fec0_0020h attribute: write-only default value: n/a size: 32-bit table 577. eoir?eoi register bits name description access 31:8 reserved reserved. to provide for future expansion, the processor should always write a value of ?0? to bits 31:8. 7:0 end of interrupt (eoi) vector to be compared with vector field in the i/o redirection table when an eoi is issued. wo device: 29 function: 5 memory address: fec0_0040h attribute: write-only default value: n/a size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 643 17?intel ? 6300ESB ich 17.2.6 offset 00h: id?identification register note: the apic id serves as a physical name of the apic1. this register is reset to ?0? on power-up reset. 17.2.7 offset 01h: ver?version register note: each i/o apic contains a hardwired version register that identifies different implementations of apic and their versions. the maximum redirection entry information also is in this register to let software know how many interrupts are supported by this apic. table 578. offset 00h: id?identification register bits name description access 31:2 8 reserved reserved. 27:2 4 apic id software must program this value before using the apic. r/w 23:0 reserved reserved. table 579. offset 01h: ver?version register bits name description access 31:2 4 reserved reserved. 23:1 6 maximum redirection entries this is the entry number (0 being the lowest entry) of the highest entry in the redirection table. it is equal to the number of interrupt input pins minus one and is in the range 0 through 239. in the intel ? 6300ESB ich , this field is hardwired to 17h to indicate 24 interrupts. ro 15 prq this bit is set to ?1? to indicate that this version of the i/o apic implements the irq assertion register and allows pci devices to write to it to cause interrupts. ro 14:8 reserved reserved. 7:0 version this is a version number that identifies the implementation version. the version number assigned to the intel ? 6300ESB ich for the i/o (x) apic is 20h. ro device: 29 function: 5 offset: 00h attribute: read/write default value: 00000000h size: 32-bit device: 29 function: 5 offset: 01h attribute: read-only default value: 00178020h size: 32-bit
intel ? 6300ESB ich?17 intel ? 6300ESB i/o controller hub ds november 2007 644 order number: 300641-004us 17.2.8 offset 03h: boot_config?boot configuration register note: this register is used to control the interrupt delivery mechanism for the apic. 17.2.9 redirection table the redirection table has a dedicated entry for each interrupt input pin. the information in the redirection table is used to translate the interrupt manifestation on the corresponding interrupt pin into an apic message. note: the apic will respond to an edge-triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. once the interrupt is detected, a delivery status bit internally to the i/o apic is set. the state machine will step ahead and wait for an acknowledgment from the apic bus unit that the interrupt message was sent over the apic bus. only then will the i/o apic be able to recognize a new edge on that interrupt pin. that new edge will only result in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from ?0? to ?1?. (i.e., if the interrupt was not already pending at the destination.) table 580. offset 03h: boot_config?boot configuration register bits name description access 31:1 reserved reserved. 0 dt: d e liv er y ty p e hardwire to 1. interrupt delivery mechanism is always a processor system bus message. ro device: 29 function: 5 offset: 03h attribute: read-only default value: 00000001h size: 32-bit table 581. redirection table (sheet 1 of 3) bits name description access 63:5 6 destination when bit 11 of this entry is 0 [physical], bits [59:56] specify an apic id. in this case, bits 63:59 should be programmed by software to 0. when bit 11 of this entry is ?1? [logical], bits [63:56] specify the logical destination address of a set of processors. r/w 55:4 8 extended destination id (edid) these bits are only sent to a local apic when in processor system bus mode. they become bits [11:4] of the address. 47:1 8 reserved reserved. software should program these bits to 0. 17 disable flushing (dflsh) this bit is maintained for any potential software compatibility, but the intel ? 6300ESB ich performs no flushing action, regardless of the setting of this bit. device: 29 function: 5 offset: 10h-11h (vector 0) through 3e-3fh (vector 23) attribute: read/write default value: bit 16-1, bits[15:12]=0. all other bits undefined size: 64 bits each, accessed as two 32 bit q uantities
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 645 17?intel ? 6300ESB ich 16 mask 0 = not masked: an edge or level on this interrupt pin results in the delivery of the interrupt to the destination. 1 = masked: interrupts are not delivered nor held pending. setting this bit after the interrupt is accepted by a local apic has no effect on that interrupt. this behavior is identical to the device withdrawing the interrupt before it is posted to the processor. it is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local apic unit but before the interrupt is dispensed to the processor. r/w 15 trigger mode this field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = edge triggered. 1 = level triggered. r/w 14 remote irr this bit is used for level-triggered interrupts in fixed or lowest priority delivery modes only; its meaning is undefined for edge triggered interrupts. for level-triggered interrupts, this bit is set if the i/o apic successfully sends the level interrupt message. remote irr bit is reset when an eoi message is received that matches the interrupt vector in this entry. this bit is never set for smi, nmi, init, or extint delivery modes. r/w 13 interrupt input pin polarity this bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = active high. 1 = active low. r/w 12 delivery status this field contains the current status of the delivery of this interrupt. writes to this bit have no effect. 0 = idle. no activity for this interrupt. 1 = pending. interrupt has been injected, but delivery is held up due to the apic bus being busy or the inability of the receiving apic unit to accept the interrupt at this time. ro 11 destination mode this field determines the interpretation of the destination field. 0 = physical. destination apic id is identified by bits [59:56]. 1 = logical. destinations are identified by matching bit [63:56] with the logical destination in the destination format register and logical destination register in each local apic. r/w table 581. redirection table (sheet 2 of 3) bits name description access device: 29 function: 5 offset: 10h-11h (vector 0) through 3e-3fh (vector 23) attribute: read/write default value: bit 16-1, bits[15:12]=0. all ot h e r b i ts u n de fin ed size: 64 bits each, accessed as two 32 bit qua n t i t i es
intel ? 6300ESB ich?17 intel ? 6300ESB i/o controller hub ds november 2007 646 order number: 300641-004us 10:8 delivery mode this field specifies how the apics listed in the destination field should act upon reception of this signal. certain delivery modes will only operate as intended when used in conjunction with a specific trigger mode. these encodings are listed in the note below: r/w 7:0 vector this field contains the interrupt vector for this interrupt. values range between 10h and feh. r/w note: delivery mode encoding: 000 = fixed. deliver the signal on the intr signal of all processor cores listed in the destination. trigger mode can be edge or level. 001 = lowest priority. deliver the signal on the intr signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. trigger mode can be edge or level. 010 = smi. this delivery mode is not supported. 011 = reserved. 100 = nmi. this delivery mode is not supported. 101 = init. this delivery mode is not supported. 110 = reserved 111 = extint. deliver the signal to the intr signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259a compatible interrupt controller. the inta cycle that corresponds to this extint delivery will be routed to the external controller that is expected to supply the vector. requires the interrupt to be programmed as edge triggered. the remote irr bit is never set if programmed for extint level-triggered operation; as a result a continuous stream of interrupts will be generated as long as the intr input is asserted. table 581. redirection table (sheet 3 of 3) bits name description access device: 29 function: 5 offset: 10h-11h (vector 0) through 3e-3fh (vector 23) attribute: read/write default value: bit 16-1, bits[15:12]=0. all ot h e r b i ts u n de fin ed size: 64 bits each, accessed as two 32 bit qua n t i t i es
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 647 18?intel ? 6300ESB ich pci-x overview (d28:f0) 18 note: since the intel ? 6300ESB ich supports a pci interface and a pci-x interface, the notation pci-x will be used to refer to the pci-x interface. since the pci-x interface can support the pci-x protocol as well as the pci protocol, the pci-x terminology is intended to refer to the interface being described and not to the protocol. 18.1 i/o window addressing this section describes the i/o window that may be set up in the bridge. refer to section 18.3, ?vga addressing? to see how i/o cycles in the vga range are handled. the register bits listed below also modify the response by the intel ? 6300ESB ich to i/ o transactions: ? i/o base and limit registers ? i/o enable bit in the command register ? master enable bit in the command register ? enable 1k granularity in the intel ? 6300ESB ich configuration register to enable outbound i/o transactions, the i/o enable bit must be set in the command register in the intel ? 6300ESB ich configuration space (bit ?0? at offset 04-05h). when the i/o enable bit is not set, all i/o transactions initiated on the hub interface receive a master abort completion. no inbound i/o transactions may cross the bridge and are therefore master aborted. the intel ? 6300ESB ich implements one set of i/o base and limit address registers in configuration space that define an i/o address range for the bridge. hub interface i/o transactions with addresses that fall inside the range defined by the i/o base and limit registers are forwarded to pci-x, and pci-x i/o transactions with addresses that fall outside this range are master aborted. setting the base address to a value greater than that of the limit address turns off the i/o range. when the i/o range is turned off, no i/o transactions are forwarded to pci even when the i/o enable bit is set. the i/o range has a minimum granularity of 4 kbytes and is aligned on a 4 kbyte boundary. the maximum i/o range is 64 kbytes. this range may be lowered to 1k granularity by setting the en1k bit in the intel ? 6300ESB ich configuration register at offset 40h. the base register consists of an 8-bit field at configuration address 1ch, and a 16-bit field at address 30h. the top four bits of the 8-bit field define bits [15:12] of the i/o base address. the bottom four bits read only as 0h to indicate that the intel ? 6300ESB ich supports 16-bit i/o addressing. bits [11:0] of the base address are assumed to be ?0?, which naturally aligns the base address to a 4 kbyte boundary. the i/o base upper 16 bits register at offset 30h is reserved. after chip reset, the value of the i/o base address is initialized to 0000h. the i/o limit register consists of an 8-bit field at offset 1dh and a 16-bit field at offset 32h. the top four bits of the 8-bit field define bits [15:12] of the i/o limit address. the bottom four bits read only as 0h to indicate that 16-bit i/o addressing is supported. bits [11:0] of the limit address are assumed to be fffh, which naturally aligns the limit address to the top of a 4 kbyte i/o address block. the 16 bits contained in the i/o limit upper 16 bits register at offset 32h are reserved. after chip reset, the value of the i/o limit address is reset to 0fffh.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 648 order number: 300641-004us note: when the en1k bit is set in the intel ? 6300ESB ich configuration register, the base and limit registers are changed so that the top six bits of the 8-bit field define bits [15:10] of the i/o base/limit address, and the bottom two bits read only as 0h to indicate support for 16-bit i/o addressing. bits [9:0] are assumed to be ?0? for the base register and ?1? for the limit register, which naturally aligns the address to a 1 kbyte boundary. 18.2 memory window addressing this section describes the memory windows that may be set up in the bridge. refer to section 18.2.2, ?prefetchable memory base and limit address registers, upper 32-bit registers? to see how memory cycles in the vga range are handled. ? memory-mapped i/o base and limit registers ? prefetchable memory base and limit registers ? prefetchable memory base and limit upper 32 bits register ? memory enable bit in the command register ? master enable bit in the command register to enable outbound memory transactions, the memory space enable bit in the command register must be set (bit 1 of offset 04-05h). to enable inbound memory transactions, the master enable bit in the command register must be set (bit 2 of offset 04-05h). the intel ? 6300ESB ich does not prefetch data from pci devices. the intel ? 6300ESB ich supports 64 bits of addressing (dac cycles) on both interfaces. 18.2.1 memory base and limit address registers the memory base address and memory limit address registers define an address range that the intel ? 6300ESB ich uses to determine when to forward memory commands. the intel ? 6300ESB ich forwards a memory transaction from the hub interface to pci- x when the address falls within the range, and forwards it from pci-x to the hub interface when the address is outside the range, provided that they do not fall into the prefetchable memory range (see section 18.2.2, ?prefetchable memory base and limit address registers, upper 32-bit registers? ). this memory range supports 32-bit addressing only (addresses 4 gbytes). it has a granularity and alignment of 1 mbyte. this range is defined by a 16-bit base address register at offset 20h in configuration space and a 16-bit limit address register at offset 22h. the top 12 bits of each of these registers correspond to bits [31:20] of the memory address. the low four bits are hardwired to ?0?. the low 20 bits of the base address are assumed to be all ?0?, which results in a natural alignment to a 1 mbyte boundary. the low 20 bits of the limit address are assumed to be all ?1?s, which results in an alignment to the top of a 1 mbyte block. setting the base to a value greater than that of the limit turns off the memory range. 18.2.2 prefetchable memory base and limit address registers, upper 32-bit registers the prefetchable memory base and address registers, along with their upper 32-bit counterparts, define an additional address range that the intel ? 6300ESB ich uses to forward accesses. the intel ? 6300ESB ich forwards a memory transaction from the hub interface to pci-x when the address falls within the range, and forwards
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 649 18?intel ? 6300ESB ich transactions from pci-x to the hub interface when the address is outside the range and do not fall into the regular memory range (see section 18.2.1, ?memory base and limit address registers? ). this memory range supports 64-bit addressing and has a granularity and alignment of 1 mbyte. this lower 32 bits of the range are defined by a 16-bit base register at offset 24h in configuration space and a 16-bit limit register at offset 26h. the top 12 bits of each of these registers correspond to bits [31:20] of the memory address. the low four bits are hardwired to 1h, indicating 64-bit address support. the low 20 bits of the base address are assumed to be all ?0?s, which results in a natural alignment to a 1 mbyte boundary. the low 20 bits of the limit address are assumed to be all ?1?s, which results in an alignment to the top of a 1 mbyte block. the upper 32 bits of the range are defined by a 32-bit base register at offset 28h in configuration space and a 32-bit limit register at offset 2ch. setting the entire base (with upper 32 bits) to a value greater than that of the limit turns off the memory range. 18.3 vga addressing when a vga-compatible device exists behind an intel ? 6300ESB ich bridge, the vga enable bit in the bridge control register is set (offset 3 at 3e-3fh). when set, the intel ? 6300ESB ich forwards all transactions addressing the vga frame buffer memory and vga i/o registers from the hub interface to pci-x, regardless of the values of the intel ? 6300ESB ich base and limit address registers. when set, the intel ? 6300ESB ich does not forward vga frame buffer memory accesses to the hub interface regardless of the values of the memory address ranges. however, the i/o enable and memory enable bit in the command register must still be set. when cleared, the intel ? 6300ESB ich forwards transactions addressing the vga frame buffer memory and vga i/o registers from the hub interface to pci-x when the defined memory address ranges enable forwarding. when cleared, accesses to the vga frame buffer memory are forwarded from pci-x to the hub interface when the defined memory address ranges enable forwarding. however, the master enable bit must still be set. the vga i/ o addresses are never forwarded to the hub interface. the vga frame buffer consists of the following memory address range: 000a 0000h? 00b ffffh. the vga i/o addresses consist of the i/o addresses 3b0h?3bbh and 3c0h?3dfh. these i/o addresses are aliased every 1 kbyte throughout the first 64 kbyte of i/o space. this means that address bits [9:0] (3b0h-3bbh and 3c0h-3dfh) are decoded, [15:10] are not decoded and may be any value, and address bits [31:16] must be all ?0?s.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 650 order number: 300641-004us 18.4 configuration addressing figure 30 shows how the intel ? 6300ESB ich appears to configuration software. as seen in figure 30 , the sm bus controller does not appear to software. this function does not have a space visible to software. configuration cycles on the hub interface have the same address format, with the bus number, device number, function number and register number present in the address. refer to the hub interface specification for details of the address. 18.4.1 type 0 accesses to the intel ? 6300ESB ich the configuration space of the bridge in the intel ? 6300ESB ich is accessed by a type 0 configuration transaction on the hub interface. the bridge configuration space (the intel ? 6300ESB ich) responds to a type 0 configuration transaction when the following conditions are met by the hub interface address: ? the bus command is a configuration read or configuration write transaction. ? low 2 address bits ad[1:0] must be 00b. ? the device number matches one of the intel ? 6300ESB ich devices (28). 18.4.2 type 1 to type 0 translation the intel ? 6300ESB ich performs a type 1 to type 0 translation when the type 1 transaction is generated on the hub interface and is intended for a device attached directly to the secondary bus. the intel ? 6300ESB ich must convert the configuration command to a type 0 format so that the secondary bus device may respond to it. this figure 30. intel ? 6300ESB i/o controller hub appearance to software table 582. configuration addressing function hub interface id pci-x bus pci-x dev pci-x func pci/pci-xbus 6 0 (hub interface) 28 h 0
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 651 18?intel ? 6300ESB ich translation is done for cycles that originate on the hub interface and target pci/pci-x. the intel ? 6300ESB ich translates a type 1 configuration transaction into a type 0 transaction under the following conditions: ? the bus command is a configuration read or write transaction. ? the low 2 address bits on ad [1:0] are 01b. ? the bus number in address field ad [23:16] is equal to the value in the secondary bus number register in the intel ? 6300ESB ich configuration space. the resulting type 0 address to be driven on pci-x is shown in figure 31 . device numbers are decoded to generate a single ?1? in address bits 31:16. when the device number is greater than 16, then all bits are ?0?. 18.4.3 type 1 to type 1 forwarding the intel ? 6300ESB ich forwards a type 1 configuration cycle unchanged to the pci-x bus under the following conditions. ? the bus command is a configuration read or write transaction. ? the low two address bits are equal to 01b. ? the bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. type 1 to type 1 forwarding is only done for cycles from the hub interface to pci-x. 18.4.4 type 1 to special cycle forwarding the intel ? 6300ESB ich translates a type 1 configuration write transaction on the hub interface into a special cycle on pci-x, but does not translate a type 1 configuration access on pci-x to a special cycle on the hub interface. a cycle to be translated has the following attributes in the address: ? the low two address bits on ad[1:0] are equal to 01b. ? the device number in address bits ad[15:11] is equal to 11111b. ? the function number in address bits ad[10:8] is equal to 111b. ? the register number in address bits ad[7:2] is equal to 000000b. ? the bus number is equal to the value in the secondary bus number register in configuration space. ? the bus command is a configuration write command. the address and data are forwarded unchanged. devices ignore the address and decode only the bus command. the data phase contains the special cycle message. the transaction does a master abort but results in a normal completion on the opposite bus figure 31. type ?1? to type ?0? translation reserved '0' dev id only one '1' fnc fnc 0000 register register 01 00 31 15 2 7 10 11 16 1 0 hl address pci address
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 652 order number: 300641-004us (normal completion status on the hub interface, trdy# on pci-x). when more than one data transfer is requested, the intel ? 6300ESB ich responds with a target disconnect operation during the first data phase. 18.5 transaction ordering 18.5.1 comparison of rules vs. a pci ? pci bridge when a pci segment is in pci (pci-x) mode, the intel ? 6300ESB ich follows the producer-consumer model of a pci ? pci bridge. tab le 58 3 is taken from appendix e of the pci specification, rev 2.2 for pci, and section 8.4.4 of the pci-x addendum for pci-x . the shaded entries represent differences from that table, and an explanation of the differences: 18.5.2 other notes ordering relationships are established for the following classes of transactions crossing the intel ? 6300ESB ich: ? the intel ? 6300ESB ich does not combine separate write transactions into a single write transaction. ? the intel ? 6300ESB ich does not merge bytes on separate write transactions to the same dword address. ? the intel ? 6300ESB ich does not collapse sequential write transactions to the same address into a single write transaction ? the pci local bus specification does not permit this. table 583. comparison of rules vs. a pci ? pci bridge row pass col? posted write delayed (split) read request delayed (split) write request 3 delayed (split) read completion delayed (split) write completion 3 posted write no yes yes yes yes delayed (split) read request no yes 1 no 2 yes 1 no 2 no 2 yes 2 yes yes 2 delayed (split) write request no no 2 no 2 no 3 yes 2 no 3 yes 2 delayed (split) read completion no yes yes no 2 yes 2 no 2 yes 2 delayed (split) write completion no 2 yes yes no 2 yes 2 no 2 yes 2 notes: 1. subsequent requests only (prefetches). all inbound initial requests are in order. 2. in a bridge, these are allowed to be yes/no. 3. in a bridge, these are allowed to be yes/no. these particular entries are ?no? because the intel ? 6300ESB ich does not accept inbound write requests that are not posted (i/o writes, configuration writes).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 653 18?intel ? 6300ESB ich 18.6 device 28 ? hub interface to pci-x bridge 18.6.1 configuration space registers 18.6.1.1 register summary table 584. configuration space register summary (sheet 1 of 2) start end symbol full name default 00 03 id identifiers 25ae8086h 04 05 cmd command 0000h 06 07 psts primary status 0030h 08 08 rid revision id see note: 09 0b cc class code 060400h 0c 0c cls cache line size 00h 0d 0d plt primary latency timer 00h 0e 0e htype header type 01h 18 1a bnum bus numbers 000000h 1b 1b slt secondary latency timer 00h 1c 1d iobl i/o base and limit 0000h 1e 1f ssts secondary status 02a0h 20 23 mbl memory base and limit 00000000h 24 27 pmbl prefetchable memory base and limit 00010001h 28 2b pmbu32 prefetchable memory base upper 32 bits 00000000h 2c 2f pmlu32 prefetchable memory limit upper 32 bits 00000000h 30 33 ioblu16 i/o base and limit upper 16 bits 00000000h 34 34 capp capabilities list pointer 50h 3c 3d intr interrupt information 0000h 3e 3f bctrl bridge control 0000h 40 41 cnf intel ? 6300ESB ich configuration 000ssh 42 42 mtt multi-transaction timer 00h 44 47 strp pci strap status 00h 50 50 px_capid pci-x capabilities identifier 07h 51 51 px_nxtp next item pointer 00h 52 53 px_ssts pci-x secondary status 0001h 54 57 px_bsts pci-x bridge status 000100d0h 58 5b px_ustc pci-x upstream split transaction control 0000ffffh note: refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to- date value of the revision id register.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 654 order number: 300641-004us 18.6.1.2 offset 00: id?identifiers note: contains the vendor and device identifiers for software. 5c 5f px_dstc pci-x downstream split transaction control 0000ffffh 60 9f reserved e0 e3 acnf additional intel ? 6300ESB ich configuration 0000000fh e4 e5 pcr pci compensation register 0002h f0 f3 hccr hub interface command/control register 00000000h f4 f7 reserved f8 f9 pc33 prefetch control ? 33 mhz 1111h fa fb pc66 prefetch control ? 66 mhz 3121h fc ff reserved 7b7bbfffh table 585. offset 00: id?identifiers bits name description reset value access 31:1 6 device id (did) indicates what device number was assigned by the pci sig. 25aeh ro 15:0 0 vendor id (vid) 16-bit field which indicates that intel is the vendor. 8086h ro table 584. configuration space register summary (sheet 2 of 2) start end symbol full name default note: refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to- date value of the revision id register. device 28 function 0 offset 00 attribute: read-only size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 655 18?intel ? 6300ESB ich 18.6.1.3 offset 04: cmd?command this controls how the device behaves on the primary interface and is the same as all other devices, with the exception of the vga palette snoop bit. as this component is a bridge, additional command information is located in a separate register called ?bridge control? located at offset 3e. table 586. offset 04: cmd?command (sheet 1 of 2) bits name description reset value access 15:1 0 reserved reserved. 00h ro 09 fast back- to-back enable (fbe) this bit has no meaning on the hub interface. it is hardwired to '0'. 0ro 08 serr# enable (see) controls the enable for assertion of serr# (via nmi/smi#) when the sse bit (d28:f0:offset 06h, bit 14) is set. see section 5.1.4 for more details on this bit. 0 = serr# disabled 1 = serr# enabled 0r/w 07 wait cycle control (wcc) reserved. 0 ro 06 parity error response enable (pere) controls the intel ? 6300ESB ich's response when a parity error is detected on the hub interface. 0 = the intel ? 6300ESB ich ignores these errors on the hub interface. 1 = the intel ? 6300ESB ich reports these errors on the hub interface and sets the dpd bit in the status register. note: the hub interface parity unsupported bit (d30:f0:40h:bit 20) must be cleared for the per bit to have any effect. 0r/w 05 vga palette snoop enable (vga_pse) reserved. 0 ro 04 memory write and invalidate enable (mwie) the intel ? 6300ESB ich does not generate memory write and invalidate transactions, as the hub interface does not have a corresponding transfer type. 0ro 03 special cycle enable (sce) reserved. 0 ro device 28 function 0 offset 04 attribute: read/write size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 656 order number: 300641-004us 18.6.1.4 offset 06: psts?primary status note: for the writable bits in this register, writing a ?1? clears the bit. writing a ?0? has no effect. note: raserr# will be asserted based on activity of bits 15:11, 8. 02 bus master enable (bme) controls the ability of the intel ? 6300ESB ich to act as a master on the hub interface when forwarding memory transactions from pci-x. when '0': the intel ? 6300ESB ich does not respond to any memory transactions on the pci-x interface that target hub interface. 0r/w 01 memory space enable (mse) controls the ability of the intel ? 6300ESB ich to respond as a target to memory accesses on the hub interface that address a device behind the intel ? 6300ESB ich. 0r/w 0 i/o space enable (iose) controls the ability of the intel ? 6300ESB ich to respond as a target to i/o transactions on the primary interface that address a device that resides behind the intel ? 6300ESB ich. 0r/w table 586. offset 04: cmd?command (sheet 2 of 2) bits name description reset value access device 28 function 0 offset 04 attribute: read/write size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 657 18?intel ? 6300ESB ich table 587. offset 06: psts?primary status bits name description reset value access 15 detected parity error (dpe) when set to 1, this bit indicates that the intel ? 6300ESB ich detected an address parity, data parity, error on the hub interface. this bit gets set even when the parity error response bit (bit 6 of the command register) is not set. note that each bridge sets this bit, regardless of address. note: the hub interface parity unsupported bit (d30:f0:40h:bit 20) must be cleared for the per bit to have any effect. 0r/wc 14 signaled system error (sse) this bit is set to ?1? when the serr# is reported to the hub interface through the nmi/smi# assertion when enabled. 0r/wc 13 received master abort (rma) this bit is set whenever the intel ? 6300ESB ich is acting as master on the hub interface and receives a completion packet with master abort status. 0r/wc 12 received ta r g e t abort (rta) this bit is set whenever the intel ? 6300ESB ich is acting as master on the hub interface and receives a completion packet with target abort status. 0r/wc 11 signaled ta r g e t abort (sta) this bit is set whenever the intel ? 6300ESB ich generates a completion packet with target abort status. 0r/wc 10:0 9 devsel# timing (dvt) these bits have no meaning on the hub interface. fast decode timing is reported. 00 ro 08 data parity error detected (dpd) this bit is set when the intel ? 6300ESB ich receives a completion packet from the hub interface from a previous request and detects a parity error, and the parity error response bit in the command register (offset 04h, bit 6) is set. 0r/wc 07 fast back- to-back capable (fbc) this bit has no meaning on the hub interface. 0 ro 06 reserved reserved. 0 ro 05 66 mhz capable (c66) this bit has no meaning on the hub interface but is set to be true in case of any software dependencies on bandwidth calculations. 1ro 04 capabil- ities list enable (cape) indicates that the intel ? 6300ESB ich contains the capabilities pointer in the bridge. offset 34h indicates the offset for the first entry in the linked list of capabilities. 1ro 03:0 reserved reserved. 0h ro device 28 function 0 offset 06 attribute: read/write clear size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 658 order number: 300641-004us 18.6.1.5 offset 08: rid?revision id table 588. offset 08: rid?revision id bits name description reset value access 07:0 revision id (rid) refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. 00h ro device 28 function 0 offset 08 attribute: read-only size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 659 18?intel ? 6300ESB ich 18.6.1.6 offset 09: cc?class code note: this contains the class code, sub class code, and programming interface for the device. 18.6.1.7 offset 0c: cls?cache line size note: this indicates the cache line size of the system. table 589. offset 09: cc?class code bits name description reset value access 23:1 6 base class code (bcc) the value of 06h indicates that this is a bridge device. 06h ro 15:0 8 sub class code (scc) 8-bit value that indicates this is of type pci-pci bridge. 04h ro 07:0 programmi ng interface (pif) indicates that this is standard (non-subtractive) pci-pci bridge. 00h ro table 590. offset 0c: cls?cache line size bits name description reset value access 07:0 cache line size (cls) the value in this register is used by the intel ? 6300ESB ich to determine the size of packets on the hub interface. this read/write register specifies the system cache line size in units of dwords. when the value is ?08h?, represents a 32- byte line (8 dwords). a value of ?10h? represents a 64-byte line, and a value of ?20h? represents a 128-byte line. any value outside this range defaults to a 64-byte line. when the intel ? 6300ESB ich is creating read and write requests to the hub interface, this value is used to partition the requests such that multiple snoops for the same line are avoided in the memory subsystem. 00h r/w device 28 function 0 offset 09 attribute: read-only size: 24-bit device 28 function 0 offset 0c attribute: read/write size: 8-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 660 order number: 300641-004us 18.6.1.8 offset 0d: plt?primary latency timer note: this register does not apply to hub interface and is maintained as r/w for software compatibility. 18.6.1.9 offset 0e: htype?header type note: this register determines how the rest of the configuration space is laid out. table 591. offset 0d: plt?primary latency timer bits name description reset value access 07:0 3 time value (tv) read/write for software compatibility only. 00h r/w 02:0 reserved reserved. 000 ro table 592. offset 0e: htype?header type bits name description reset value access 07 multi- function device (mfd) reserved as ?0? to indicate the bridge is a single function device. 0ro 06:0 header ty pe (htype) defines the layout of addresses 10h through 3fh in configuration space. reads as ?01h? to indicate that the register layout conforms to the standard pci-to-pci bridge layout. 01h ro device 28 function 0 offset 0d attribute: read/write size: 8-bit device 28 function 0 offset 0e attribute: read-only size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 661 18?intel ? 6300ESB ich 18.6.1.10offset 18: bnum?bus numbers note: this contains the primary, secondary, and maximum subordinate bus number registers. 18.6.1.11offset 1b: slt?secondary latency timer note: this timer controls the amount of time that the intel ? 6300ESB ich continues to burst data on its secondary interface. the counter starts counting down from the assertion of pxframe#. when the grant is removed, the expiration of this counter results in the deassertion of pxframe#. when the grant has not been removed, the intel ? 6300ESB ich may continue ownership of the bus. the secondary latency timer's default value should be 64 in pci-x mode (section 8.6.1 of the pci-x 1.0 specification ). table 593. offset 18: bnum?bus numbers bits name description reset value access 23:1 6 subordinat e bus number (sbbn) indicates the highest pci bus number below this bridge. any type one configuration cycle on the hub interface whose bus number is greater than the secondary bus number and less than or equal to the subordinate bus number is run as a type one configuration cycle on the pci bus. 00h r/w 15:0 8 secondary bus number (scbn) indicates the bus number of pci to which the secondary interface is connected. any type one configuration cycle matching this bus number is translated to a type 0 configuration cycle and run on the pci bus. 00h r/w 07:0 0 primary bus number (pbn) indicates the bus number of the hub interface. any type 1 configuration cycle with a bus number less than this number is not accepted by this portion of the intel ? 6300ESB ich (i.e., it still may match the other bridge). 00h r/w table 594. offset 1b: slt?secondary latency timer bits name description reset value access 07:0 3 secondary latency timer (tv) a five-bit value that indicates the number of pci clocks, in 8- clock increments, that the intel ? 6300ESB ich remains as a master of the pci bus when another master is requesting use of the pci bus. 00h r/w 02:0 0 reserved reserved. 000 ro device 28 function 0 offset 18 attribute: read/write size: 24-bit device 28 function 0 offset 1b attribute: read/write size: 8-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 662 order number: 300641-004us 18.6.1.12offset 1c: iobl?i/o base and limit note: defines the base and limit, aligned to a 4 kbyte boundary, of the i/o area of the bridge. accesses from the hub interface that are within the ranges specified in this register are sent to pci-x when the i/o space enable bit is set. note: accesses from pci-x that are outside the ranges specified result in a master abort. table 595. offset 1c: iobl?i/o base and limit bits name description reset value access 15:1 2 i/o limit address bits [15:12] (iola) defines the top address of an address range to determine when to forward i/o transactions from one interface to the other. these bits correspond to address lines 15:12 for 4 kbyte alignment. bits 11:0 are assumed to be fffh. 0h r/w 11:1 0 i/o limit address bits [11:10] (iola1k) when the en1k bit is set in the intel ? 6300ESB ich configuration register (cnf), these bits become read/write and are compared with i/o address bits 11:10 to determine the 1k limit address. when the en1k bit is cleared, this field becomes read only . 00 r/w 09:0 8 i/o limit addressing capability (iolc) this is hard-wired to 0h, indicating support for only 16-bit i/o addressing. 0h ro 07:0 4 i/o base address bits [15:12] (ioba) defines the bottom address of an address range to determine when to forward i/o transactions from one interface to the other. these bits correspond to address lines 15:12 for 4 kbyte alignment. bits 11:0 are assumed to be 000h. 0h r/w 03:0 2 i/o base address bits [11:10] (ioba1k) when the en1k bit is set in the intel ? 6300ESB ich configuration register (cnf), these bits become read/write and are compared with i/o address bits 11:10 to determine the 1k base address. when the en1k bit is cleared, this field becomes read only . 00 r/w 01:0 0 i/o base addressing capability (iobc) this is hard-wired to 0h, indicating support for only 16-bit i/o addressing. 0h ro device 28 function 0 offset 1c attribute: read/write size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 663 18?intel ? 6300ESB ich 18.6.1.13offset 1e: ssts?secondary status note: for the writable bits in this register, writing a ?1? clears the bit. writing a ?0? to the bit has no effect. note: raserr# will be asserted based on activity of bits 15:11, 8. table 596. offset 1e: ssts?secondary status (sheet 1 of 2) bits name description reset value access 15 detected parity error (dpe) this bit is set to a ?1? whenever the intel ? 6300ESB ich detects a address or data parity error on the pci-x bus. this bit gets set even when the parity error response bit (bit ?0? of offset 3e-3f) is not set. 0r/wc 14 received system error (rse) the intel ? 6300ESB ich sets this bit when a serr# assertion is received on pci-x. 0r/wc 13 received master abort (rma) this bit is set whenever the intel ? 6300ESB ich is acting as an initiator on the pci-x bus and the cycle is master-aborted. for hub interface packets that have completion required, this should also cause a target abort completion status to be returned and set the signaled target abort bit in the primary status register. 0r/wc 12 received ta r g e t abort (rta) this bit is set whenever the intel ? 6300ESB ich is acting as an initiator on pci-x and a cycle is target-aborted on pci-x. for ?completion required? hub interface packets, this event should force a completion status of ?target abort? on the hub interface and set the signaled target abort in the primary status register. 0r/wc 11 signaled ta r g e t abort (sta) this bit is set to ?1? when the intel ? 6300ESB ich is acting as a target on the pci-x bus and signals a target abort. 0r/wc 10:9 devsel# timing (dvt) indicates that the intel ? 6300ESB ich responds in medium decode time to all cycles targeting the hub interface. 01 ro 8 data parity error detected (dpd) the intel ? 6300ESB ich sets this bit when all of the following are true: ?the intel ? 6300ESB ich is the initiator on pci-x. ? perr# is detected asserted or a parity error is detected internally. ? the parity error response enable bit in the bridge control register (bit 0, offset 3eh) is set. 0r/wc 7 fast back- to-back capable (fbc) indicates that the secondary interface of the intel ? 6300ESB ich may receive fast back-to-back cycles. 1ro 6 reserved reserved. 0 ro device 28 function 0 offset 1e attribute: read/write clear size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 664 order number: 300641-004us 18.6.1.14offset 20: mbl?memory base and limit note: defines the base and limit, aligned to a 1 mbyte boundary, of the memory area of the bridge. accesses from the hub interface that are within the ranges specified in this register are sent to pci-x when the memory space enable bit is set. note: accesses from pci-x that are outside the ranges specified are forwarded to the hub interface when the bus master enable bit is set. 5 66 mhz capable (c66) indicates the secondary interface of the bridge is 66 mhz capable. 1ro 4 perr# assertion detect this bit is set by hardware whenever the perr# pin is asserted on the rising edge of pci-x clock. this includes cases in which the chipset is the agent driving perr#. it remains asserted until cleared by software writing a ?1? to this location. when enabled by the perr#-to-serr# enable bit (in the bridge control register), a ?1? in this bit can generate an internal serr# and be a source for the nmi logic. r/wc 3:0 reserved reserved. 00h ro table 597. offset 20: mbl?memory base and limit bits name description reset value access 31:2 0 memory limit (ml) these bits are compared with bits 31:20 of the incoming address to determine the upper 1 mbyte aligned value (exclusive) of the range. the incoming address must be less than or equal to this value. 000h r/w 19:1 6 reserved reserved. 0h ro 15:0 4 memory base (mb) these bits are compared with bits 31:20 of the incoming address to determine the lower 1 mbyte aligned value (inclusive) of the range. the incoming address must be greater than or equal to this value. 000h r/w 03:0 0 reserved reserved. 0h ro table 596. offset 1e: ssts?secondary status (sheet 2 of 2) bits name description reset value access device 28 function 0 offset 1e attribute: read/write clear size: 16-bit device 28 function 0 offset 20 attribute: read/write size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 665 18?intel ? 6300ESB ich 18.6.1.15offset 24: pmbl?prefetchable memory base and limit note: defines the base and limit, aligned to a 1 mbyte boundary, of the prefetchable memory area of the bridge. accesses from the hub interface that are within the ranges specified in this register are sent to pci-x when the memory space enable bit is set. note: accesses from pci-x that are outside the ranges specified are forwarded to the hub interface when the bus master enable bit is set. 18.6.1.16offset 28: pmbu32?prefetchable memory base upper 32 bits note: this defines the upper 32 bits of the prefetchable address base register. table 598. offset 24: pmbl?prefetchable memory base and limit bits name description reset value access 31:2 0 prefetchabl e memory limit (pml) these bits are compared with bits 31:20 of the incoming address to determine the upper 1 mbyte aligned value (exclusive) of the range. the incoming address must be less than this value. 000h r/w 19:1 6 64-bit indicator (is64l) indicates that 32-bit addressing is supported for the limit. this value must be in agreement with the is64b field. 1h ro 15:0 4 prefetchabl e memory base (pmb) these bits are compared with bits 31:20 of the incoming address to determine the lower 1 mbyte aligned value (inclusive) of the range. the incoming address must be greater than or equal to this value. 000h r/w 03:0 0 64-bit indicator (is64b) indicates that 32-bit addressing is supported for the limit. this value must be in agreement with the is64l field. 1h ro table 599. offset 28: pmbu32?prefetchable memory base upper 32 bits bits name description reset value access 31:0 0 prefetchabl e memory base upper portion (pmbu) all bits are read/writable. this register should always be programmed to 00000000h since the intel ? 6300ESB ich only supports 32-bit downstream addressing and 64-bit upstream addressing 00000000h r/w device 28 function 0 offset 24 attribute: read/write size: 32-bit device 28 function 0 offset 28 attribute: read/write size: 32-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 666 order number: 300641-004us 18.6.1.17offset 2c: pmlu32?prefetchable memory limit upper 32 bits note: this defines the upper 32 bits of the prefetchable address limit register. 18.6.1.18offset 30: ioblu16?i/o base and limit upper 16 bits note: since i/o is limited to 64 kbytes, this register is reserved and not used. table 600. offset 2c: pmlu32?prefetchable memory limit upper 32 bits bits name description reset value access 31:0 0 prefetchabl e memory limit upper portion (pmlu) all bits are read/writable - the intel ? 6300ESB ich supports full 64-bit addressing. note: the upper 32 bits should not be used to determine the prefetch region. the intel ? 6300ESB ich supports only 32-bit downstream cycles, so the upper 32 bits of the prefetch region are ignored. prefetch regions are limited to a single 4 gbyte boundary. the upper 32 bits of the prefetch region cannot be used to extend this region. the intel ? 6300ESB ich supports 64-bit upstream cycles, although the upper 32 bits are not used to determined the destination if the target lies within the intel ? 6300ESB ich . 00000000h r/w table 601. offset 30: ioblu16?i/o base and limit upper 16 bits bits name description reset value access 31:1 6 i/o base high 16 bits (iobh) reserved. 0000h ro 15:0 0 i/o limit high 16 bits (iolh) reserved. 0000h ro device 28 function 0 offset 2c attribute: read/write size: 32-bit device 28 function 0 offset 30 attribute: read-only size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 667 18?intel ? 6300ESB ich 18.6.1.19offset 34: capp?capabilities list pointer note: contains the pointer for the first entry in the capabilities list. 18.6.1.20offset 3c: intr?interrupt information note: this register contains information on interrupts on the bridge. 18.6.1.21offset 3e: bctrl?bridge control note: this register provides extensions to the command register that are specific to a bridge. the bridge control register provides many of the same controls for the secondary interface that are provided by the command register for the primary interface. some bits affect operation of both interfaces of the bridge. table 602. offset 34: capp?capabilities list pointer bits name description reset value access 07:0 0 capabil- ities pointer (ptr) indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. 50h ro table 603. offset 3c: intr?interrupt information bits name description reset value access 15:0 8 interrupt pin (pin) bridges do not support the generation of interrupts. 00h ro 07:0 0 interrupt line (line) the intel ? 6300ESB ich bridge does not generate interrupts, so this is reserved as 00h. 00h ro device 28 function 0 offset 34 attribute: read-only size: 8-bit device 28 function 0 offset 3c attribute: read-only size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 668 order number: 300641-004us table 604. offset 3e: bctrl?bridge control (sheet 1 of 3) bits name description reset value access 15:1 1 reserved reserved. 0h ro 12 perr# to serr# enable when this bit is set to ?1?, pci-x perr nmi reporting is enabled. in addition to setting this bit, you also must set bit ?1? of d30_f0 pne register. section 7.1.28 when this bit is set to a ?1? and perr# is asserted on pci-x, the perr# assertion detect status bit in the secondary status register will indicate a perr# internal serr# assertion. the serr# can be a s source on nmi. 11 discard timer serr# enable (dtse) controls the generation of serr# on the primary interface in response to a timer discard on the secondary interface. when 0: do not generate serr# on a secondary timer discard when 1: generate serr# in response to a secondary timer discard 0r/w 10 discard timer status (dtsb) this bit is set to a ?1? when the secondary discard timer expires (there is no discard timer for the primary interface). 0r/wc 09 secondary discard timer (sdt) sets the maximum number of pci clock cycles that the intel ? 6300ESB ich waits for an initiator on pci to repeat a delayed transaction request. the counter starts once the delayed transaction completion is at the head of the queue. if the master has not repeated the transaction at least once before the counter expires, the intel ? 6300ESB ich discards the transaction from its queues. when 0: the pci master timeout value is between 2^15 and 2^16 pci clocks. when 1: the pci master timeout value is between 2^10 and 2^11 pci clocks 0r/w 08 primary discard timer (pdt) not relevant to hub interface. this bit is r/w for software compatibility only. 0r/w 07 fast back- to-back enable (fbe) the intel ? 6300ESB ich cannot generate fast back-to-back cycles on the pci-x bus from hub interface initiated transactions. 0ro device 28 function 0 offset 3e attribute: read/write size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 669 18?intel ? 6300ESB ich 06 secondary bus reset (sbr) controls pxpcirst# assertion on pci-x bus when sbre is set. see section 18.6.1.32, ?offset e4: pcr - pci compensation register? for sbre details. 1 = the intel ? 6300ESB ich asserts pcixsbrst#. when pcixsbrst# is asserted, the data buffers between the hub interface and pci-x and the pci-x bus are initialized back to reset conditions. the hub interface and the configuration registers are not affected. to be effective, software must keep asserted for at least 100 secs. 0 = the intel ? 6300ESB ich de-asserts pcixsbrst# 0r/w 05 master abort mode (mam) controls the intel ? 6300ESB ich's behavior when a master abort occurs on either interface. master abort on hub interface: when 0: the intel ? 6300ESB ich asserts trdy# on pci-x. it drives all '1's for reads and discards data on writes. when 1: the intel ? 6300ESB ich returns a target abort on pci-x. master abort pci/pci-x: (completion required packets only) when 0: normal completion status is returned on the hub interface. when 1: target abort completion status is returned on the hub interface. 0r/w 04 vga 16-bit decode enables the bridge to provide 16 bits decoding of vga i/o address precluding the decode of vga alias addresses every 1 kb. this bit requires the vga enable bit (bit 3 of this register) to be set 1. 0r/w 03 vga enable (vgae) modifies the intel ? 6300ESB ich's response to vga compatible address. when set to a 1, the intel ? 6300ESB ich forwards the following transactions from the hub interface to pci-x regardless of the value of the i/o base and limit registers. the transactions are qualified by the memory enable and i/o enable in the command register. memory addresses: 000a0000h-000bffffh i/o addresses: 3b0h-3bbh and 3c0h-3dfh. for the i/o addresses, bits [63:16] of the address must be 0, and bits [15:10] of the address are ignored (i.e., aliased). the same holds true from secondary accesses to the primary interface in reverse. that is, when the bit is 0, memory and i/ o addresses on the secondary interface between the above ranges are forwarded to the hub interface. 0r/w table 604. offset 3e: bctrl?bridge control (sheet 2 of 3) bits name description reset value access device 28 function 0 offset 3e attribute: read/write size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 670 order number: 300641-004us 02 isa enable (ie) modifies the response by the bridge to isa i/o addresses. this only applies to i/o addresses that are enabled by the i/o base and i/o limit registers and are in the first 64 kbytes of pci-x i/o space. when this bit is set, the bridge blocks any forwarding from primary to secondary of i/o transactions addressing the last 768 bytes in each 1 kbyte block (offsets 100h to 3ffh). this bit has no effect on transfers originating on the secondary bus as the intel ? 6300ESB ich does not forward i/o transactions across the bridge. 0r/w 01 pxserr# enable (se) when set, the bridge is enabled for serr reporting. 0 r/w 0 parity error response enable (pere) controls the intel ? 6300ESB ich's response to address and data parity errors on the secondary interface. when the bit is cleared, the bridge must ignore any parity errors that it detects and continue normal operation. the intel ? 6300ESB ich must generate parity even when parity error reporting is disabled. 0r/w table 604. offset 3e: bctrl?bridge control (sheet 3 of 3) bits name description reset value access device 28 function 0 offset 3e attribute: read/write size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 671 18?intel ? 6300ESB ich 18.6.1.22offset 40: cnf?intel ? 6300ESB i/o controller hub configuration table 605. offset 40: cnf?intel? 6300ESB i/o controller hub configuration (sheet 1 of 3) bits name description reset value access 15 reserved reserved. 0 ro 14:1 0 disable pxpclkou t 4- 0 (dpclk) disables a pci-x clock output that is not used in the system. bit 10 refers to pclkout0, bit 11 to pclkout1, etc. when disabled, the pclkout pin is tri-stated. note: bit 14 controls the feedback path. this bit should not be written to a ?1?. 00h r/w 09 enable i/o space to 1k granularity (en1k) when set, this enables the i/o space to be decoded to 1k, down from the 4k limit that currently exists in the i/o base and limit registers. it does this by redefining bits [11:10] and bits [3:2] of the iobl register at offset 1c to be read/write and enables them to be compared with i/o address bits [11:10] to determine if they are within the bridge's i/o range. 0r/w 08 pci-x mode (pmode) when set, indicates the bus is operating in pci-x mode. when cleared, indicates the bus is in pci mode. the power up value of this register is written based upon the table below: pcixcap=bit 7 m66en=bit 6 pcixcap m66en pci/xfreq pmode 0 0 pci 33 mhz 0 0 1 pci 66 mhz 0 mid n/a pci-x 66 mhz 1 1 n/a pci-x 66 mhz 1 the default value (s-select value) is determined by the values of m66en and pcixcap pins as per the table above. note: this register should not be written to and should be treated by software as read only. writes will change the register value rendering the contents invalid since the value will not affect the pci-x mode. r/w device 28 function 0 offset 40 attribute: read/write size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 672 order number: 300641-004us 07:0 6 pci-x frequency (pfreq) determines the frequency the pci-x bus operates. the power up value of this register is written based upon the following table: pcixcap=bit 7m66en=bit 6 pcixcap m66en pci/x freq 0 0 pci 33 mhz 0 1 pci 66 mhz mid n/a pci-x 66 mhz 1 n/a pci-x 66 mhz after software determines the buses? capabilities, it sets this value and the pmode bit (bit 8 of this register) to the desired frequency and resets the pci-x bus. the values are encoded as follows: bits freq (mhz)notes 0 33 only valid when pmode is 0. 166 10 not supported 11 not supported the default value (s-select value) is determined by the values of m66en and pcixcap pins as per the table above. note: this register should not be written to and should be treated by software as read only. writes will change the register value rendering the contents invalid since the value will not affect the pci-x mode. 0h r/w 05 restreamin g disable (rsdis) when this bit is set, this bridge of the intel ? 6300ESB ich no longer performs restreaming. this bit only applies when the bridge is in pci mode, and not when the bridge is in pci-x mode. when the pci transaction ends, either due to a pci master removing pxframe# or the intel ? 6300ESB ich asserting stop#, the intel ? 6300ESB ich discards all data in the prefetch buffer. 0r/w table 605. offset 40: cnf?intel? 6300ESB i/o controller hub configuration (sheet 2 of 3) bits name description reset value access device 28 function 0 offset 40 attribute: read/write size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 673 18?intel ? 6300ESB ich 18.6.1.23offset 42: mtt?multi-transaction timer note: this register controls the amount of time that the intel ? 6300ESB ich's arbiter allows a pci initiator to perform multiple back-to-back transactions on the pci-x bus. the number of clocks programmed in the mtt represents the ensured time slice (measured in pci clocks) allotted to the current agent, after which the arbiter grants another agent that is requesting the bus. 04:0 3 prefetch policy (pp) controls how the intel ? 6300ESB ich prefetches data on behalf of pci masters: 00: allow prefetching on mrm, mrl, and mr. 01: allow prefetching on mrm and mrl but not on a memory read. 1x: disable all prefetching. 00 r/w 02 delayed transaction depth (dtd) controls the intel ? 6300ESB ich behavior relative to the number and size of the delayed transaction buffers: when 0: 4 dts at 1k for 33/66 mhz when 1: 4 dts at 1k for all frequencies this bit is set by platform bios, based upon the pci frequency read from bits 8:6 of this register. 0r/w 01:0 0 maximum delayed tra n sa c - tions (mdt) controls the maximum number of delayed transactions the intel ? 6300ESB ich is allowed to have: 00 : 4 active, 4 pending 01 : 1 active, 1 pending 10 : 2 active, 2 pending 11 : reserved 00 r/w table 606. offset 42: mtt?multi-transaction timer bits name description reset value access 07:0 3 timer count value (mtc) this field specifies the amount of time that grant remains asserted to a master continuously asserting its request for multiple transfers. this field specifies the count in an 8-clock (pci clock) granularity. 00h r/w 02:0 0 reserved reserved. 000 ro table 605. offset 40: cnf?intel? 6300ESB i/o controller hub configuration (sheet 3 of 3) bits name description reset value access device 28 function 0 offset 40 attribute: read/write size: 16-bit device 28 function 0 offset 42 attribute: read/write size: 8-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 674 order number: 300641-004us 18.6.1.24offset 44: strp?pci strap status note: this register indicates the states of various straps for this pci-x interface. 18.6.1.25offset 50: px_capid?pci-x capabilities identifier note: identifies this item in the capabilities list as a pci-x register set. it returns 07h when read. 18.6.1.26offset 51: px_nxtp?next item pointer note: indicates where the next item in the capabilities list resides. this is the end of the list and 00h is returned. table 607. offset 44: strp?pci strap status bits name description reset value access 31:0 reserved reserved. ro table 608. offset 50: px_capid?pci-x capabilities identifier bits name description reset value access 07:0 0 identifier (id) indicates this is a pci-x capabilities list. 07h ro table 609. offset 51: px_nxtp?next item pointer bits name description reset value access 07:0 0 reserved reserved. 00h ro device 28 function 0 offset 44 attribute: read-only size: 32-bit device 28 function 0 offset 50 attribute: read-only size: 8-bit device 28 function 0 offset 51 attribute: read-only size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 675 18?intel ? 6300ESB ich 18.6.1.27offset 52: px_ssts?pci-x secondary status note: this is the pci-x command register which controls various modes of the bridge. table 610. offset 52: px_ssts?pci-x secondary status (sheet 1 of 2) bits name description reset value access 15:0 9 reserved reserved. 00h ro 08:0 6 secondary clock frequency (scf) this field is set with the frequency of the secondary bus. the values are: bits max frequency clock period 000 pci mode n/a 001 66 15 010 [not supported] 011 [not supported] 1xx reserved reserved the default value for this register is given by pcixcap=bit 7 m66en=bit 6 pcixcap m66enpci/x freq 0 0 pci 33 mhz 0 1 pci 66 mhz mid n/a pci-x 66 mhz 1 n/a pci-x 66 mhz xxx ro 05 split request delayed. (srd) this bit is set by a bridge when it cannot forward a transaction on the secondary bus to the primary bus because there is not enough room within the limit specified in the split transaction commitment limit field in the downstream split transaction control register. note: the intel ? 6300ESB ich does not set this bit. 0ro 04 split completion overrun (sco) this bit is set when a bridge terminates a split completion on the secondary bus with retry or disconnect at next adb because its buffers are full. note: the intel ? 6300ESB ich does not set this bit. 0ro 03 unexpected split completion (usc) this bit is set when an unexpected split completion with a requester id equal to the intel ? 6300ESB ich's secondary bus number, device number 00h, and function number 0 is received on the secondary interface. this bit is cleared by software writing a ?1?. 0r/wc device 28 function 0 offset 52 attribute: read-only size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 676 order number: 300641-004us 18.6.1.28offset 54: px_bsts - pci-x bridge status note: identifies pci-x capabilities and current operating mode of the bridge. 02 split completion discarded (scd) this bit is set when the intel ? 6300ESB ich discards a split completion moving toward the secondary bus because the requester would not accept it. this bit is cleared by software writing a ?1?. 0r/wc 01 133 mhz capable (c133) this bit indicates that the intel ? 6300ESB ich?s secondary interface is capable of 133 mhz operation in pci-x mode. 0 = not capable 1 = capable 0ro 00 64-bit device (d64) indicates the width of the secondary bus as 64-bits. 1 ro table 611. offset 54: px_bsts - pci-x bridge status bits name description reset value access 31:2 2 reserved reserved. 0 ro 21 split request delayed (srd) the intel ? 6300ESB ich does not support this bit. 0 ro 20 split completion overrun (sco) the intel ? 6300ESB ich does not set this bit because it does not request more data on the hub interface than it may receive. 0ro 19 unexpected split completion (usc) this does not apply to hub interface, which is the primary interface. 0ro table 610. offset 52: px_ssts?pci-x secondary status (sheet 2 of 2) bits name description reset value access device 28 function 0 offset 52 attribute: read-only size: 16-bit device 28 function 0 offset 54 attribute: read-only size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 677 18?intel ? 6300ESB ich 18 split completion discarded (scd) this does not apply to hub interface. 0 ro 17 reserved reserved. 0 ro 16 64-bit device (d64) default value is 1. the hub interface is a 64-bit interface (in hi2.0, it is 128 bits). 1ro 15:0 8 bus number (bnum) an alias to the pbn field of the bnum register at offset 18h. available for diagnostic software. 00h ro 07:0 3 device number (dnum) default value is device 28. readable from separate pci-x diagnostic software. 1ch ro 02:0 0 function number (fnum) read-only bits for pci-x diagnostic software. 0h ro table 611. offset 54: px_bsts - pci-x bridge status bits name description reset value access device 28 function 0 offset 54 attribute: read-only size: 32-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 678 order number: 300641-004us 18.6.1.29offset 58: px_ustc - pci-x upstream split transaction control note: this register identifies controls behavior of the pci-x upstream split control buffers for forwarding split transactions from the secondary bus to the hub interface. note: the intel ? 6300ESB ich maintains these registers internally; programming is not required by end users. 18.6.1.30offset 5c: px_dstc - pci-x downstream split transaction control note: this register controls behavior of the pci-x downstream split control buffers for forwarding split transactions from the hub interface to the secondary bus. note: the intel ? 6300ESB ich maintains these registers internally, programming not required by end users. table 612. offset 58: px_ustc - pci-x upstream split transaction control bits name description reset value access 31:1 6 split transactio n limit (stl) r/w field available for use by diagnostic software. note: not used by the intel ? 6300ESB ich for modifying its ?commitment? level. the intel ? 6300ESB ich internal launch algorithms keep buffers from being overallocated. 0000h r/w 15:0 0 split transactio n capacity (stc) infinite capacity due to launch algorithm keeping buffers from overrunning. the intel ? 6300ESB ich internal launch algorithms keep buffers from being overallocated. ffffh ro device 28 function 0 offset 58 attribute: read/write size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 679 18?intel ? 6300ESB ich table 613. offset 5c: px_dstc - pci-x downstream split transaction control bits name description reset value access 31:1 6 split transaction limit (stl) r/w field available for use by diagnostic software. note: not used by the intel ? 6300ESB ich for modifying its ?commitment? level. the intel ? 6300ESB ich internal launch algorithms keep buffers from being overallocated. 0000h r/w 15:0 0 split transaction capacity (stc) infinite capacity due to launch algorithm keeping buffers from overrunning. the intel ? 6300ESB ich internal launch algorithms keep buffers from being overallocated ffffh ro device 28 function 0 offset 5c attribute: read/write size: 32-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 680 order number: 300641-004us 18.6.1.31offset e0: acnf ? additional intel ? 6300ESB ich configuration table 614. offset e0: acnf ? additional intel? 6300ESB ich configuration bits name description reset value access 31:1 6 reserved reserved. 0 ro 15:1 4 reserved reserved. 0 r/w 13:1 2 miscella- neous (msc) reserved but maintained as read/write in case a situation arises during the project which may require their use. 0r/w 11 reserved reserved. 0 r/w 10:0 7 reserved reserved. 0 r/w 06 reserved reserved. 0 ro 05 bunit inbound pending queue bypass (bupb) when 1, bunit bypasses it?s read pending queue when empty. this bit may only be set to ?1? when in pci mode. 0r/w 04 reserved reserved. 0 r/w 03:0 0 reserved reserved. fh r/w device 28 function 0 offset e0 attribute: read-only size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 681 18?intel ? 6300ESB ich 18.6.1.32offset e4: pcr - pci compensation register table 615. offset e4: pcr - pci compensation register bits name description reset value access 15:1 0 reserved reserved. 0 r/w 09 sbr enable (sbre) this field specifies the maximum size write a master should request in a single b 0 = pci-x secondary bus reset (pcixsbrst#) disabled and sbr bit has no effect. see section 18.6.1.21, ?offset 3e: bctrl?bridge control? , bit 6, for sbr details. 1 = pci-x secondary bus reset (pcixsbrst#) enabled and sbr is set. note: processor always writes a ?1? into this bit and enables the secondary bus reset for the pci-x bus. 0r/w 08:0 reserved reserved. 0 r/w device 28 function 0 offset e4 attribute: read/write size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 682 order number: 300641-004us 18.6.1.33offset f0: hccr - hub interface command/control register 18.6.1.34offset f8h ? offset ffh: prefetch control registers the following registers contain prefetch parameters. each parameter is in 64 byte cache line quantities. bios programs the values in these registers upon power up. the values in this register are zero-based ? a zero means 64 bytes, and ?1? means 128 bytes, etc. there is a fifth parameter in the prefetch algorithm, called ?d?, which is the delay to wait before sending a subsequent request of rs when prior requests of rs still have not brought the prefetch buffers above ts. its value is in pci clocks, and is [rs]:111. for example, when rs = ?0101?b, then d is ?0101111?b. note that for memory read (mr) and memory read line (mrl) commands in pci, no prefetching is done. a fetch of one cache line (based upon the cache line size register) is performed and when it drains, the delayed transaction is complete. a new delayed transaction is established when the master wished the burst to continue. table 616. offset f0: hccr - hub interface command/control register bits name description reset value access 31:2 0 reserved reserved. 0 ro 19:1 6 reserved reserved. 0h ro 15:1 0 reserved reserved. 0 ro 09:0 8 reserved reserved. 0 r/w 07:0 6 reserved reserved. 00 ro 5:4 reserved reserved. 0 ro 03:0 1 maximum data size (maxd) this field specifies the maximum size write a master should request in a single burst, as well as the maximum optimal size read completion a target should return. encoding: 000: 32 bytes others: 64 bytes 000 r/w 00 reserved reserved. 0 r device 28 function 0 offset f0 attribute: read/write size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 683 18?intel ? 6300ESB ich 18.6.1.35offset f8h: pc33 - prefetch control ? 33 mhz 18.6.1.36offset fah: pc66 - prefetch control ? 66 mhz table 617. offset f8h: pc33 - prefetch control ? 33 mhz bits name description reset value access 15:1 2 subsequen t threshold (ts) subsequent threshold size in 64-byte cache lines 1h r/w 11:0 8 subsequen t request (rs) subsequent request size in 64-byte cache lines. allowable programmable values are 00h or 01h only. 1h r/w 07:0 4 initial threshold (ti) initial threshold size in 64-byte cache lines 1h r/w 03:0 0 initial request (ri) initial request size in 64-byte cache lines. allowable programmable values are 00h or 01h only. 1h r/w table 618. offset fah: pc66 - prefetch control ? 66 mhz bits name description reset value access 15:1 2 subsequen t threshold (ts) subsequent threshold size in 64-byte cache lines. 3h r/w 11:0 8 subsequen t request (rs) subsequent request size in 64-byte cache lines. allowable programmable values are 00h or 01h only. 1h r/w 07:0 4 initial threshold (ti) initial threshold size in 64-byte cache lines. 2h r/w 03:0 0 initial request (ri) initial request size in 64-byte cache lines. allowable programmable values are 00h or 01h only. 1h r/w device 28 function 0 offset f8h attribute: read/write size: 16-bit device 28 function 0 offset fah attribute: read/write size: 16-bit
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 684 order number: 300641-004us 18.7 pci mode in the pci-x interface this section discusses the specifics of the pci interface associated with the pci-x interface while operating in pci mode. the pci section of this document describes the ?legacy? pci which is not visible external to the chip. pci-x is not mentioned in this section. to see specifics on how the pci-x interface operates, refer to section 18.8, ?pci-x interface? . 18.7.1 summary of changes for the most part, the pci interface of the intel ? 6300ESB ich is exactly the same as the pci interface for the p64h2. ? full 64 bit addressing inbound ? inbound packet size based upon cache line size of the platform. ? i/o space may be programmed to 1k granularity through the en1k bit of the cnf register. ? when inbound reads are retried, they are moved to the side so posted writes and completion packets may pass. i/o reads and writes on pci are no longer be forwarded to the hub interface. 18.7.2 transaction types as a pci master, the intel ? 6300ESB ich has access to the 32-bit address space. as a target, the intel ? 6300ESB ich may accept dual address cycles up to the full 64-bit address space. the intel ? 6300ESB ich supports the linear increment address mode only for bursting memory transfers (indicated when the low two address bits are equal to ?0?). when either of these address bits is nonzero, the intel ? 6300ESB ich disconnects the transaction after the first data transfer. table 619. intel ? 6300ESB i/o controller hub pci transactions type of transaction intel ? 6300ESB ich as type of transaction intel ? 6300ESB ich as maste r targe t maste r targe t 0000 interrupt acknowledge no no 1000 reserved ? no no 0001 special cycle yes no 1001 reserved ? no no 0010 i/o read yes no 1010 configuration read yes no 0011 i/o write yes no 1011 configuration write yes no 0100 reserved ? no no 1100 memory read multiple no yes 0101 reserved ? no no 1101 dual address cycle yes yes 0110 memory read yes yes 1110 memory read line no yes 0111 memory write yes yes 1111 memory write and invalidate no yes ? the intel ? 6300ESB ich never initiates a pci transaction with a reserved command code and ignores reserved command codes as a target.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 685 18?intel ? 6300ESB ich the intel ? 6300ESB ich decodes all pci cycles in medium devsel# timing. 18.7.3 detection of 64-bit environment the intel ? 6300ESB ich drives req64# low during pxpcirst# on each pci-x interface to signal that the bus is a 64-bit bus . 18.7.4 data bus for supplying data, the intel ? 6300ESB ich drives the following in the data phase: ? the low 32 bits of data on pxad[31:0] ? the low four byte enable bits on pxc/be#[3:0] ? the high 32 bits of data on pxad[63:32] (64-bit data phases only) ? the high four byte enable bits on pxc/be#[7:4] (64-bit data phases only) as a pci master, when the intel ? 6300ESB ich drives pxreq64# and detects pxack64# asserted in the same clock that it detects pxdevsel# asserted, every data phase then consists of 64 bits and eight byte enable bits. on write transactions, when the intel ? 6300ESB ich does not detect pxack64# asserted in the same clock that it detects pxdevsel# asserted, it redirects all data to ad[31:0] and byte enables to c/be#[3:0]. for 64-bit memory-write transactions that end at an odd dword boundary, the intel ? 6300ESB ich drives the byte enable bits to ?1?, and drives random but stable data on pxad[63:32]. on read transactions, the intel ? 6300ESB ich drives eight bits of byte enables on pxc/ be#[7:0]. it generates byte enables from the hub interface byte enables, with the upper dword driven on pxc/be#[7:4]. when ack64# is not sampled active with pxdevsel# active, then the intel ? 6300ESB ich downshifts the all byte enables pxc/ be#[3:0]. the intel ? 6300ESB ich does not assert req64# when initiating a transfer under the following conditions: ? the intel ? 6300ESB ich is initiating an i/o transaction. ? the intel ? 6300ESB ich is initiating a configuration transaction. ? the intel ? 6300ESB ich is initiating a special cycle transaction. ? a 1-dword or 2-dword transaction is being performed. ? when the address of the hub interface initiated transaction is not quad word aligned. as a pci target, the intel ? 6300ESB ich does not assert pxack64# when pxreq64# was not asserted by the initiator. 18.7.5 write transactions 18.7.5.1 posted posted write forwarding is used for memory write and for memory write and invalidate transactions. when the intel ? 6300ESB ich decodes a memory write transaction for the hub interface, it asserts pxdevsel# and pxtrdy# in the same clock, provided that enough buffer space is available in the posted data queue. the intel ? 6300ESB ich adds no target wait states.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 686 order number: 300641-004us the intel ? 6300ESB ich disconnects a write transaction when: ? the initiator terminates the transaction by de-asserting pxframe# and pxirdy#. ? a 4 kbyte page boundary is reached. ? the posted write data buffer fills up. 18.7.5.2 non-posted delayed write forwarding is not used. it is only for i/o write transactions. since the intel ? 6300ESB ich does not support i/o write transactions across a bridge, these cycles all result in a master abort. note: configuration cycles are not allowed to cross a bridge per the pci bridge specification. 18.7.5.3 fast back-to-back the intel ? 6300ESB ich allows fast back-to-back write transactions on pci. 18.7.6 read transactions 18.7.6.1 prefetchable any memory read multiple command on pci that is decoded by the intel ? 6300ESB ich is prefetched on the hub interface. prefetching may be optionally disabled when bit 4 of the intel ? 6300ESB ich configuration register (offset 40-41h) is set. the intel ? 6300ESB ich does not prefetch past a 4 kbyte page boundary. 18.7.6.2 delayed all memory read transactions are delayed read transactions. when the intel ? 6300ESB ich accepts a delayed read request, it samples the address, command, and address parity. this information is entered into the delayed transaction queue and all i/o transactions then master abort. 18.7.7 transaction termination 18.7.7.1 normal master termination as a pci master, the intel ? 6300ESB ich uses normal termination when devsel# is returned by the target within five clock cycles of pxframe# assertion. it terminates a transaction when the following conditions are met: ? all write data for the transaction is transferred from the intel ? 6300ESB ich data buffers to the target. ? the master latency timer expires and the intel ? 6300ESB ich?s bus grant is de- asserted. 18.7.7.2 master abort termination when an intel ? 6300ESB ich initiated transaction is not responded to with devsel# within five clocks of pxframe# assertion, the intel ? 6300ESB ich terminates the transaction with a master abort. the intel ? 6300ESB ich sets the received master abort bit in the status register corresponding to the target bus.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 687 18?intel ? 6300ESB ich note: when the intel ? 6300ESB ich performs a type 1 to special cycle translation, a master abort is the expected termination for the special cycle on the target bus. in this case, the master abort received bit is not set, and the type 1 con-figuration transaction is disconnected after the first data phase. 18.7.7.3 target termination received by the intel ? 6300ESB ich when the intel ? 6300ESB ich receives a retry or disconnect response from a target, it re-initiates the transfer with the remaining length. when the intel ? 6300ESB ich receives a target abort, and the cycle requires completion on the hub interface, the intel ? 6300ESB ich returns the target abort code to the hub interface as the completion status. 18.7.7.4 target termination initiated by the intel ? 6300ESB ich the intel ? 6300ESB ich returns a target retry to an initiator for memory read transactions when any of the following conditions are met: ? a new transaction for delayed transaction queue. ? the request has already been queued, but has not completed on the hub interface. ? the delayed transaction queue is full, and the transaction cannot be queued. ? a lock transaction has been established from the hub interface to pci. the intel ? 6300ESB ich disconnects an initiator when one of the following conditions is met: ? the intel ? 6300ESB ich cannot accept any more write data ? the intel ? 6300ESB ich has no more read data to deliver ? when the memory address is non-linear the intel ? 6300ESB ich returns a target abort to pci when the cycle master aborted or target aborted on the hub interface. 18.7.8 lock cycles a lock is established when a memory read from the hub interface that targets pci with the lock bit set, and at least one byte enable active, is responded to with a trdy# by a pci target. the intel ? 6300ESB ich does not support a split-lock request with no byte enables are asserted on the initial locked read request. the bus is unlocked when the unlock special cycle is sent on the hub interface. when the bus is locked, the cycle is retried when a memory cycle originates on pci that is outside the range of the memory windows. no i/o cycles that are destined across the bridge are accepted, whether the bus is locked or not, and then master abort. once the bus is locked, any hub interface cycle to pci is driven with the lock# pin, even when that particular cycle is not locked. 18.7.9 error handling the intel ? 6300ESB ich checks and generates parity on the hub interface and parity on the pci interfaces. parity errors must always be reported to some system level software, typically the device driver or the os. this section describes how a standard pci bridge handles these errors. for enhanced error detection, see the ras section located section.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 688 order number: 300641-004us the intel ? 6300ESB ich requires that the ?hub interface parity unsupported? bit (d30:f0:40h:bit 20) is cleared in order to perform any parity checking as described below. good hub interface parity is presented to all logic in the intel ? 6300ESB ich when the bit is set. to support error reporting on the pci bus, the intel ? 6300ESB ich implements the following: ? perr# and serr# signals on pci ? primary status (offset 06-07h) and secondary status registers (offset 1e-1fh) the intel ? 6300ESB ich does not have the perr# or serr# pins on the hub interface. the intel ? 6300ESB ich is capable of generating nmi, and smi address parity errors address parity errors are very serious and may abort further data transfers, depending upon the direction of the transfer and the setting of the parity error response enable bit, as described in the following paragraphs. the intel ? 6300ESB ich checks address parity for all transactions on both the hub interface and pci buses, for all address and all bus commands. when the intel ? 6300ESB ich detects an parity error in the header section of a hub interface packet, it: ? sets the detected parity error bit in the primary status register (bit 15 of offset 06- 07h) when the address is targeting the device. the bridge devices log address parity errors independent of the target address. ? generates nmi/smi (as enabled) and sets the signaled system error bit in the primary status register (bit 14 of offset 06-07h), when the parity error response bit in the command register (bit 6 of offset 04-05h) is set and serr# is enabled. ? attempts to interpret the cycle as best it can, and forwards the cycle with an address parity error tag to the internal logic, where it aborts internally. when a device is not enabled to respond to parity errors, it ignores the address parity error (except for setting the detected parity error bit). when the address targets that device, the device accepts the cycle and responds as though there was no address parity error. the cycle is forwarded to pci with good address parity when the cycle targets a bridge and it is not enabled to respond to parity errors. when the intel ? 6300ESB ich detects an address parity error on the pci interface, the following events occur: the intel ? 6300ESB ich sets the detected parity error bit in the secondary status register (bit 15 of offset 1e-1f). ? when the parity error response bit is ?0? in the bridge control register (bit ?0? of offset 3e-3f), the address parity errors are ignored. the cycles would be treated as though no error was observed. ? when the parity error response bit is set and the address parity error is observed on memory cycles, the cycle is accepted as though the address was correct. delayed transactions are established for memory reads and data are posted for memory writes. the cycles are forwarded to the hub interface with correct address parity. the intel ? 6300ESB ich generates nmi/smi (as enabled) sets the signaled system error bit in the primary status register, when all of the following conditions are met: ? the serr# enable bit is set in the primary command register. ? the parity error response bit is set in the bridge control register. ? the serr# enable bit is set in the bridge control register. the intel ? 6300ESB ich generates nmi, if the following conditions are met: ? port70.7 (i/o register at offset 70h, bit 7) is enabled.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 689 18?intel ? 6300ESB ich ? the parity errors response bit is set in the bridge control register (d28:3eh,0) 18.7.9.1 data parity errors unlike address parity errors, data parity errors are not considered as severe and transactions are aborted. the following sections describe the sequence of events when a data parity error is detected for the following transactions: ? configuration write transactions ? read transactions (inbound and outbound) ? posted write transaction 18.7.9.1.1 hub interface configuration write transactions when the intel ? 6300ESB ich detects a data parity error during a type 0 configuration write transaction to one of the intel ? 6300ESB ich configuration spaces, the intel ? 6300ESB ich: ? does not write the data to the configuration register when parity error response is enabled. ? sets the detected parity error bit in the primary status register (bit 15 of offset 06- 07h). ? generates nmi/smi (depending on which is enabled) and sets the signaled system error bit (bit 14) in the primary status register, when the parity error response enable bit in the command register (bit 6 of offset 04-05h) is set. 18.7.9.1.2 read transactions from hub interface targeting pci on the pci-x when the intel ? 6300ESB ich detects a read data parity error on the pci bus from a hub interface initiated read, it: ? sets the detected parity error bit in the secondary status register (bit 15 of offset 1e-1fh). ? sets the data parity detected bit in the secondary status register (bit 8 of offset 1e- 1fh), when the secondary interface parity error response bit is set in the bridge control register (bit ?0? of offset 3e-3fh). ? forces bad parity error with the data back to the initiator on the hub interface. 18.7.9.1.3 read transactions from pci targeting hub interface when the intel ? 6300ESB ich detects a data parity error on a hub interface completion packet from a previous memory read request on pci, the intel ? 6300ESB ich: ? sets the detected parity error bit in the primary status register (bit 15 of offset 06- 07h). ? sets the data parity detected bit in the primary status register (bit 8 of offset 06- 07h) and generates the nmi/smi (depending on which is enabled), when the primary interface parity error response bit is set in the command register (bit 6 of offset 04-05h). ? forwards the bad parity with the data back to pci. 18.7.9.1.4 write transactions on hub interface ? intel ? 6300ESB ich as a hub interface target when the intel ? 6300ESB ich detects a data parity error on a hub interface write request, it: ? sets the data parity error detected bit in the status register (bit 15 of offset 06- 07h) of the target interface (pci bridge primary).
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 690 order number: 300641-004us ? forwards the bad parity with the data to pci when decoded by the bridge. ? generates nmi/smi (depending on which is enabled) and sets the signaled system error bit (bit 14) in the primary status register, when the parity error response bit (bit 6) is set in the command register. 18.7.9.1.5 write transactions on hub interface ? intel ? 6300ESB ich as a hub interface master there is no way of detecting that a northern device detected a parity error from a hub interface posted write from pci. therefore, no action is taken by the intel ? 6300ESB ich. 18.7.9.1.6 write transactions on pci ? intel ? 6300ESB ich as pci target when the intel ? 6300ESB ich detects a data parity error on a pci write, it: ? asserts perr# two cycles after the data transfer, when the secondary interface parity error response bit is set in the bridge control register. ? sets the secondary interface parity error detected bit in the secondary status register. ? forces bad parity error condition to the primary bus. 18.7.9.1.7 write transactions on pci ? intel ? 6300ESB ich as pci master when a data parity error is reported on the pci bus from a hub interface or pci peer initiated write request by the target?s assertion of perr#, the intel ? 6300ESB ich: ? sets the detected parity detected bit in the secondary status register (bit 8 of offset 1e-1fh), when the secondary interface parity error response bit is set in the bridge control register. ? generates nmi/smi (depending on which is enabled) and sets the signaled system error bit in the status register, when all of the following conditions are met: ? the serr# enable bit is set in the command register. ? the secondary interface parity error response bit is set in the bridge control register. ? the primary interface parity error response bit is set in the command register. ?the intel ? 6300ESB ich did not detect the parity error on the hub interface (i.e., the parity error was not forwarded from the hub interface). 18.7.9.2 system errors 18.7.9.2.1 pci serr# pin assertion when serr# is sampled asserted, the intel ? 6300ESB ich sets the received system error bit in the secondary status register. the intel ? 6300ESB ich generates nmi/smi (depending on which is enabled) when: ? the serr# forward enable bit is set in the bridge control register, and ? the primary serr# enable bit is set in the primary command register. 18.7.9.2.2 other system errors the intel ? 6300ESB ich also conditionally nmi or smi as enabled for any of the following reasons: ? master timeout on delayed transaction when the primary serr# enable bit is set and serr# due to timeout enable bit (bit 11 of offset 3e-3fh) is set. ? the mam bit (master abort mode) is set in the bridge control register and a posted write from the hub interface results in a master abort on pci, or a posted write from one pci interface results in a master abort on the other pci interface. (no
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 691 18?intel ? 6300ESB ich indication is given back on the hub interface when a posted pci write fails on the hub interface ? the north hub interface agent must handle this condition). 18.8 pci-x interface this section is not intended to describe the pci-x protocol. it is intended to clarify the intel ? 6300ESB ich behavior in areas of the specification which are open to interpretation. please see the pci-x addendum to the pci specification, revision 1.0 for all details related to pci-x operation. unless otherwise noted in this section, the intel ? 6300ESB ich follows all rules of the pci-x addendum. 18.8.1 command encoding 18.8.2 attributes the following table describes how the intel ? 6300ESB ich fills in attribute fields where the pci-x specification leaves some implementation leeway. table 620. pci-x interface command encoding type of transaction intel ? 6300ESB ich as type of transaction intel ? 6300ESB ich as maste r targe t mast er targe t 000 0 interrupt acknowledge no no 100 0 alias to memory read block no yes 000 1 special cycle no no 100 1 alias to memory write block no yes 001 0 i/o read yes no 101 0 configuration read yes no 001 1 i/o write yes no 101 1 configuration write yes no 010 0 reserved no no 110 0 split completion yes yes 010 1 reserved no no 110 1 dual address cycle yes yes 011 0 memory read dword yes yes 111 0 memory read block yes yes 011 1 memory write yes yes 111 1 memory write block no yes
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 692 order number: 300641-004us 18.8.3 special notes for burst transactions the pci-x specification allows burst transactions to cross page (in the intel ? 6300ESB ich?s case, this is 4k) and 4 gbyte address boundaries. as a pci-x master, the intel ? 6300ESB ich ends the transaction at a 4k boundary. as a pci-x target, the intel ? 6300ESB ich allows a burst past a 4k page boundary. the intel ? 6300ESB ich does not issue an immediate response as a target for a burst read command, but it must be ready with 128 bytes of data space (an adq) as an initiator. when it does not have this space available, it does not issue the transaction. 18.8.4 device select timing pci-x targets are required to claim transactions by asserting devsel# as shown in table 622 . the intel ? 6300ESB ich responds as a type a target. 18.8.5 wait states the intel ? 6300ESB ich does not generate wait states as a target. instead, it ends the transfer. table 621. intel ? 6300ESB ich implementation of requester attribute fields attribute function no snoop (ns) as a target, this bit is forwarded with the transaction to allow a north bridge to not snoop the transaction. it goes to bit ?1? in the td attr field of the hub interface packet. it is not generated by the intel ? 6300ESB ich as a master from a hub interface packet. the intel ? 6300ESB ich takes no action on this bit. relaxed ordering (ro) this bit allows relaxed ordering of transactions, which the intel ? 6300ESB ich does not permit. this bit is simply forwarded in the intel ? 6300ESB ich, and is never generated on pci-x from a hub interface packet. ta g since the intel ? 6300ESB ich only has one outstanding request on pci-x at a time, this field is be set to 0. byte counts from the hub interface, this is based upon the length field from the hub interface, which is dword based. table 622. devsel# timing decode speed pci-x 1 clock after address phase(s) not supported 2 clocks after address phase(s) decode a 3 clocks after address phase(s) decode b 4 clocks after address phase(s) decode c 5 clocks after address phase(s) n/a 6 clocks after address phase(s) subtractive
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 693 18?intel ? 6300ESB ich 18.8.6 split transactions 18.8.6.1 completer attributes 18.8.6.2 requirements for accepting split completions the intel ? 6300ESB ich asserts devsel# and discards the data when the requester id matches the bridge, but the tag does not match that of any outstanding requests from this device, or when the byte count exceeds that of the split request. the hub interface accepts more than one completion required request from the hub interface, but only one is pending on any pci/pci-x interface at a time. 18.8.6.3 split completion messages the intel ? 6300ESB ich may only generate error messages for cycles that cross the bridge that master or target abort. no dword cycles cross the bridge that require completion (i.e., i/o cycles). therefore, the intel ? 6300ESB ich generates a ?pci-x bridge error? completion message for the memory read commands as shown in table 624 . 18.8.6.4 arbitration among multiple split completions the intel ? 6300ESB ich arbitrates among all active split completions so that each completion receives consideration for running on pci. when there are multiple completions waiting to use pci, the intel ? 6300ESB ich internally arbitrates based upon its mlt value, even when no other agents are requesting on the bus. therefore, the intel ? 6300ESB ich ends one transaction when its mlt expires, reload, and start another transaction. when any particular transaction runs out of data, and there are other active transactions to run, the intel ? 6300ESB ich switches to the next agent, even when the mlt has not expired for that transaction. finally, the prefetch algorithm is altered such that several transactions may be active at one time. table 623. intel ? 6300ESB ich implementation completer attribute fields attribute function byte count modified (bcm) this bit is used for diagnostic purposes. the intel ? 6300ESB ich never sets this bit. split completion error (sce) the intel ? 6300ESB ich is only set this bit when a memory read command from pci-x master or target aborted on the hub interface. split completion message (scm) this bit shadows the sce bit. table 624. split completion messages index message 00h master-abort: the intel ? 6300ESB ich encountered a master-abort on the destination bus. 01h target-abort: the intel ? 6300ESB ich encountered a target-abort on the destination bus.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 694 order number: 300641-004us 18.8.7 transaction termination as a pci-x target 18.8.7.1 retry the intel ? 6300ESB ich retries a cycle when the split request queue is full (i.e., we already have four current and four pending split transactions). it has room to accept a split completion as it has a dedicated buffer for split completions. it also retries a cycle when the bus is locked. the intel ? 6300ESB ich stores no state from the transaction on a retry. 18.8.7.2 split response all cycles that cross the bridge receive this termination, when they are not retried. 18.8.7.3 master-abort any i/o transaction that would cross from pci-x to either the hub interface or the peer bridge are not decoded and results in a master abort to the pci-x initiator. 18.8.8 arbitration the intel ? 6300ESB ich parks on the last agent to use pci. this allows pci devices operating as a single stream to stay on pci bus for the duration of their transfer. 18.8.9 bridge buffer requirements the intel ? 6300ESB ich has 128 bytes (one adq) available for accepting memory write, split completion, and immediate read data. the intel ? 6300ESB ich contains 1.5k of data total for inbound transactions. the intel ? 6300ESB ich pci-x interface terminates all memory transactions (memory read dword, memory read block, and alias to memory read block) that address a device north of the bridge with a split response. other split transaction commands are not decoded by the intel ? 6300ESB ich. the intel ? 6300ESB ich does not implement any split completion buffer allocation algorithm as listed in the pci-x specification. this is overhead that is not necessary. the intel ? 6300ESB ich does not request on the hub interface more than it has buffer space for on returns, and does not initiate a cycle from the hub interface that it cannot accept as a return. the bridge rules of the specification already allow the pci-x interface to retry split completions when the bridge is temporarily full. therefore, the split transaction control registers are not used by the intel ? 6300ESB ich. 18.8.10 locked transactions the intel ? 6300ESB ich is not locked until the target has completed at least the first data phase as an immediate transaction or a split transaction (target signals split response).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 695 18?intel ? 6300ESB ich 18.8.11 error support 18.8.11.1general as a pci-x target, the intel ? 6300ESB ich bridge responds as specified in the pci-x addendum. 18.8.11.2special parity error rule for split response when the intel ? 6300ESB ich calculates a data parity error when a target signals split response for a read transaction, it records the error as described in section 5.4.1 of the pci/x 1.0 specification . furthermore, when the intel ? 6300ESB ich is enabled to assert perr# on the secondary bus and enabled to assert serr# on the hub interface, it generates nmi/smi (depending on which is enabled). 18.9 transaction termination translation between interfaces though intel ? 6300ESB ich?s primary bus is the hub interface, from a register and software perspective, the hub interface is a pci-x bus and intel ? 6300ESB ich is a pci-x bridge that supports a secondary bus configured as either pci or pci-x. section 8.7.1.5 of the pci-x 1.0 specification modified the behavior of a bridge from that specified in the pci to pci bridge 1.1 spec regarding returning completions on the primary bus when the secondary bus transaction terminates in either a master abort or target abort. in general, the pci-x spec does not honor the master abort mode bit for cycles requiring completions, and returns to the primary bus the termination that occurred on the secondary bus without any translation. the following sections describe the behavior of the intel ? 6300ESB ich on both the hub interface and the pci/pci-x under various termination conditions. for specific information as to why the intel ? 6300ESB ich?s pci, pci-x, or hub interface generates a specific termination, see the specific sections on the interface above. 18.9.1 behavior of hub interface initiated cycles to pci/ pci-x receiving immediate terminations the behavior described for completion required cycles is independent of the setting of the master abort mode bit, and is independent of whether the cycle is exclusive (locked) or not. the intel ? 6300ESB ich returns all ?1?s on data bytes for a read completion that terminates in either master abort or target abort. table 625. immediate terminations of completion required cycles to pci/pci-x pci/pci-x termination hub interface completion status register bits set ? the master data parity error bit is set only when a data parity error is encountered on the pci/pci-x bus.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 696 order number: 300641-004us 18.9.2 behavior of hub interface initiated cycles to pci- x receiving split terminations the behavior described in the following table is independent of the master abort mode bit and whether or not the cycle is exclusive (locked) or not. the intel ? 6300ESB ich returns all ?1?s on all data bytes for a read completion that terminates in either master abort or target abort on the hub interface. note that when a target or master abort is returned on the hub interface, the attached pci/pci-x bus is not locked. this is of special importance to the completion messages of ?data parity error?, ?byte count out of range?, ?write data parity error?, ?device specific?, and reserved/illegal codes. the intel ? 6300ESB ich must not lock its bus on these errors, even though they are not explicitly master or target aborts on the pci-x interface. successful successful master data parity error (sec) ? master abort master abort received master abort (sec) target abort target abort received target abort (sec) signaled target abort (pri) master data parity error (sec) ? table 626. immediate terminations of posted write cycles to pci/pci-x pci/pci-x termination mam bit action status register bits set successful n/a none none master abort 1 generate nmi/smi received master abort (sec) signaled system error (pri) master abort 0 none received master abort (sec) ta rg e t ab o r t n / a generate nmi/smi as enabled received target abort (sec) signaled system error (pri) table 625. immediate terminations of completion required cycles to pci/pci-x ? the master data parity error bit is set only when a data parity error is encountered on the pci/pci-x bus. table 627. split terminations of completion required cycles to pci-x (sheet 1 of 2) pci-x split termination message hub interface completion status register bits set class index successful 0 00h successful master data parity error (sec), when encountered master abort 1 00h master abort received master abort (sec) ta rg e t ab o r t 1 0 1 h ta rg e t a b o rt received target abort (sec) signaled target abort (pri) write data parity error 1 02h target abort master data parity error (sec) signaled target abort (pri) byte count out of range 2 00h target abort signaled target abort (pri)
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 697 18?intel ? 6300ESB ich 18.9.3 hub interface action on immediate responses to pci-x split completions the following table indicates what the intel ? 6300ESB ich does when it is returning a split completion to pci-x from a normal hub interface completion, and receives an immediate response indicating some kind of error. write data parity error 2 01h target abort master data parity error (sec) signaled target abort (pri) device specific 2 8xh target abort signaled target abort (pri) reserved/illegal others target abort signaled target abort (pri) table 627. split terminations of completion required cycles to pci-x (sheet 2 of 2) pci-x split termination message hub interface completion status register bits set class index table 628. hub interface response to pci-x split completion terminations of completion required cycles split completion termination action status register bits successful none none master abort assert serr# ? received master abort (sec) split completion discarded (sec) signaled system error (pri) ? target abort assert serr# ? received target abort (sec) split completion discarded (sec) signaled system error (pri) ? ? in this case, the assertion of serr# and setting of the signaled system error bit only occur when the serr# enabled in the primary command register is set.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 698 order number: 300641-004us 18.9.4 behavior of pci/pci-x initiated cycles to hub interface 18.10 delayed/split transactions 18.10.1 number supported when in pci mode, transactions follow the delayed transaction model of pci 2.2. when in pci-x mode, transactions follow the split transaction model of pci-x. for each bridge, the intel ? 6300ESB ich supports eight delayed / split transactions inbound, and one delayed/split transaction outbound. the hub interface may take four outbound delayed/split transactions, but only launches one at a time to each pci-x interface. each pci interface may take eight delayed/split transactions, but only launches four of those transactions onto the hub interface. the outbound delayed/split transactions does not prefetch from pci devices, regardless of whether the transaction falls in the prefetchable window or the non-prefetchable window. when in pci mode, the inbound delayed/split transactions prefetch for all command types. the ?memory read? command may optionally have its prefetch turned off as specified in the pci bridge specification. when in pci-x mode, the inbound delayed/split transactions do not prefetch ? they acquire only the byte count from the request. table 629. terminations of completion required cycles to hub interface hub interface termination pci completion status register bits set successful successful none master abort (pci) target abort 1 received master abort (pri) signaled target abort (sec) master abort (pci-x) split master abort 2 received master abort (pri) ta rg e t ab o r t ta rg e t a bo rt ( p ci ) 1 split target abort (pci-x) 2 received target abort (pri) signaled target abort (sec) master and target abort ta rg e t a bo rt ( p ci ) 1 split target abort (pci-x) 2 received master abort (pri) received target abort (pri) signaled target abort (sec) notes: 1. the intel ? 6300ESB ich only signals target abort when the error has been logged from the hub interface before the initial connect by pci or when the pci master reconnects after a previous disconnect. when the intel ? 6300ESB ich receives an abort on the hub interface in the middle of a read completion stream it do es not interrupt the stream to signal target abort. 2. the intel ? 6300ESB ich issues a split completion error message with either master abort or target abort for the remaining completion sequ ence when an abort is detected on the hub interface. when several bytes of data returned successfully from the hub interface and have not yet been sent back on pci-x, when the abort is detected on the hub interface the intel ? 6300ESB ich stops the current sequence for that data (if it was running) and generates the split completion error message.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 699 18?intel ? 6300ESB ich 18.10.2 prefetch algorithm since outbound cycles are not prefetched, there is no algorithm. the algorithm for inbound cycles is below. note that the algorithm changes depending upon whether only one device is requesting or multiple devices are requesting. 18.10.2.1parameters parameters based upon the prefetch parameter registers at offset f8h ? ffh ri initial request size (bits[03:00]) ti initial threshold (bits[07:04]) rs subsequent request (bits [11:08]) ts subsequent threshold (bits[15:12]) d delay to wait between next ts (calculated). the value is ?rs:111? clocks. other algorithm parameters sb buffer size (either 1k or 2k, depending upon the delayed transaction bit (offset 40h, bit 2)) n data in buffer + data in flight (requested to sibus but not returned) b data in buffer 18.10.2.2algorithm (single device only) 1. establish dt, launch request of size ri. the actual amount fetched is such that the transfer ends on a naturally aligned 128-byte line. when the initial address is less than 64-bytes into the 128-byte line, the ri value is rounded down (i.e., eight 64- byte lines become seven 64-byte lines + remainder). when the initial address is more than 64-bytes into the 128-byte line, the ri value is rounded up (i.e., eight 64-byte lines become nine 64-byte lines + remainder). example 1: address starts at 32 bytes into a 128-byte line, and the fetch length is 4*64 byte lines (256 bytes). the amount fetched is 256 - 32 = 224 bytes (56 dwords). example 2: address starts at 96 bytes into a 128-byte line, and the fetch length is 4*64-byte lines (256 bytes). the amount fetched is 256 + (128 - 96) = 288 bytes (72 dwords). 2. wait until at least some data has returned and master has reconnected. in pci mode, this is when the first qword becomes available. in pci-x, when not running in 133 mhz mode, or running in 133 mhz mode but the request size is less than or equal to 256 bytes, this is when the first adb becomes available. 3. when n < ti, launch a request of size rs (truncated by sb, when necessary). start timer when there are not more active delayed transactions. when there are other active delayed transactions, go to step 5. 4. check for size b vs. ts when b < ts, wait for timer to expire before launch of size rs. restart timer. go to step 4. when b > ts before timer expires, reset timer. go to step 5.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 700 order number: 300641-004us 5. wait for b < ts; launch request of size rs (truncated by sb, when necessary). restart timer. go to step 4. 18.10.3 algorithm (multiple pci-x devices requesting) when multiple agents are requesting in pci-x mode, the definition of t s changes. instead of just indicating data in buffer, it becomes like t i , and represents data in buffer plus data in flight. when multiple agents are requesting in pci-x mode, the intel ? 6300ESB ich needs to switch between these agents for completions. it does this by utilizing its mlt parameter. when the mlt expires, it stops this stream and switches to another stream. differences from p64h algorithm: ? no connect threshold: as soon as the first data is available in the dt buffer, a pci device is allowed to connect. ? allows multiple outstanding reads per dt buffer, (so long as restrict size of all outstanding reads for a dt buffer to remaining capacity in dt buffer), yielding smaller prefetch overshoot ? periodic subsequent fetch: smaller, more frequent requests reduce prefetch overshoot ? t i and t s as a low watermark takes into account data in flight; not just data remaining in the dt buffer ? delayed subsequent launch for multi-stream operation to reduce prefetch overshoot ? first subsequent launch threshold 18.10.4 accesses from multiple agents to same 4k page in order to avoid the need to track the status of the buffers when multiple agents are asking for data from the same 4k page, the intel ? 6300ESB ich retries a pci master when the same pci master has already established another delayed transaction to that 4k page. 18.11 internal bus/device communication internally, all devices that reside on the ?logical pci bus? are connected to an internal bus called ?sibus? (silicon bus). this is a bus architecture developed within pcg that allows for high code reuse and the ability to connect multiple units together in a standard manner. it is split transaction based. by choosing this micro-architecture, cycles may originate from any agent and be decoded by any other agent. this allows peer-to-peer communication to effectively be free. for this reason, the sm bus controller is also connected to this bus, allowing pci configuration cycles that originate either from the hub interface or sm bus to use the same data and control paths to access internal registers. however, this must be monitored carefully by the micro-architecture. configuration cycles from sm bus must be allowed to reach their destination, even when the hub interface communication to one of the pci busses is blocked due to a deadlock condition. therefore, the micro-architecture must ensure the following:
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 701 18?intel ? 6300ESB ich ? all units that have a configuration space that could be accessed by sm bus have a ?1 command only? depth. this helps ensure that multiple requests are not outstanding, minimizing any possibility of sm bus accesses being stuck. ? the intel ? 6300ESB ich does not launch successive requests that have the same hub id/pipe id on the internal bus, ensuring that no space has to be reserved to re-order the completion data. only cycles that have a unique hub id/pipe id may be launched simultaneously, and their completions may return in any order. ? any request from sm bus (or the hub interface) that targets the i/oxapic must be able to complete, even when the i/oxapic has an interrupt to deliver to the hub interface. otherwise, the completion for the sm bus/hub interface access is blocked behind the i/oxapic request to the hub interface, and it does not finish. system management software must ensure that the sm bus does not generate accesses pci. when this occurs and pci is blocked, the sm bus is blocked. 18.12 data return behavior of hub interface initiated reads for all hub interface initiated memory read cycles targeting pci/pci-x, the intel ? 6300ESB ich ensures a return length of a naturally aligned 128-bytes. when a request is less than 128 bytes and within a single 128-byte line, the intel ? 6300ESB ich generates one completion. when the request crosses a line, the intel ? 6300ESB ich returns multiple completions, broken on 128-byte line boundaries, until the request is fulfilled. the intel ? 6300ESB ich does not return a dword completion on a memory read command that is longer than a dword and is qword aligned. the intel ? 6300ESB ich only generates qword aligned reads whose length is a multiple number of qwords. the intel ? 6300ESB ich requires that the completions for these requests be returned as qwords and never dwords. for read streaming to work, the intel ? 6300ESB ich requires that the driving agent only disconnect read completions on a cache line boundary (64 or 128 bytes). 18.13 performance targets 18.13.1 introduction this information is organized into three sections. the first section specifies general bus timings. the second specifies single active master throughputs. the third specifies concurrent performance when multiple agents are generating requests from both busses. 18.13.2 definitions and assumptions bandwidth tests are sustained throughput tests. the system may be run until it reaches steady state and then run longer with the bandwidth measured. the system under test uses 4x, 8 bit, hl 1.5. memory bandwidth in the system under test is sufficient to service the requirements of the pci-x so that contention for memory and other system resources is not a performance bottleneck.
intel ? 6300ESB ich?18 intel ? 6300ESB i/o controller hub ds november 2007 702 order number: 300641-004us references to signal timings are stated from the point of view of the bus itself. internal register timings of the individual devices are not considered. one megabyte =10 6 bytes rather than 2 20 bytes. 18.13.3 active master clock counts this section specifies clock counts for general bus timings and first word latencies for read requests. bus timings should be consistent regardless of other system activity. first word latency specifications only apply in situations where contention for system resources does not present a performance bottleneck. first word latency is measured as the number of clocks from the initial assertion of pxframe# (this is clock 0) to the first clock on which valid data is returned in response to the request.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 703 19?intel ? 6300ESB ich serial i/o unit 19 the siu is similar to currently available super i/o controllers. it is specifically designed for integration into the intel ? 6300ESB ich. it is connected externally through the lpc bus and consists of two uarts, a serial interrupt controller, port 60/64 emulation and the lpc interface. 19.1 features lpc interface ? multiplexed command, address and data bus ? 8-bit i/o transfers ? 16-bit address qualification for i/o transactions ? serial irq interface compatible with serialized irq support for pci systems note: each siu port must use a dedicated interrupt. siu interrupts cannot be shared with each other or with other devices. serial port ? two serial ports note: the serial ports of the intel? 6300ESB ich are not completely compatible with other 16550 standard devices. a system or software designer must follow the specifications laid out in this document above standard 16550 specifications. ? configurable i/o addresses and interrupts ? 16-byte fifos ? supports up to 115 kbps ? programmable baud rate generator ? modem control circuitry port 60/64 emulation ? configurable unit disable ? positive decode for i/o cycles to 60h and 64h ? read/write scratchpad registers only (sticky bits) ? configurable interrupt generation on writes to either register
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 704 order number: 300641-004us 19.2 pin description 19.2.1 universal asynchronous receive and transmit (uart0, uart1) figure 32. siu block diagram table 630. universal asynchronous receive and transmit (uart0, uart1) (sheet 1 of 2) signal name type description uart_clk i input clock to the siu. this clock is passed to the baud clock generation logic of each uart in the siu. siu0_rxd, siu1_rxd i serial inputs for uart0 and uart1: serial data input from device pin to the receive port. siu0_txd, siu1_txd o serial output for uart0 and uart1: serial data output to the communication peripheral/modem or data set. upon reset, the txd pins will be set to marking condition (logic ?1? state). lpc i/f registers control apb i/f sirq controller port 60/64 uart0 emulation uart1 siu_serirq
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 705 19?intel ? 6300ESB ich siu0_cts#, siu1_cts# i clear to send: active low, this pin indicates that data may be exchanged between the intel ? 6300ESB ich and external interface. these pins have no effect on the transmitter. note: these pins could be used as modem status input whose condition may be tested by the processor by reading bit 4 (cts) of the modem status register (msr). bit 4 is the complement of the cts# signal. bit 0 (dcts) of the msr indicates whether the cts# input has changed state since the previous reading of the msr. when the cts bit of the msr changes state an interrupt is generated if the modem status interrupt is enabled. siu0_dsr#, siu1_dsr# i data set ready for uart0 and uart1: active low, this pin indicates that the external agent is ready to communicate with the intel ? 6300ESB ich uarts. these pins have no effect on the transmitter. note: these pins could be used as modem status input whose condition may be tested by the processor by reading bit 5 (dsr) of the modem status register. bit 5 is the complement of the dsr# signal. bit 1 (ddsr) of the modem status register (msr) indicates whether the dsr# input has changed state since the previous reading of the msr. when the dsr bit of the msr changes state an interrupt is generated if the modem status interrupt is enabled. siu0_dcd#, siu1_dcd# i data carrier detect for uart0 and uart1: active low, this pin indicates that data carrier has been detected by the external agent. note: these pins are modem status input whose condition may be tested by the processor by reading bit 7 (dcd) of the modem status register (msr). bit 7 is the complement of the dcd# signal. bit 3 (ddcd) of the msr indicates whether the dcd# input has changed state since the previous reading of the msr. when the dcd bit of the msr changes from a ?1? to 0, an interrupt is generated if the modem status interrupt is enabled. siu0_ri# siu1_ri# i ring indicator for uart0 and uart1: active low, this pin indicates that a telephone ringing signal has been received by the external agent. note: these pins are modem status input whose condition may be tested by the processor by reading bit 6 (ri) of the modem status register (msr). bit 6 is the complement of the ri# signal. bit 2 (teri) of the msr indicates whether the ri# input has transition back to an inactive state. when the ri bit of the msr changes state an interrupt is generated if the modem status interrupt is enabled. siu0_dtr#, siu1_dtr# o data terminal ready for uart0 and uart1: when low these pins informs the modem or data set that the intel ? 6300ESB ich uart0 and uart1 are ready to establish a communication link. the dtr#x(x=0,1) output signals may be set to an active low by programming the dtrx (x-0,1) (bit0) of the modem control register to a logic ?1?. a reset operation sets this signal to its inactive state (logic ?1?). loop mode operation holds this signal in its inactive state. siu0_rts#, siu1_rts# o request to send for uart0 and uart1: when low these pins informs the modem or data set that intel ? 6300ESB ich uart0 and uart1 are ready to establish a communication link. the rts#x(x=0,1) output signals may be set to an active low by programming the rtsx (x-0,1) (bit1) of the modem control register to a logic ?1?. a reset operation sets this signal to its inactive state (logic ?1?). loop mode operation holds this signal in its inactive state. table 630. universal asynchronous receive and transmit (uart0, uart1) (sheet 2 of 2) signal name type description
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 706 order number: 300641-004us 19.3 functional description 19.3.1 host processor interface (lpc) the host processor communicates with the siu through the lpc bus. access is through a series of read/write registers and accomplished through i/o cycles or dma transfers. all registers are 8 bits wide. the siu registers include global configuration space and device specific regions accessed by setting the logical device number in the siu configuration register 07h (scr7). see table 631 . see section 19.8, ?configuration? for configuration register descriptions and setting the base address. 19.4 lpc interface the lpc interface is used to control all the logical blocks on the siu. lpc bus signals use pci 33 mhz electrical signal characteristics. refer to the low pin count (lpc) interface specification, rev 1.0. 19.4.1 lpc cycles the following cycle types are supported by the lpc protocol. the siu ignores cycles that it does not support. 19.4.1.1 i/o read and write cycles the siu is the target for i/o cycles. i/o cycles are initiated by the host for register or fifo accesses and will generally have minimal sync times. data transfers are assumed to be exactly 1-byte. if the processor requested a 16- or 32-bit transfer, the host must break it up into 8-bit transfers. see the low pin count (lpc) interface specification for the sequence of cycles for the i/o read and write cycles. table 631. address map address block name logical device 04eh configuration index 04fh configuration data base+(0-7) serial port com 1 04h base+(0-7) serial port com 2 05h 060h/064h port 60/64 emulation 07h table 632. supported lpc cycle types cycle type transfer size i/o write 1 byte i/o read 1 byte
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 707 19?intel ? 6300ESB ich 19.4.2 reset policy the following rules govern the reset policy: ? the siu reset (active low) is internally tied to the pci bus reset. ? when the siu reset goes active (low): ? the host drives the lframe# signal high, tristates the lad[3:0] signals, and ignores the ldrq# signal. ? the siu ignores lframe#, tristates the lad[3:0] pins and drives the siu?s ldrq# signal inactive (high). note: lpc bus signals from siu are tied to primary lpc interface external to the intel ? 6300ESB ich device. host lpc and siu lpc names are used interchangeably throughout. 19.4.3 lpc transfers 19.4.3.1 i/o transfers these will generally be used for register or fifo accesses, and will generally have minimal sync times. the minimum number of wait-states between bytes is 1. data transfers are assumed to be exactly 1 byte. the host is responsible for breaking up larger data transfers into 8 bit cycles. 19.5 logical device 4 and 5: serial ports (uarts) this section describes the universal asynchronous receiver/transmitter (uart) serial port used for the two uarts integrated into the siu. the uart may be controlled through programmed i/o. the basic programming model is the same for both uarts with the only difference being the logical device number assigned to each. 19.5.1 overview the serial port consists of a uart which supports all the functions of a standard 16550 uart including hardware flow control interface. the uart performs serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the processor. the processor may read the complete status of the uart at any time during the functional operation. available status information includes the type and condition of the transfer operations being performed by the uart and any error conditions (parity, overrun, framing, or break interrupt). table 633. i/o sync bits description bits indication 0000 sync achieved with no error. 0101 indicates that sync not achieved yet, but the part is driving the bus. 0110 indicates that sync not achieved yet, but the part is driving the bus, and expect long sync. 1010 special case: peripheral indicating errors.
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 708 order number: 300641-004us the serial port may operate in either fifo or non-fifo mode. in fifo mode, a 16-byte transmit fifo holds data from the processor to be transmitted on the serial link and a 16-byte receive fifo buffers data from the serial link until read by the processor. each uart includes a programmable baud rate generator which is capable of dividing the baud clock input by divisors of 1 to (2 16 -1) and producing a 16x clock to drive the internal transmitter and receiver logic. each uart has complete modem control capability and a processor interrupt system. interrupts may be programmed to the user's requirements, minimizing the computing required to handle the communications link. each uart may operate in a polled or an interrupt driven environment as configured by software. the baud rate generator input is a function of the uart_clk and a configurable pre- divide of 1, 8, or 26. see also siu configuration (address 29h) in table 656 . the output of the baud rate generator is 16 times the baud rate. 19.5.1.1 uart feature list ? adds or deletes standard asynchronous communications bits (start, stop, and parity) to or from the serial data ? independently controlled transmit, receive, line status and data set interrupts ? programmable baud rate generator allows division of clock by 1 to (2 16 -1) and generates an internal 16x clock ? modem control functions (cts#, rts#, dsr#, dtr#, ri#, and dcd#) ? fully programmable serial-interface characteristics: table 634. uart clock divider support clock frequency 14.7456 mhz 48.0 mhz pre-divide value 826 generator frequency 1.8432 mhz 1.8462 mhz note: some clock chips provide a 14.318x mhz clock output. the intel ? 6300ESB ich?s uart clock must use a 14.7456 mhz frequency; most clock chips do not provide this frequency. an option will be to use the 48.0 mhz clock. table 635. baud rate examples desired baud rate uart clock frequency 14.7456 mhz uart clock frequency 48 mhz divisor divisor % error 1200 768 2500 0.16 2400 384 1250 0.16 4800 192 625 0.16 7200 128 417 0.16 9600 96 312 0.16 19200 48 156 0.16 38400 24 78 0.16 56000 16 54 3 115200 8 26 0.16
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 709 19?intel ? 6300ESB ich ? 5, 6, 7 or 8-bit characters ? even, odd, or no parity detection ? 1, 1-1/2, or 2 stop bit generation ? baud rate generation (up to 115kbps) ? false start bit detection ? 16-byte receive fifo ? complete status reporting capability ? line break generation and detection ? internal diagnostic capabilities include: ? loopback controls for communications link fault isolation ? break, parity, overrun, and framing error simulation ? fully prioritized interrupt system controls 19.5.1.2 uart operational description the format of a uart data frame is shown in figure 33 . each data frame is between 7 bits and 12 bits long depending on the size of data programmed, if parity is enabled and if two stop bits are selected. the frame begins with a start bit that is represented by a high to low transition. next, either 5 to 8 bits of data are transmitted, beginning with the least significant bit. an optional parity bit follows, which is set if even parity is enabled and an odd number of ?1?s exist within the data byte, or if odd parity is enabled and the data byte contains an even number of ?1?s. the data frame ends with one, one and a half or two stop bits as programmed by the user, which is represented by one or two successive bit periods of a logic ?1?. the unit is disabled upon reset, the user needs to enable the unit by setting bit 6 of interrupt enable register. when the unit is enabled, the receiver starts looking for the start bit of a frame; the transmitter starts transmitting data to the transmit data pin if there is data available in the transmit fifo. transmit data may be written to the fifo before the unit is enabled. when the unit is disabled, the transmitter/receiver finishes the current byte being transmitted/received if it is in the middle of transmitting/ receiving a byte and stops transmitting/receiving more data. an siu reset will force the internal register and output signals on the serial port to the values listed in table 636 . figure 33. example uart data frame star t bit dat a<0 > dat a<1 > dat a<2 > dat a<3 > dat a<4 > dat a<5 > dat a<6 > dat a<7 > parit y bit stop bit 1 stop bit 2 txd3 or rxd3 pin lsb msb receive data sample counter frequency = 16x bit frequency, each bit is sampled three times in the middle. shaded bits are optional and may be programmed by users.
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 710 order number: 300641-004us 19.5.1.3 internal register descriptions there are 12 registers in the uart. these registers share eight address locations in the i/o address space. table 637 shows the registers and their addresses as offsets of a base address. note that the state of the divisor latch bit (dlab), which is the most significant bit of the serial line control register, affects the selection of certain of the uart registers. the dlab bit must be set high by the system software to access the baud rate generator divisor latches. table 636. siu signal reset states register/signal reset control reset state interrupt enable register reset all bits are low. interrupt id register reset bit 0 is forced high. bits 1-3 and 6-7 are forced low. bits 4-5 are permanently low. line control register reset all bits are forced low. line status register reset bits 0-4, and 7 are forced low. bits 5 and 6 are forced high. modem control register reset bits 0, 1, 2, 3, 4 are forced low. bits 5, 6, and 7 are permanently low. modem status register reset/modem signal, read msr for bits 3-0. low siu0_txd siu1_txd reset high siu_serirq reset/ clear line status reg low siu0_rts# siu1_rts# reset high siu0_dtr# siu1_dtr# reset high table 637. internal register descriptions uart register addresses (base + offset) dlab bit value register accessed base 0 receive buffer (read only) base 0 transmit buffer (write only) base + 01h 0 interrupt enable (r/w) base + 02h x interrupt i.d. (read only) base + 02h x fifo control (write only) base + 03h x line control (r/w) base + 04h x modem control (r/w) base + 05h x line status (read only) base + 06h x modem status (read only) base + 07h x scratch pad (r/w) base 1 divisor latch (lower byte, r/w) base + 01h 1 divisor latch (upper byte, r/w)
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 711 19?intel ? 6300ESB ich 19.5.1.3.1 receive buffer register (rbr) in non-fifo mode, this register holds the character received by the uart's receive shift register. if fewer than eight bits are received, the bits are right-justified and the leading bits are zeroed. reading the register empties the register and resets the data ready (dr) bit in the line status register to 0. other (error) bits in the line status register are not cleared. in fifo mode, this register latches the value of the data byte at the top of the fifo. 19.5.1.3.2 transmit holding register (thr) this register holds the next data byte to be transmitted. when the transmit shift register becomes empty, the contents of the transmit holding register are loaded into the shift register and the transmit data request (tdrq) bit in the line status register is set to ?1?. in fifo mode, writing to thr puts data to the top of the fifo. the data at the bottom of the fifo is loaded to the shift register when it is empty. 19.5.1.3.3 interrupt enable register (ier) this register enables five types of interrupts which independently activate the int signal and set a value in the interrupt identification register. each of the five interrupt types may be disabled by resetting the appropriate bit of the ier register. similarly, by setting the appropriate bits, selected interrupts may be enabled. receiver time out interrupt may be configured to be separated from the receive data available interrupt (using the bit5: comp) to avoid interrupt controller and dma controller serving the receive fifo at the same time. note: the use of bit 4 and 5 is different from the register definition of standard 16550. table 638. receive buffer register (rbr) receive buffer register rbr read only address: reset state: access: base (dlab=0) 00h 8-bit bit number bit mnemonic function 7:0 rb[7:0] data byte received, least significant bit first. table 639. transmit holding register (thr) transmit holding register thr write only address: reset state: access: base (dlab=0) 00h 8 bit bit number bit mnemonic function 7:0 tb[7:0] data byte transmitted, least significant bit first.
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 712 order number: 300641-004us 19.5.1.3.4 interrupt identification register (iir) in order to minimize software overhead during data character transfers, the uart prioritizes interrupts into four levels (listed in table 641 ) and records these in the interrupt identification register. the interrupt identification register (iir) stores information indicating that a prioritized interrupt is pending and the source of that interrupt. table 640. interrupt enable register (ier) interrupt enable register ier read/write address: reset state: access: base + 01h (dlab=0) 00h 8-bit bit number bit mnemonic function 7:6 rsvd rsvd = 0 5comp compatibility enable: 0 = bit 0 of this register also controls rtoie and bit 4 is rsvd. 1 = bit 4 of this register controls rtoie. note: the use of bit 5 is different from the register definition of the 16550. the 16550 has this bit always set to 0. 4rtoie receiver time out interrupt enable: 0 = receiver data time out interrupt disabled. 1 = receiver data time out interrupt enabled. note: the use of bit 4 is different from the register definition of the 16550. the 16550 has this bit always set to 0. 3mie modem interrupt enable: 0 = modem status interrupt disabled. 1 = modem status interrupt enabled. 2rlse receiver line status interrupt enable: 0 = receiver line status interrupt disabled. 1 = receiver line status interrupt enabled. 1tie transmit data request interrupt enable: 0 = transmit fifo data request interrupt disabled. 1 = transmit fifo data request interrupt enabled. 0ravie receiver data available interrupt enable: when bit 5 = 1 0 = receiver data available (trigger level reached) interrupt disabled. 1 = receiver data available (trigger level reached) interrupt enabled. when bit 5 = ?0? the following additional functionality is used. 0 = receiver data time out interrupt also disabled. 1 = receiver data time out interrupt enabled.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 713 19?intel ? 6300ESB ich table 641. interrupt conditions priority level interrupt origin 1 (highest) receiver line status: one or more error bits were set. 2 received data is available. in fifo mode, trigger level was reached; in non-fifo mode, rbr has data. 2 receiver time out occurred. it happens in fifo mode only, when there is data in the receive fifo but no activity for a time period. 3 transmitter requests data. in fifo mode, the transmit fifo is half or more than half empty; in non-fifo mode, thr is read already. 4 modem status: one or more of the modem input signals has changed state. table 642. interrupt identification register (iir) interrupt identification register iir read-only address: reset state: access: base + 02h 01h 8-bit bit number bit mnemonic function 7:6 fifoes[1:0] fifo mode enable status: 00 = non-fifo mode is selected. 01 = reserved 10 = reserved 11 = fifo mode is selected (trfifoe = 1). 5:4 -- reserved 3 tod (iid3) time out detected: 0 = no time out interrupt is pending. 1 = time out interrupt is pending. (fifo mode only) 2:1 iid[2:1] interrupt source encoded: 00 = modem status (cts, dsr, ri, dcd modem signals changed state) 01 = transmit fifo requests data. 10 = received data available 11 = receive error (overrun, parity, framing, break, fifo error) 0 ip# interrupt pending: 0 = interrupt is pending. (active low) 1 = no interrupt is pending.
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 714 order number: 300641-004us 19.5.1.3.5 fifo control register (fcr) fcr is a write only register that is located at the same address as the iir (iir is a read only register). fcr enables/disables the transmitter/receiver fifos, clears the transmitter/receiver fifos, and sets the receiver fifo trigger level. note: the use of bit 6 and 7 is different from the register definition of standard 16550. table 643. interrupt identification register decode interrupt id bits interrupt set/reset function 3 210 priority type source reset control 0 001 - none no interrupt is pending. - 0 110 highes t receiver line status overrun error, parity error, framing error, break interrupt. reading the line status register. 0 100 secon d highes t received data available. non-fifo mode: receive buffer is full. non-fifo mode: reading the receiver buffer register. fifo mode: trigger level was reached. fifo mode: reading bytes until receiver fifo drops below trigger level or setting resetrf bit in fcr register. 1 100 secon d highes t character timeout indication. fifo mode only: at least one character is in receiver fifo and there was no activity for a time period. reading the receiver fifo or setting resetrf bit in fcr register. 0 010 third highes t transmit fifo data request non-fifo mode: transmit holding register empty reading the iir register (if the source of the interrupt) or writing into the transmit holding register. fifo mode: transmit fifo has half or less than half data. reading the iir register (if the source of the interrupt) or writing to the transmitter fifo. 0000 fourth highes t modem status clear to send, data set ready, ring indicator, received line signal detect reading the modem status register table 644. fifo control register (fcr) (sheet 1 of 2) fifo control register fcr write-only address: reset state: access: base + 02h 00h 8-bit bit number bit mnemonic function 7:6 itl[1:0] interrupt trigger level: when the number of bytes in the receiver fifo equals the interrupt trigger level programmed into this field and the received data available interrupt is enabled (through ier), an interrupt is generated and appropriate bits are set in the iir. 00 = 1 byte or more in fifo causes interrupt (same as 16550). 01 = rsvd 10 = 8 bytes or more in fifo causes interrupt and dma request (same as 16550). 11 = rsvd
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 715 19?intel ? 6300ESB ich 19.5.1.3.6 line control register (lcr) in the line control register (lcr), the system programmer specifies the format of the asynchronous data communications exchange. the serial data format consists of a start bit (logic 0), five to eight data bits, an optional parity bit, and one or two stop bits (logic 1). the lcr has bits for accessing the divisor latch and causing a break condition. the programmer may also read the contents of the line control register. the read capability simplifies system programming and eliminates the need for separate storage in system memory. 5:3 ? reserved 2 resettf reset transmitter fifo: when resettf is set to 1, the transmitter fifo counter logic is set to 0, effectively clearing all the bytes in the fifo. the tdrq bit in lsr are set and iir shows a transmitter requests data interrupt if the tie bit in the ier register is set. the transmitter shift register is not cleared; it completes the current transmission. after the fifo is cleared, resettf is automatically reset to 0. 0 = writing ?0? has no effect. 1 = the transmitter fifo is cleared (fifo counter set to 0). after clearing, bit is automatically reset to 0. 1 resetrf reset receiver fifo: when resetrf is set to 1, the receiver fifo counter is reset to 0, effectively clearing all the bytes in the fifo. the dr bit in lsr is reset to 0. all the error bits in the fifo and the fifoe bit in lsr are cleared. any error bits, oe, pe, fe or bi, that had been set in lsr are still set. the receiver shift register is not cleared. if iir had been set to received data available, it is cleared. after the fifo is cleared, resetrf is automatically reset to 0. 0 = writing ?0? has no effect. 1 = the receiver fifo is cleared (fifo counter set to 0). after clearing, bit is automatically reset to 0. 0trfifoe transmit and receive fifo enable: trfifoe enables/disables the transmitter and receiver fifos. when trfifoe = 1, both fifos are enabled (fifo mode). when trfifoe = 0, the fifos are both disabled (non-fifo mode). writing a ?0? to this bit clears all bytes in both fifos. when changing from fifo mode to non- fifo mode and vice versa, data is automatically cleared from the fifos. this bit must be 1 when other bits in this register are written or the other bits are not programmed. 0 = fifos are disabled. 1 = fifos are enabled. table 644. fifo control register (fcr) (sheet 2 of 2) fifo control register fcr write-only address: reset state: access: base + 02h 00h 8-bit bit number bit mnemonic function
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 716 order number: 300641-004us table 645. line control register (lcr) (sheet 1 of 2) serial line control register lcr read/write address: reset state: access: base + 03h 00h 8-bit bit number bit mnemonic function 7dlab divisor register access bit: this bit is the divisor latch access bit. it must be set high (logic 1) to access the divisor latches of the baud rate generator during a read or write operation. it must be set low (logic 0) to access the receiver buffer, the transmit holding register, or the interrupt enable register. 0 = access transmit holding register (thr), receive buffer register (rbr) and interrupt enable register. 1 = access divisor latch registers (dll and dlm) 6 sb set break: this bit is the set break control bit. it causes a break condition to be transmitted to the receiving uart. when sb is set to a logic 1, the serial output (txd) is forced to the spacing (logic 0) state and remains there until sb is set to a logic 0. this bit acts only on the txd pin and has no effect on the transmitter logic. this feature enables the processor to alert a terminal in a computer communications system. if the following sequence is executed, no erroneous characters will be transmitted because of the break: ? load 00h in the transmit holding register in response to a tdrq interrupt ? after tdrq goes high (indicating that 00h is being shifted out), set the break bit before the parity or stop bits reach the txd pin ? wait for the transmitter to be idle (temt = 1) and clear the break bit when normal transmission has to be restored during the break, the transmitter may be used as a character timer to accurately establish the break duration. in fifo mode, wait for the transmitter to be idle (temt=1) to set and clear the break bit. 0 = no effect on txd output. 1 = forces txd output to ?0? (space). 5stkyp sticky parity: this bit is the ?sticky parity? bit, which may be used in multiprocessor communications. when pen and stkyp are logic 1, the bit that is transmitted in the parity bit location (the bit just before the stop bit) is the complement of the eps bit. if eps is 0, the bit at the parity bit location will be transmitted as a 1. in the receiver, if stkyp and pen are 1, the receiver compares the bit that is received in the parity bit location with the complement of the eps bit. if the values being compared are not equal, the receiver sets the parity error bit in lsr and causes an error interrupt if line status interrupts were enabled. for example, if eps is 0, the receiver expects the bit received at the parity bit location to be 1. if it is not, then the parity error bit is set. by forcing the bit value at the parity bit location, rather than calculating a parity value, a system with a master transmitter and multiple receivers may identify some transmitted characters as receiver addresses and the rest of the characters as data. if pen = 0, stkyp is ignored. 0 = no effect on parity bit. 1 = forces parity bit to be opposite of eps bit value.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 717 19?intel ? 6300ESB ich 19.5.1.3.7 line status register (lsr) this register provides status information to the processor concerning the data transfers. bits 5 and 6 show information about the transmitter section. the rest of the bits contain information about the receiver. in non-fifo mode, three of the lsr register bits, parity error, framing error, and break interrupt, show the error status of the character that has just been received. in fifo mode, these three bits of status are stored with each received character in the fifo. lsr shows the status bits of the character at the top of the fifo. when the character at the top of the fifo has errors, the lsr error bits are set and are not cleared until software reads lsr, even if the character in the fifo is read and a new character is now at the top of the fifo. bits 1 through 4 are the error conditions that produce a receiver line status interrupt when any of the corresponding conditions are detected and the interrupt is enabled. these bits are not cleared by reading the erroneous byte from the fifo or receive buffer. they are cleared only by reading lsr. in fifo mode, the line status interrupt 4eps even parity select: this bit is the even parity select bit. when pen is a logic ?1? and eps is a logic ?0?, an odd number of logic ?1?s is transmitted or checked in the data word bits and the parity bit. when pen is a logic ?1? and eps is a logic ?1?, an even number of logic ones is transmitted or checked in the data word bits and parity bit. if pen = 0, eps is ignored. 0 = sends or checks for odd parity. 1 = sends or checks for even parity. 3pen parity enable: this is the parity enable bit. when pen is a logic ?1?, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd number of ?1?s when the data word bits and the parity bit are summed.) 0 = no parity function 1 = allows parity generation and checking. 2stb stop bits: this bit specifies the number of stop bits transmitted and received in each serial character. if stb is a logic ?0?, one stop bit is generated in the transmitted data. if stb is a logic ?1? when a 5-bit word length is selected through bits ?0? and ?1?, then one and one half stop bits are generated. if stb is a logic ?1? when either a 6, 7, or 8-bit word is selected, then two stop bits are generated. the receiver checks the first stop bit only, regardless of the number of stop bits selected. 0 = 1 stop bit 1 = 2 stop bits, except for 5-bit character then 1-1/2 bits 1:0 wls[1:0] word length select: the word length select bits specify the number of data bits in each transmitted or received serial character. 00 = 5-bit character (default) 01 = 6-bit character 10 = 7-bit character 11 = 8-bit character table 645. line control register (lcr) (sheet 2 of 2) serial line control register lcr read/write address: reset state: access: base + 03h 00h 8-bit bit number bit mnemonic function
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 718 order number: 300641-004us occurs only when the erroneous byte is at the top of the fifo. if the erroneous byte being received is not at the top of the fifo, an interrupt is generated only after the previous bytes are read and the erroneous byte is moved to the top of the fifo. table 646. line status register (lsr) (sheet 1 of 2) line status register lsr read-only address: reset state: access: base + 05h 60h 8-bit bit number bit mnemonic function 7fifoe fifo error status: in non-fifo mode, this bit is 0. in fifo mode, fifoe is set to ?1? when there is at least one parity error, framing error, or break indication for any of the characters in the fifo. note that a processor read to the line status register does not reset this bit. fifoe is reset when all error bytes have been read from the fifo. fifoe set to ?1? does not generate interrupt. 0 = no fifo or no errors in receiver fifo. 1 = at least one character in receiver fifo has errors. 6temt transmitter empty: temt is set to a logic ?1? when the transmit holding register and the transmitter shift register are both empty. it is reset to a logic ?0? when either the transmit holding register or the transmitter shift register contains a data character. in fifo mode, temt is set to ?1? when the transmitter fifo and the transmit shift register are both empty. 5trdq transmit data request: tdrq indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the processor when the transmit data request interrupt enable is set high and generates the dma request to dma controller to ask for data. the tdrq bit is set to a logic ?1? when a character is transferred from the transmit holding register into the transmit shift register. the bit is reset to logic ?0? concurrently with the loading of the transmit holding register by the processor. in fifo mode, tdrq is set to ?1? when the transmit fifo is empty or the resettf bit in fcr has been set to 1. it is cleared when at least one byte is written to the transmit fifo. if more than 16 characters are loaded into the fifo, the excess characters are lost. 0 = processor has loaded the transmit holding register. 1 = transmit fifo is empty (fifo mode) or a character has transferred from the transmit holding register into the transmit shift register. 4bi break interrupt: bi is set to a logic ?1? when the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits). the break indicator is reset when the processor reads the line status register. in fifo mode, only one character (equal to 00h), is loaded into the fifo regardless of the length of the break condition. bi shows the break condition for the character at the top of the fifo, not the most recently received character. 0 = no break signal has been received. 1 = break signal occurred
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 719 19?intel ? 6300ESB ich 19.5.1.3.8 modem control register (mcr) this 8-bit register controls the interface with the modem or data set (or a peripheral device emulating a modem). the contents of the modem control register are described in table 647 . 3fe framing error: fe indicates that the received character did not have a valid stop bit. fe is set to a logic ?1? when the bit following the last data bit or parity bit is detected as a logic ?0? bit (spacing level). if the line control register had been set for two stop bit mode, the receiver does not check for a valid second stop bit. the fe indicator is reset when the processor reads the line status register. the uart will resynchronize after a framing error. to do this it assumes that the framing error was due to the next start bit, so it samples this ?start? bit twice and then takes in the ?data?. in fifo mode, fe shows a framing error for the character at the top of the fifo, not for the most recently received character. 0 = no framing error 1 = invalid stop bit has been detected. 2pe parity error: pe indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. the pe is set to a logic ?1? upon detection of a parity error and is reset to a logic ?0? when the processor reads the line status register. in fifo mode, pe shows a parity error for the character at the top of the fifo, not the most recently received character. 0 = no parity error 1 = parity error has occurred. 1oe overrun error: in non-fifo mode, oe indicates that data in the receiver buffer register was not read by the processor before the next character was transferred into the receiver buffer register, thereby destroying the previous character. in fifo mode, oe indicates that all 16 bytes of the fifo are full and the most recently received byte has been discarded. the oe indicator is set to a logic ?1? upon detection of an overrun condition and reset when the processor reads the line status register. 0 = no data has been lost 1 = received data has been lost. 0dr data ready: bit 0 is set to a logic ?1? when a complete incoming character has been received and transferred into the receiver buffer register or the fifo. in non-fifo mode, dr is reset to ?0? when the receive buffer is read. in fifo mode, dr is reset to a logic ?0? if the fifo is empty (last character has been read from rbr) or the resetrf bit is set in fcr. 0 = no data has been received. 1 = data is available in rbr or the fifo. table 646. line status register (lsr) (sheet 2 of 2) line status register lsr read-only address: reset state: access: base + 05h 60h 8-bit bit number bit mnemonic function
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 720 order number: 300641-004us table 647. modem control register (mcr) (sheet 1 of 2) modem control register mcr read/write address: reset state: access: base + 04h 00h 8-bit bit number bit mnemonic function 7:5 0 reserved 4loop loop back test mode: this bit provides a local loopback feature for diagnostic testing of the uart. when loop is set to a logic 1, the following will occur: the transmitter serial output is set to a logic ?1? state. the out2# signal is forced to a logic ?1? state. the receiver serial input is disconnected from the pin. the output of the transmitter shift register is ?looped back? into the receiver shift register input. the four modem control inputs (cts#, dsr#, dcd#, and ri#) are disconnected from the pins and the modem control output pins (rts# and dtr#) are forced to their inactive state. ? coming out of the loopback test mode may result in unpredictable activation of the delta bits (bits 3:0) in the modem status register (msr). it is recommended that msr be read once to clear the delta bits in the msr. the lower four bits of the modem control register are connected to the upper four modem status register bits: ? dtr = ?1? forces dsr to a '1' ? rts = ?1? forces cts to a '1' ? out1 = ?1? forces ri to a '1' ? out2 = ?1? forces dcd to a '1' in the diagnostic mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the uart. the transmit, receive and modem control interrupts are operational, except the modem control interrupts are activated by control register bits, not the modem control inputs. a break signal may also be transferred from the transmitter section to the receiver section in loopback mode. 0 = normal uart operation 1 = test mode uart operation 3out2 out2# signal control: this bit controls the out2# output. when the out2 bit is set, out2# is asserted low. when the out2 bit is cleared, out2# is deasserted (set high). outside of the uart module, the out2# signal is used to connect the uart's interrupt output to the interrupt controller unit. 0 = out2# signal is '1' , which disables the uart interrupt. 1 = out2# signal is ?0?. 2out1 test bit: this bit is used only in loopback test mode. see (loop) above. 1rts request to send: this bit controls the request to send (rts#) output pin. bit ?1? affects the rts# output in a manner identical to that described below for the dtr bit. 0 = rts# pin is 1 1 = rts# pin is 0
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 721 19?intel ? 6300ESB ich 19.5.1.3.9 modem status register (msr) this 8 bit register provides the current state of the control lines from the modem or data set (or a peripheral device emulating a modem) to the processor. in addition to this current state information, four bits of the modem status register provide change information. these bits, 3:0, are set to a logic ?1? when a control input from the modem changes state. they are reset to a logic ?0? when the processor writes ?1?s to the bits of the modem status register. when bits 0, 1, 2, or 3 are set to logic 1, a modem status interrupt is generated if bit 3 of the interrupt enable register is set. 0dtr data terminal ready: this bit controls the data terminal ready output. when bit 0 is set to a logic ?1?, the dtr# output is force to a logic ?0?. when bit 0 is reset to a logic ?0?, the dtr# output pin is forced to a logic ?1?. ? the dtr# output of the uart may be applied to an eia inverting line driver (such as the ds1488) to obtain the proper polarity input at the succeeding modem or data set. 0 = dtr# pin is 1 1 = dtr# pin is 0 table 647. modem control register (mcr) (sheet 2 of 2) table 648. modem status register (msr) (sheet 1 of 2) modem status register msr read only address: reset state: access: base + 06h 00h 8-bit bit number bit mnemonic function 7dcd data carrier detect: this bit is the complement of the data carrier detect (dcd#) input. this bit is equivalent to bit out2 of the modem control register if loop in the mcr is set to 1. 0 = dcd# pin is 1 1 = dcd# pin is 0 6ri ring indicator: this bit is the complement of the ring indicator (ri#) input. this bit is equivalent to bit out1 of the modem control register if loop in the mcr is set to 1. 0 = ri# pin is 1 1 = ri# pin is 0 5dsr data set ready: this bit is the complement of the data set ready (dsr#) input. this bit is equivalent to bit dtr of the modem control register if loop in the mcr is set to 1. 0 = dsr# pin is 1 1 = dsr# pin is 0 4cts clear to send: this bit is the complement of the clear to send (cts#) input. this bit is equivalent to bit rts of the modem control register if loop in the mcr is set to 1. 0 = cts# pin is 1 1 = cts# pin is 0 3ddcd delta data carrier detect: 0 = no change in dcd# pin since last read of msr. 1 = dcd# pin has changed state.
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 722 order number: 300641-004us 19.5.1.3.10scratchpad register (scr) this 8-bit read/write register has no effect on the uart. it is intended as a scratchpad register for use by the programmer. 19.5.1.3.11programmable baud rate generator the uart contains a programmable baud rate generator that is capable of taking the uart_clk input and dividing it by any divisor from 1 to (2 16 -1). the output frequency of the baud rate generator is 16 times the baud rate. two 8-bit latches store the divisor in a 16-bit binary format. these divisor latches must be loaded during initialization to ensure proper operation of the baud rate generator. if both divisor latches are loaded with 0, the 16x output clock is stopped. upon loading either of the divisor latches, a 16-bit baud counter is immediately loaded. this prevents long counts on initial load. access to the divisor latch may be done with a word write. the baud rate of the data shifted in/out of the uart is given by: baudrate = uart_clk(mhz)/[16x divisor] for example, if uart_clk is 14.7456mhz and the divisor is 96, the baud rate is 9600. a divisor value of 0 in the divisor latch register is not allowed. the reset value of the divisor is 02. 2teri trailing edge ring indicator: 0 = ri# pin has not changed from ?0? to ?1? since last read of msr. 1 = ri# pin has changed from ?0? to 1. 1ddsr delta data set ready: 0 = no change in dsr# pin since last read of msr. 1 = dsr# pin has changed state. 0dcts delta clear to send: 0 = no change in cts# pin since last read of msr. 1 = cts# pin has changed state. table 648. modem status register (msr) (sheet 2 of 2) table 649. scratch pad register (scr) scratch pad register scr read/write address: reset state: access: base + 07h 00h 8-bit bit number bit mnemonic function 7:0 sp[7:0] no effect on uart functionality table 650. divisor latch register low (dll) divisor latch register low dll read/write address: reset state: access: base (dlab=1) 02h 8-bit bit number bit mnemonic function 7:0 br[7:0] low byte compare value to generate baud rate
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 723 19?intel ? 6300ESB ich 19.5.1.4 fifo operation 19.5.1.4.1 fifo interrupt mode operation receiver interrupt when the receive fifo and receiver interrupts are enabled (fcr[0]=1 and ier[0]=1), receiver interrupts occur as follows: ? the receive data available interrupt is invoked when the fifo has reached its programmed trigger level. the interrupt is cleared when the fifo drops below the programmed trigger level. ? the iir receive data available indication also occurs when the fifo trigger level is reached, and like the interrupt, the bits are cleared when the fifo drops below the trigger level. ? the receiver line status interrupt (iir = c6h), as before, has the highest priority. the receiver data available interrupt (iir=c4h) is lower. the line status interrupt occurs only when the character at the top of the fifo has errors. ? the data ready bit (dr in lsr register) is set to ?1? as soon as a character is transferred from the shift register to the receive fifo. this bit is reset to ?0? when the fifo is empty. character timeout interrupt when the receiver fifo and receiver time out interrupt are enabled, a character timeout interrupt occurs when all of the following conditions exist: ? at least one character is in the fifo. ? the last received character was longer than four continuous character times ago (if 2 stop bits are programmed the second one is included in this time delay). ? the most recent processor read of the fifo was longer than four continuous character times ago. ? the receiver fifo trigger level is greater than one. the maximum time between a received character and a timeout interrupt is 160 ms at 300 baud with a 12-bit receive character (i.e., 1 start, 8 data, 1 parity, and 2 stop bits). when a time out interrupt occurs, it is cleared and the timer is reset when the processor reads one character from the receiver fifo. if a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or after the processor reads the receiver fifo. transmit interrupt when the transmitter fifo and transmitter interrupt are enabled (fcr[0]=1, ier[1]=1), transmit interrupts occur as follows: ? the transmit data request interrupt occurs when the transmit fifo is half empty or more than half empty. the interrupt is cleared as soon as the transmit holding table 651. divisor latch register high (dlh) divisor latch register high dlh read/write address: reset state: access: base + 1 (dlab=1) 00h 8-bit bit number bit mnemonic function 7:0 br[15:8] high byte compare value to generate baud rate
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 724 order number: 300641-004us register is written (1 to 16 characters may be written to the transmit fifo while servicing the interrupt) or the iir is read. 19.5.1.4.2 fifo polled mode operation with the fifos enabled (trfifoe bit of fcr set to 1), setting ier[3:0] to all zeros puts the serial port in the fifo polled mode of operation. since the receiver and the transmitter are controlled separately, either one or both may be in the polled mode of operation. in this mode, software checks receiver and transmitter status through the lsr. as stated in the register description: ? lsr[0] is set as long as there is one byte in the receiver fifo. ? lsr[1] through lsr[4] specify which error(s) has occurred for the character at the top of the fifo. character error status is handled the same way as interrupt mode. the iir is not affected since ier[2] = 0. ? lsr[5] indicates when the transmitter fifo needs data. ? lsr[6] indicates that both the transmitter fifo and shift register are empty. ? lsr[7] indicates whether there are any errors in the receiver fifo. 19.6 logical device 7 (07h): port 60/64 emulation this section describes the port 60/64 emulation integrated into the siu. 19.6.1 feature list ? configurable unit disable ? positive decode for i/o cycles to 60h and 64h ? read/write scratchpad registers only (sticky bits) ? interrupt on write and self-interrupt clearing 19.6.2 overview the port 60/64 emulation unit consists of two 8-bit i/o registers intended to preserve values written to port 60 and 64 thus emulating a legacy 8042 device formerly at this legacy i/o address space. these registers may be enabled by bios typically in a pre- os environment and may be disabled during run time. these registers may be used for 8042 keyboard controller emulation but in no way support any controller or functionality beyond a scratchpad register and interrupt generation on writes. when enabled, this device will positively decode 8-bit i/o accesses to address 60h and 64h. writes to these addresses may generate an interrupt as configured in the logical device 07 primary interrupt register (70h). the interrupt generated from this unit will drive active (drives a logical 0) for one sirq frame. it does not require any further action (i.e., no eoi required or status bit to clear).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 725 19?intel ? 6300ESB ich 19.6.2.1 port 60h emulation (scr60) this 8-bit read/write register has no effect. it is intended as a scratchpad register for use by the programmer. 19.6.2.2 port 64h emulation (scr64) this 8-bit read/write register has no effect. it is intended as a scratchpad register for use by the programmer. 19.7 serial irq the siu supports the serial interrupt to transmit interrupt information to the host system. the serial interrupt scheme adheres to the serial irq specification. 19.7.1 timing diagrams for siu_serirq cycle table 652. scratch pad register p60 (scr60) scratch pad register p60 scr60 read/write address: reset state: access: 60h 00h 8-bit bit number bit mnemonic function 7:0 sp60[7:0] no effect on siu functionality table 653. scratch pad register p64 (scr64) scratch pad register p64 scr64 read/write address: reset state: access: 64h 00h 8-bit bit number bit mnemonic function 7:0 sp64[7:0] no effect on siu functionality figure 34. start frame timing with source sampled a low pulse on irq1 notes: 1. h=host control; r=recovery; t=turn-around; sl=slave control; s=sample 2. start frame pulse may be 4-8 clocks wide depending on the location of the device in the pci bridge hierarchy in a synchronous bridge design. r t s r t s s iusirq s iuclk host controller irq irq1 drive source r t none irq0 frame irq1 frame s r t irq2 frame none start start frame h sl or h 1
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 726 order number: 300641-004us 19.7.1.1 siu_serirq cycle control there are two modes of operation for the siu_serirq start frame. 1. quiet (active) mode : any device may initiate a start frame by driving the siu_serirq low for one clock, while the siu_serirq is idle. after driving low for one clock the siu_serirq is immediately tri-stated without at any time driving high. a start frame may not be initiated while the siu_serirq is active. the siu_serirq is idle between stop and start frames. the siu_serirq is active between start and stop frames. this mode of operation allows the siu_serirq to be idle when there are no irq/data transitions which should be most of the time. once a start frame has been initiated the host controller will take over driving the siu_serirq low in the next clock and will continue driving the siu_serirq low for a programmable period of three to seven clocks. this makes a total low pulse width of four to eight clocks. finally, the host controller will drive the siu_serirq back high for one clock, then tri- state. any siu_serirq device (i.e., the siu) which detects any transition on an irq/data line for which it is responsible must initiate a start frame in order to update the host controller unless the siu_serirq is already in an siu_serirq cycle and the irq/data transition may be delivered in that siu_serirq cycle. 2. continuous (idle) mode : only the host controller may initiate a start frame to update irq/data line information. all other siu_serirq agents become passive and may not initiate a start frame. siu_serirq will be driven low for four to eight clocks by host controller. this mode has two functions. it may be used to stop or idle the siu_serirq or the host controller may operate siu_serirq in a continuous mode by initiating a start frame at the end of every stop frame. an siu_serirq mode transition may only occur during the stop frame. note: upon reset, siu_serirq bus is defaulted to continuous mode, therefore only the host controller may initiate the first start frame. slaves must continuously sample the stop frames pulse width to determine the next siu_serirq cycle?s mode. each siu port must use a dedicated interrupt. siu interrupts cannot be shared with each other or with other devices. figure 35. stop frame timing with host using 17 siu_serirq sampling period notes: 1. h=host control; r=recovery; t=turn-around; s=sample; i=idle 2. stop pulse is 2 clocks wide for quiet mode, 3 clocks wide for continuous mode. 3. there may be none, one or more idle states during the stop frame. 4. the next siu_serirq cycle?s start frame pulse may or may not start immediately after the turn-around clock of the stop frame. s rt s s er_irq p ci_clk host controller irq15 driver rt none irq14 irq15 s rt iochck# none stop rt stop frame h i start next cycle 1 2 3 frame frame frame
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 727 19?intel ? 6300ESB ich 19.7.1.2 siu_serirq data frame once a start frame has been initiated, the siu will watch for the rising edge of the start pulse and start counting irq/data frames from there. each irq/data frame is three clocks: sample phase, recovery phase, and turn-around phase. during the sample phase the siu drives the siu_serirq low, if and only if, its last detected irq/ data value was low. if its detected irq/data value is high, siu_serirq is left tri- stated. during the recovery phase the siu drives the siu_serirq high, if and only if, it had driven the siu_serirq low during the previous sample phase. during the turn- around phase the siu tri-states the siu_serirq. the siu will drive the siu_serirq line low at the appropriate sample point if its associated irq/data line is low, regardless of which device initiated the start frame. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times three, minus one. (e.g., the irq5 sample clock is the sixth irq/data frame, (6 x 3) - 1 = 17th clock after the rising edge of the start pulse). siu_serirq period 13 is used to transfer irq12. 19.7.1.3 stop cycle control once all irq/data frames have completed the host controller will terminate siu_serirq activity by initiating a stop frame. only the host controller may initiate the stop frame. a stop frame is indicated when the siu_serirq is low for two or three clocks. if the stop frame?s low time is two clocks, the next siu_serirq cycle?s sampled mode is the quiet mode; and any siu_serirq device may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. if the stop frame?s low time is three clocks, the next siu_serirq cycle?s sampled mode is the continuous mode; and only the host controller may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. table 654. siu_serirq sampling periods siu_serirq period signal sampled # of clocks past start 1not used 2 2irq1 5 3irq2 8 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 728 order number: 300641-004us 19.7.1.4 latency latency for irq/data updates over the siu_serirq bus in bridge-less systems with the minimum host supported irq/data frames of seventeen, will range up to 96 clocks (2.88 s with a 33mhz pci bus). if one or more pci to pci bridge is added to a system, the latency for irq/data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. 19.7.1.5 eoi/isr read latency any serialized irq scheme has a potential implementation issue related to irq latency. irq latency could cause an eoi or isr read to precede an irq transition that it should have followed. this could cause a system fault. the host interrupt controller is responsible for ensuring that these latency issues are mitigated. the recommended solution is to delay eois and isr reads to the interrupt controller by the same amount as the siu_serirq cycle latency in order to ensure that these events do not occur out of order. 19.7.1.6 reset and initialization the siu_serirq bus uses siu_lreset# as its reset signal. the siu_serirq pin is tri- stated by all agents while siu_lreset# is active. with reset, siu_serirq slaves are put into the (continuous) idle mode. the host controller is responsible for starting the initial siu_serirq cycle to collect system?s irq/data default values. the system then follows with the continuous/quiet mode protocol (stop frame pulse width) for subsequent siu_serirq cycles. it is host controller?s responsibility to provide the default values to the interrupt controller and other system logic before the first siu_serirq cycle is performed. for siu_serirq system suspend, insertion, or removal application, the host controller should be programmed into continuous (idle) mode first. this is to ensure that the siu_serirq bus is in idle state before the system configuration changes. 19.8 configuration the configuration of the siu is very flexible and is based on the configuration architecture implemented in typical plug-and-play components. the siu is designed for motherboard applications in which the resources required by their components are known. with its flexible resource allocation architecture, the siu allows the bios to assign resources at post. 19.8.1 configuration port address selection the siu configuration port addresses for index and data are fixed at 4eh/4fh. see also section 8.1.31, ?offset e6h - e7h: lpc_en?lpc i/f enables (lpc i/f? d31:f0)? on page 337 . 19.8.2 primary configuration address decoder after a pci reset (siu_lreset# pin asserted) or power on reset the siu is in the run mode with the two uarts disabled. they may be configured through two standard configuration i/o ports (index and data) by placing the siu into configuration mode.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 729 19?intel ? 6300ESB ich the bios uses these configuration ports to initialize the logical devices at post. the index and data ports are only valid when the siu is in configuration mode. the index and data ports are effective only when the chip is in the configuration state. when the siu is not in the configuration state, reads return ffh and write data is ignored. 19.8.2.1 entering the configuration state the device enters the configuration state by the following contiguous sequence: write 80h to configuration port. write 86h to configuration port. 19.8.2.2 exiting the configuration state the device exits the configuration state by the following contiguous sequence: write 68h to configuration port. write 08h to configuration port. 19.8.2.3 configuration sequence to program the configuration registers, the following sequence must be followed: 1. enter configuration mode. 2. configure the configuration registers. 3. exit configuration mode. 19.8.2.4 configuration mode the system sets the logical device information and activates desired logical devices through the index and data ports. in configuration mode, the index port is located at the config port address and the data port is at index port address + 1. the desired configuration registers are accessed in two steps: 1. write the index of the logical device number configuration register (i.e., 07) to the index port and then write the number of the desired logical device to the data port. 2. write the address of the desired configuration register within the logical device to the index port and then write or read the configuration register through the data port. note: if accessing the global configuration registers, step (a) is not required. 3. the chip returns to the run state. note: only two states are defined: run and configuration. in the run state, the chip will always be ready to enter the configuration state.
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 730 order number: 300641-004us 19.8.3 siu configuration registers summary table 655. configuration registers summary global configuration registers index type default configuration register 07h r/w 00h logical device number 20h r 00h device id 21h r 00h device rev 28h r/w 01h siu i/f (wait states) 29h r/w 02h sirq configuration 2eh r/w 00 test mode configuration register logical device 4 registers (serial port 0) 30h r/w 00h enable 60h r/w 00h base i/o address msb 61h r/w 00h base i/o address lsb 70h r/w 00h primary interrupt select 74h r 04h reserved 75h r 04h reserved f0h r 00h vendor specific configuration logical device 5 registers (serial port 1) 30h r/w 00h enable 60h r/w 00h base i/o address msb 61h r/w 00h base i/o address lsb 70h r/w 00h primary interrupt select 74h r 04h reserved 75h r 04h reserved f0h r 00h vendor specific configuration logical device 7 registers (port emulation) 30h r/w 00h enable 60h r 00h base i/o address msb 61h r 60h base i/o address lsb 70h r/w 00h primary interrupt select
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 731 19?intel ? 6300ESB ich 19.8.3.1 global control/configuration registers [00h ? 2fh] the chip-level (global) registers lie in the address range [00h-2fh]. the design must use all 8 bits of the address port for register selection. all unimplemented registers and bits ignore writes and return ?0? when read. the index port is used to select a configuration register in the chip. the data port is then used to access the selected register. these registers are accessible only in the configuration mode. 19.8.3.2 logical device configuration registers [30h ? ffh] used to access the registers that are assigned to each logical unit. this chip supports two logical units and has two sets of logical device registers. the two logical devices are uart0 and uart1. a separate set (bank) of control and configuration registers exists for each logical device and is selected with the logical device # register. the index port is used to select a specific logical device register. these registers are then accessed through the data port. the logical device registers are accessible only when the device is in the configuration state. the logical register addresses are shown in table 657 through table 659 . table 656. global control registers register address (type) description logical device # default = 00h 07h (r/w) logical device select: a write to this register selects the current logical device. this allows access to the control and configuration registers for each logical device. device id default = 00h 20h (r) device id: a read only register which provides the device id. device rev default = 01h 21h (r) device rev: a read only register which provides device revision information. siu interface default = 01h 28h (r/w bits 7:2, 0 r- bit 1) bit 1 ? lpc bus wait states 1 = long wait states (sync 6) 0 = not supported bit 7:2, 0 ? rsvd = 0 siu configuration default = 02h 29h (r/w bits 3:2, 0 r- bit 1) bit 0 ? sirq enable 1 = enabled; participates in interrupt generation 0 = disabled; serial interrupts disabled bit 1 ? irq mode (read only, writes ignored) 1 = continuous mode 0 = quiet mode bit 3:2 ? uart_clk pre-divide uart_clk input 00 divide by 1 01 divide by 8 10 divide by 26 11 reserved bit 7:4 ? rsvd = 0
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 732 order number: 300641-004us table 657. logical device 4 (serial port 0) logical device register address description enable default = 00h 30h (r/w) bits[7:1] reserved, set to ?0?. bit[0] 1 = enable the logical device currently selected through the logical device # register. 0 = logical device currently selected is inactive i/o base address default = 00h 60-61h (r/w) registers 60h (msb) and 61h (lsb) set the base address for the device. note: decode is on 8 byte boundaries intel ? 6300ESB ich comm decode ranges 3f8 - 3ff (com 1) 2f8 - 2ff (com 2) 220 - 227 228 - 22f 238 - 23f 2e8 - 2ef (com 4) 338 - 33f 3e8 - 3ef (com 3) primary interrupt select default = 00h 70h (r/w) bits[3:0] select which interrupt level is used for the primary interrupt. 00= no interrupt selected 01= irq1 02= irq2 03= irq3 04= irq4 05= irq5 06= irq6 07= irq7 08= irq8 09= irq9 0a= irq10 0b= irq11 0c= irq12 0d= irq13 0e= irq14 0f= irq15 bits[7:4] reserved note: an interrupt is activated by setting this register to a non-zero value and setting any combination of bits 0-3 in the corresponding uart ier and the out2 bit in the mcr note: each siu port must use a dedicated interrupt. siu interrupts cannot be shared with each other or with other devices.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 733 19?intel ? 6300ESB ich rsvd default = 04h 74h (r/w - bit 3:0) (r - bit 7:4) bit 7:0 - rsvd rsvd default = 04h 75h (r/w - bit 3:0) (r - bit 7:4) bit 7:0 - rsvd rsvd default = 00h f0h (r/w - bit 0) (r - bit 7:1) bit 7:0 - rsvd table 657. logical device 4 (serial port 0) logical device register address description
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 734 order number: 300641-004us table 658. logical device 5 (serial port 1) logical device register address description enable default = 00h 30h (r/w) bits[7:1] reserved, set to ?0?. bit[0] 1 = enable the logical device currently selected through the logical device # register. 0 = logical device currently selected is inactive i/o base address default = 00h 60-61h (r/w) registers 60h (msb) and 61h (lsb) set the base address for the device. note: decode is on 8 byte boundaries. intel ? 6300ESB ich comm decode ranges 3f8 - 3ff (com 1) 2f8 - 2ff (com 2) 220 ? 227 228 - 22f 238 - 23f 2e8 - 2ef (com 4) 338 - 33f 3e8 - 3ef (com 3) primary interrupt select default = 00h 70h (r/w) bits[3:0] select which interrupt level is used for the primary interrupt. 00 = no interrupt selected 01 = irq1 02 = irq2 03 = irq3 04 = irq4 05 = irq5 06 = irq6 07 = irq7 08 = irq8 09 = irq9 0a = irq10 0b = irq11 0c = irq12 0d = irq13 0e = irq14 0f = irq15 bits[7:4] reserved note: an interrupt is activated by setting this register to a non-zero value and setting any combination of bits 0-3 in the corresponding uart ier and the out2 bit in the mcr note: each siu port must use a dedicated interrupt. siu interrupts cannot be shared with each other or with other devices.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 735 19?intel ? 6300ESB ich rsvd default = 04h 74h (r/w - bit 3:0) (r - bit 7:4 bit 7:0 - rsvd rsvd default = 04h 75h (r/w - bit 3:0) (r - bit 7:4 bit 7:0 - rsvd rsvd default = 00h f0h (r/w - bit 0) (r - bit 7:1) bit 7:0 - rsvd table 659. logical device 7 (port emulation) logical device register address description table 658. logical device 5 (serial port 1) logical device register address description
intel ? 6300ESB ich?19 intel ? 6300ESB i/o controller hub ds november 2007 736 order number: 300641-004us enable default = 00h 30h (r/w) bits[7:1] reserved, set to ?0?. bit[0 ] 1 = enable the logical device currently selected through the logical device # register. 0 = logical device currently selected is inactive. i/o base address default = 60h 60-61h (r) registers 60h (msb) and 61h (lsb) set the base address for the device. decode is on 8 byte boundaries so both 60h and 64h are captured by the single value of 60h in this space. note: this device must ignore accesses to unsupported bytes (specifically 61-63h and 65-67h) primary interrupt select default = 00h 70h (r/w) bits[3:0] select which interrupt level is used for the primary interrupt for port 60h, software note: do not set the interrupt to the same value as the port 64h interrupt. bits[7:4] select which interrupt level is used for the primary interrupt for port 64h, software note: do not set the interrupt to the same value as the port 60h interrupt. 00 = no interrupt selected 01 = irq1 02 = irq2 03 = irq3 04 = irq4 05 = irq5 06 = irq6 07 = irq7 08 = irq8 09 = irq9 0a = irq10 0b = irq11 0c = irq12 0d = irq13 0e = irq14 0f = irq15 note: an interrupt is activated by enabling this device (offset 30h),setting this register to a non-zero value, and writing to the appropriate i/o address (60h or 64h). table 659. logical device 7 (port emulation)
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 737 20?intel ? 6300ESB ich serial ata controller registers (d31:f2) 20 20.1 pci configuration registers (sata?d31:f2) note: registers that are not shown should be treated as reserved. all of the sata registers are in the core well. they can never be locked. table 660. pci configuration map (sata?d31:f2) (sheet 1 of 2) offset mnemonic register name/function default type 00-01h vid vendor id 8086h ro 02-03h did device id 25a3h or 25b0h ro 04-05h cmd command register 00h r/w 06-07h sts device status 02b0h r/w 08h rid revision id see note 2 ro 09h pi programming interface 8ah r/w 0ah scc sub class code 01h or 04h ro 0bh bcc base class code 01h ro 0dh mlt master latency timer 00h ro 0eh htype header type 00h ro 10-13h pcmd_bar primary command block base address 00000001h r/w 14-17h pcnl_bar primary control block base address 00000001h r/w 18-1bh scmd_bar secondary command block base address 00000001h r/w 1c-1fh scnl_bar secondary control block base address 00000001h r/w 20-23h bar base address register 00000001h r/w 2c-2dh svid subsystem vendor id 00h r/write-once 2e-2fh sid subsystem id 00h r/write-once 34h cap capabilities pointer 80h ro 3c intr_ln interrupt line 00h r/w 3d intr_pn interrupt pin 01h r/w 40-41h ide_timp primary ide timing 0000h r/w 42-43h ide_tims secondary ide timing 0000h r/w 44h sidetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control register 00h r/w notes: 1. the intel ? 6300ESB ich sata controller is not arbitrated as a pci device, therefore it does not need a master latency timer. 2. refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register.
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 738 order number: 300641-004us 20.1.1 offset 00 - 01h: vid?vendor id register (sata? d31:f2) 4a-4bh sdma_tim synchronous dma timing register 0000h r/w 54-57h ide_config ide i/o configuration register 00h r/w 70-71h pid pci power management capability id 0001h ro 72-73h pc pci power management capabilities 0002h ro 74-75h pmcs pci power management control and status 0000h r/w 80-81h mid message signaled interrupt capability id 7005h ro 82-83h mc message signaled interrupt message control 0000h r/w 84-87h ma message signaled interrupt message address 0000h r/w 88-89h md message signaled interrupt message data 0000h r/w 90h map address map 00h r/w 92-93h pcs port status and control 0000h r/w a0h sri sata registers index 00h r/w a4h srd sata registers data xxh r/w e0h? e3h bfcs bist fis control/status 00000000h r/w, r/wc e4h? e7h bftd1 bist fis transmit data, dw1 00000000h r/w e8h? ebh bftd2 bist fis transmit data, dw2 00000000h r/w table 661. offset 00 - 01h: vid?vendor id register (sata?d31:f2) bits name description access 15:0 vendor id value this is a 16-bit value assigned to intel. intel vid = 8086h ro table 660. pci configuration map (sata?d31:f2) (sheet 2 of 2) offset mnemonic register name/function default type notes: 1. the intel ? 6300ESB ich sata controller is not arbitrated as a pci device, therefore it does not need a master latency timer. 2. refer to the intel ? 6300ESB i/o controller hub specification update for the most up-to-date value of the revision id register. device: 31 function: 2 offset: 00-01h attribute: read-only default value: 8086h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 739 20?intel ? 6300ESB ich 20.1.2 offset 02 - 03h: did?device id register (sata? d31:f2) 20.1.3 offset 04h - 05h: cmd?command register (sata?d31:f2) table 662. offset 02 - 03h: did?device id register (sata?d31:f2) bits name description access 15:0 device id value indicates what device number was assigned by the pci sig. when device 31 function 2, offset ac h, bit 22=0; did = 25a3h (hard drive) when device 31 function 2, offset ac h, bit 22=1; did = 25b0h (raid) table 663. offset 04h - 05h: cmd?command register (sata?d31:f2) (sheet 1 of 2) bits name description access 15:1 1 reserved reserved. 10 interrupt disable 0 = enables the sata host controller to assert inta# (native mode), irq14/15 (legacy mode), and msi (when msi is enabled). 1 = the interrupt will be deasserted and it may not generate msis. r/w 9 fast back-to-back enable (fbe) reserved as ?0?. ro 8 serr# enable reserved as ?0?. ro 7 wait cycle control reserved as ?0?. ro 6 parity error response 0 = disabled. sata controller will not generate perr# when a data parity error is detected. 1 = enabled. sata controller will generate perr# when a data parity error is detected. r/w 5 vga palette snoop reserved as ?0?. ro 4 postable memory write enable (pmwe) reserved as ?0?. ro device: 31 function: 2 offset: 02-03h attribute: read-only default value: 25a3h or 25b0h size: 16-bit lockable: no power well: core device: 31 function: 2 offset: 04h-05h attribute: read-only, read/write default value: 00h size: 16-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 740 order number: 300641-004us 3 special cycle enable (sce) reserved as ?0?. ro 2 bus master enable (bme) controls the intel ? 6300ESB ich?s ability to act as a pci master for ide bus master transfers. this bit does not impact the generation of completions for split transaction commands. r/w 1 memory space enable (mse) the sata controller does not contain memory space. ro 0 iose - i/o space enable (iose) this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus master io registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set. r/w table 663. offset 04h - 05h: cmd?command register (sata?d31:f2) (sheet 2 of 2) bits name description access device: 31 function: 2 offset: 04h-05h attribute: read-only, read/write default value: 00h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 741 20?intel ? 6300ESB ich 20.1.4 offset 06 - 07h: sts?device status register (sata?d31:f2) table 664. offset 06 - 07h: sts?device status register (sata?d31:f2) bits name description access 15 detected parity error (dpe) 0 = no parity error detected by sata controller. 1 = sata controller detects a parity error on its interface. r/wc 14 signaled system error (sse) this bit is set by the intel ? 6300ESB ich whenever it signals serr# (internally). the serr_en bit (bit 8 in the command register) must be ?1? for this bit to be set. the following conditions can cause the generation of serr#: a parity error is seen on address, command, or data (if the data was targeting the ehc) on the internal interface to the usbe host controller due to a parity error on hub interface and bit 6 of the command register is set to 1. an ehc-initiated memory read results in a completion packet with a status other than successful on hub interface. the serr on aborts enable bit (bit 3, offset 84h) must also be set in this case. software clears this bit by writing a ?1? to this bit location. r/wc 13 received master-abort status (rma) 0 = 0 cleared by writing a ?1? to it. 1 = bus master ide interface function, as a master, generated a master-abort. r/wc 12 received target-abort status (rta) set when the sata controller receives a target abort to a cycle it generated. 11 signaled target-abort status (sta) reserved as ?0?. ro 10:9 devsel# timing status (devt) 01 = hardwired; controls the device select time for the sata controller?s pci interface. ro 8 master data parity error detected (dpd) set when the sata controller, as a master, either detects a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. for the intel ? 6300ESB ich, this bit may only be set on read completions when there is a parity error. 7 fast back-to-back capable reserved as ?1?. ro 6 user definable features (udf) reserved as ?0?. ro 5 66mhz capable reserved as ?1?. ro 4 capabilities list (cl) indicates the presence of a capabilities list. this bit is hardwired to a ?1? indicating the presence of a valid capabilities pointer at offset 34h. ro 3:0 reserved reserved device: 31 function: 2 offset: 06-07h attribute: read/write clear, read-only default value: 02b0h size: 16-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 742 order number: 300641-004us 20.1.5 offset 09h: pi?programming interface (sata? d31:f2) 20.1.6 offset 0ah: scc?sub class code (sata?d31:f2) table 665. offset 09h: pi?programming interface (sata?d31:f2) bits name description access 7 this read-only bit is a ?1? to indicate that the sata controller supports bus master operation ro 6:4 reserved reserved. will always return 0. 3sop_mode_cap this read-only bit is a ?1? to indicate that the secondary controller supports both legacy and native modes. ro 2sop_mode_sel this read-write bits determines the mode that the secondary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode r/w 1 pop_mode_cap this read-only bit is a ?1? to indicate that the primary controller supports both legacy and native modes. ro 0 pop_mode_sel this read-write bits determines the mode that the primary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode r/w table 666. offset 0ah: scc?sub class code (sata?d31:f2) bits name description access 7:0 sub class code 01h when dev 31, func 0, offset ach, bit 23 is ?0?; indicates ide controller 04h when dev 31, func 0, offset ach, bit 23 is ?1?; indicates raid controller ro device: 31 function: 2 offset: 09h attribute: read/write default value: 8ah size: 8-bit device: 31 function: 2 offset: 0ah attribute: read-only default value: 01h or 04h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 743 20?intel ? 6300ESB ich 20.1.7 offset 0bh: bcc?base class code (sata?d31:f2) 20.1.8 offset 0dh: mlt?master latency timer (sata? d31:f2) table 667. offset 0bh: bcc?base class code (sata?d31:f2) bits name description access 7:0 base class code 01 = mass storage device ro table 668. offset 0dh: mlt?master latency timer (sata?d31:f2) bits name description access 7:0 bus master latency hardwired to 00h. the ide controller is implemented internally, and is not arbitrated as a pci device, so it does not need a master latency timer. ro device: 31 function: 2 offset: 0bh attribute: read-only default value: 01h size: 8-bit device: 31 function: 2 offset: 0dh attribute: read-only default value: 00h size: 8-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 744 order number: 300641-004us 20.1.9 offset 10h - 13h: pcmd_bar?primary command block base address register (sata?d31:f2) note: this 8-byte i/o space is used in native mode for the primary controller?s command block. 20.1.10 offset 14h - 17h: pcnl_bar?primary control block base address register (sata?d31:f2) note: this 4-byte i/o space is used in native mode for the primary controller?s control block. table 669. offset 10h - 13h: pcmd_bar?primary command block base address register (sata?d31:f2) bits name description access 31:1 6 reserved reserved. 15:3 base address base address of the i/o space (8 consecutive i/o locations). r/w 2:1 reserved reserved. 0 resource type indicator (rte) this bit is set to ?1?, indicating a request for io space. ro table 670. offset 14h - 17h: pcnl_bar?primary control block base address register (sata?d31:f2) bits name description access 31:1 6 reserved reserved. 15:2 base address base address of the i/o space (4 consecutive i/o locations). r/w 1 reserved reserved. 0 resource type indicator (rte) this bit is set to ?1?, indicating a request for io space. ro device: 31 function: 2 offset: 10h-13h attribute: read/write default value: 00000001h size: 32-bit device: 31 function: 2 offset: 14h-17h attribute: read/write default value: 00000001h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 745 20?intel ? 6300ESB ich 20.1.11 offset 18h - 1bh: scmd_bar?secondary command block base address register (ide d31:f1) note: this 4-byte i/o space is used in native mode for the secondary controller?s control block. 20.1.12 offset 14h - 17h: scnl_bar?secondary control block base address register (ide d31:f1) note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. table 671. offset 18h - 1bh: scmd_bar?secondary command block base address register (ide d31:f1) bits name description access 31:1 6 reserved reserved. 15:3 base address base address of the i/o space (8 consecutive i/o locations). r/w 2:1 reserved reserved. 0 resource type indicator (rte) this bit is set to ?1?, indicating a request for io space. ro table 672. offset 14h - 17h: scnl_bar?secondary control block base address register (ide d31:f1) bits name description access 31:1 6 reserved reserved. 15:2 base address base address of the i/o space (4 consecutive i/o locations). r/w 1 reserved reserved. 0 resource type indicator (rte) this bit is set to ?1?, indicating a request for io space. ro device: 31 function: 2 offset: 18h-1bh attribute: read/write default value: 00000001h size: 32-bit device: 31 function: 2 offset: 14h-17h attribute: read/write default value: 00000001h size: 32-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 746 order number: 300641-004us 20.1.13 offset 20h - 23h: bar?legacy bus master base address register (sata?d31:f2) note: the bus master ide interface function uses base address register 5 to request a 16- byte io space to provide a software interface to the bus master functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. 20.1.14 offset 2ch - 2dh: svid?subsystem vendor id (sata?d31:f2) table 673. offset 20h - 23h: bar?legacy bus master base address register (sata?d31:f2) bits name description access 31:1 6 reserved reserved. 15:4 base address base address of the i/o space (16 consecutive i/o locations). r/w 3:1 reserved reserved. 0 resource type indicator (rte) hardwired to ?1?, indicating a request for io space. ro table 674. offset 2ch - 2dh: svid?subsystem vendor id (sata?d31:f2) bits name description access 15:0 subsystem vendor id (svid) the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value may be read, but subsequent writes to this register have no effect. the value written to this register will also be readable through the corresponding svid registers for the usb#1, usb#2 and smbus functions. r/wo device: 31 function: 2 offset: 20h-23h attribute: read/write default value: 00000001h size: 32-bit device: 31 function: 2 offset: 2ch-2dh attribute: read/write once default value: 00h size: 16-bit lockable: no power well: core
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 747 20?intel ? 6300ESB ich 20.1.15 offset 2eh - 2fh: sid?subsystem id (sata? d31:f2) 20.1.16 offset 34h: cap?capabilities pointer register (sata?d31:f2) 20.1.17 offset 3ch: intr_ln?interrupt line register (sata?d31:f2) table 675. offset 2eh - 2fh: sid?subsystem id (sata?d31:f2) bits name description access 15:0 subsystem id (sid) the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value may be read, but subsequent writes to this register have no effect. the value written to this register will also be readable through the corresponding sid registers for the usb#1, usb#2 and smbus functions. r/wo table 676. offset 34h: cap?capabilities pointer register (sata?d31:f2) bits name description access 7:0 capability pointer (cp) this bit indicates that the first capability pointer offset is 80h, the msi capability. this value will be 70h if the map register (offset 90h) indicates that the sata and ide functions are combined (values of 100, 101, 110, or 111). ro table 677. offset 3ch: intr_ln?interrupt line register (sata?d31:f2) bits name description access 7:0 interrupt line it is to communicate to software the interrupt line that the interrupt pin is connected to. r/w device: 31 function: 2 offset: 2eh-2fh attribute: read/write-once default value: 00h size: 16-bit lockable: no power well: core device: 31 function: 2 offset: 34h attribute: read-only default value: 80h size: 8-bit device: 31 function: 2 offset: 3ch attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 748 order number: 300641-004us 20.1.18 offset 3dh: intr_pn?interrupt pin register (sata?d31:f2) 20.1.19 offset 40 - 41h: ide_timp?primary ide timing register (sata?d31:f2) note: this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. table 678. offset 3dh: intr_pn?interrupt pin register (sata?d31:f2) bits name description access 7:3 reserved reserved. 2:0 interrupt pin the value of 01h indicates to ?software? that the intel ? 6300ESB ich will drive inta#. note that this is only used in native mode. also note that the routing to the internal interrupt controller does not necessarily relate to the value in this register. ro table 679. offset 40 - 41h: ide_timp?primary ide timing register (sata? d31:f2) (sheet 1 of 2) bits name description access 15 ide decode enable (ide) individually enable/disable the primary or secondary decode. 0 = disable. 1 = enables the intel ? 6300ESB ich to decode the associated command blocks (1f0-1f7h for primary, 170- 177h for secondary) and control block (3f6h for primary and 376h for secondary). this bit effects the ide decode ranges for both legacy and native-mode decoding. r/w 14 drive 1 timing register enable (sitre) 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and use the slave ide timing register for drive 1 r/w 13:1 2 iordy sample point (isp) the setting of these bits determine the number of pci clocks between ide ior#/iow# assertion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved device: 31 function: 2 offset: 3dh attribute: read-only default value: 01h size: 8-bit device: 31 function: 2 offset: primary: 40-41h secondary: 42-43h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 749 20?intel ? 6300ESB ich 11:1 0 reserved reserved. 9:8 recovery time (rct) the setting of these bits determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock r/w 7 drive 1 dma timing enable (dte1) 0 = disable. 1 = enable the fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. r/w 6 drive 1 prefetch/posting enable (ppe1) 0 = disable. 1 = enable prefetch and posting to the ide data port for this drive. r/w 5 drive 1 iordy sample point enable (ie1) 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive. r/w 4 drive 1 fast timing bank (time1) 0 = accesses to the data port will use compatible timings for this drive. 1 = when this bit =?1? and bit 14 = ?0?, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. when this bit = ?1? and bit 14 = ?1?, accesses to the data port will use the iordy sample point and recover time specified in the slave ide timing register. r/w 3 drive 0 dma timing enable (dte0) 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. r/w 2 drive 0 prefetch/posting enable (ppe0) 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. r/w 1 drive 0 iordy sample point enable (ie0) 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. r/w 0 drive 0 fast timing bank (time0) 0 = accesses to the data port will use compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. r/w table 679. offset 40 - 41h: ide_timp?primary ide timing register (sata? d31:f2) (sheet 2 of 2) bits name description access device: 31 function: 2 offset: primary: 40-41h secondary: 42-43h attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 750 order number: 300641-004us 20.1.20 ide_tims?secondary ide timing register (sata?d31:f2) note: see the above register description for ?primary ide timing register.? 20.1.21 offset 44h: sidetim?slave ide timing register (sata?d31:f2) table 680. offset 44h: sidetim?slave ide timing register (sata?d31:f2) bits name description access 7:6 secondary drive 1 iordy sample point (sisp1) determines the number of pci clocks between ide ior#/ iow# assertion and the first iordy sample point, when the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved r/w 5:4 secondary drive 1 recovery time (srct1) determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, when the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks r/w 3:2 primary drive 1 iordy sample point (pisp1) determines the number of pci clocks between ior#/iow# assertion and the first iordy sample point, when the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved r/w 1:0 primary drive 1 recovery time (prct1) determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, when the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks r/w device: 31 function: 2 offset: 44h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 751 20?intel ? 6300ESB ich 20.1.22 offset 48h: sdma_cnt?synchronous dma control register (sata?d31:f2) table 681. offset 48h: sdma_cnt?synchronous dma control register (sata? d31:f2) bits name description access 7:4 reserved reserved. 3 secondary drive 1 synchronous dma mode enable (ssde1) 0 = disable (default) 1 = enable synchronous dma mode for secondary channel drive 1. r/w 2 secondary drive 0 synchronous dma mode enable (ssde0) 0 = disable (default) 1 = enable synchronous dma mode for secondary drive 0. r/w 1 primary drive 1 synchronous dma mode enable (psde1) 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 1. r/w 0 primary drive 0 synchronous dma mode enable (psde0) 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 0. r/w device: 31 function: 2 offset: 48h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 752 order number: 300641-004us 20.1.23 offset 4a - 4bh: sdma_tim?synchronous dma timing register (sata?d31:f2) table 682. offset 4a - 4bh: sdma_tim?synchronous dma timing register (sata?d31:f2) (sheet 1 of 2) bits name description access 15:1 4 reserved reserved. 13:1 2 secondary drive 1 cycle time (sct1) for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to- stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33mhz clk) 00 = ct 4 clocks, rp 6 clocks 01 = ct 3 clocks, rp 5 clocks 10 = ct 2 clocks, rp 4 clocks 11 = reserved scb1 = ?1? (66mhz clk) 00 = reserved 01 = ct 3 clocks, rp 8 clocks 10 = ct 2 clocks, rp 8 clocks 11 = reserved fast_scb1 = ?1? (133mhz clk) 00 = reserved 01 = ct 3 clks, rp 16 clks 10 = reserved 11 = reserved r/w 11:1 0 reserved reserved. 9:8 secondary drive 0 cycle time (sct0) for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to- stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33mhz clk) 00 = ct 4 clocks, rp 6 clocks 01 = ct 3 clocks, rp 5 clocks 10 = ct 2 clocks, rp 4 clocks 11 = reserved scb1 = ?1? (66mhz clk) 00 = reserved 01 = ct 3 clocks, rp 8 clocks 10 = ct 2 clocks, rp 8 clocks 11 = reserved fast_scb1 = ?1? (133mhz clk) 00 = reserved 01 = ct 3 clks, rp 16 clks 10 = reserved 11 = reserved r/w 7:6 reserved reserved. device: 31 function: 2 offset: 4a-4bh attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 753 20?intel ? 6300ESB ich 5:4 primary drive 1 cycle time (pct1) for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to- stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33mhz clk) 00 = ct 4 clocks, rp 6 clocks 01 = ct 3 clocks, rp 5 clocks 10 = ct 2 clocks, rp 4 clocks 11 = reserved pcb1 = ?1? (66mhz clk) 00 = reserved 01 = ct 3 clocks, rp 8 clocks 10 = ct 2 clocks, rp 8 clocks 11 = reserved fast_pcb1 = ?1? (133mhz clk) 01 = ct 3 clks, rp 16 clks 00 = reserved 10 = reserved 11 = reserved r/w 3:2 reserved reserved. 1:0 primary drive 0 cycle time (pct0) for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to- stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33mhz clk) 00 = ct 4 clocks, rp 6 clocks 01 = ct 3 clocks, rp 5 clocks 10 = ct 2 clocks, rp 4 clocks 11 = reserved pcb1 = ?1? (66mhz clk) 00 = reserved 01 = ct 3 clocks, rp 8 clocks 10 = ct 2 clocks, rp 8 clocks 11 = reserved fast_pcb1 = ?1? (133mhz clk) 00 = reserved 01 = ct 3 clks, rp 16 clks 10 = reserved 11 = reserved r/w table 682. offset 4a - 4bh: sdma_tim?synchronous dma timing register (sata?d31:f2) (sheet 2 of 2) bits name description access device: 31 function: 2 offset: 4a-4bh attribute: read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 754 order number: 300641-004us 20.1.24 offset 54h: ide_config?ide i/o configuration register (sata?d31:f2) table 683. offset 54h: ide_config?ide i/o configuration register (sata? d31:f2) (sheet 1 of 2) bits name description access 31:2 4 reserved reserved. 23:2 0 scratchpad (sp2) the intel ? 6300ESB ich does not perform any actions on these bits. 19:1 8 reserved reserved. r/w 17:1 6 reserved reserved. r/w 15 fast_scb1: fast secondary drive 1 base clock this bit is used in conjunction with the sct1 bits to enable/ disable ultra ata/100 timings for the secondary slave drive. 0 = disable ultra ata/100 timing for the secondary slave drive. 1 = enable ultra ata/100 timing for the secondary slave drive (overrides bit 3 in this register). r/w 14 fast_scb0: fast secondary drive 0 base clock this bit is used in conjunction with the sct0 bits to enable/ disable ultra ata/100 timings for the secondary master drive. 0 = disable ultra ata/100 timing for the secondary master drive. 1 = enable ultra ata/100 timing for the secondary master drive (overrides bit 2 in this register). r/w 13 fast_pcb1: fast primary drive 1 base clock this bit is used in conjunction with the pct1 bits to enable/ disable ultra ata/100 timings for the primary slave drive. 0 = disable ultra ata/100 timing for the primary slave drive. 1 = enable ultra ata/100 timing for the primary slave drive (overrides bit ?1? in this register). r/w 12 fast_pcb0: fast primary drive 0 base clock this bit is used in conjunction with the pct0 bits to enable/ disable ultra ata/100 timings for the primary master drive. 0 = disable ultra ata/100 timing for the primary master drive. 1 = enable ultra ata/100 timing for the primary master drive (overrides bit ?0? in this register). r/w 11:8 reserved reserved. 7:4 scratchpad (sp1) the intel ? 6300ESB ich does not perform any action on these bits. 3 scb1: secondary drive 1 base clock 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings r/w device: 31 function: 2 offset: 54h attribute: read-write default value: 00h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 755 20?intel ? 6300ESB ich 20.1.25 offset 70 - 71h: pid?pci power management capability id (sata?d31:f2) 20.1.26 offset 72 - 73h: pc?pci power management capabilities (sata?d31:f2) 2 scbo: secondary drive 0 base clock 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings r/w 1 pcb1: primary drive 1 base clock 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings r/w 0 pcb0: primary drive 0 base clock 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings r/w table 684. offset 70 - 71h: pid?pci power management capability id (sata? d31:f2) bits name description access 15:8 next capability (next) indicates that this is the last item in the list 7:0 cap id (cid) indicates that this pointer is a pci power management. table 685. offset 72 - 73h: pc?pci power management capabilities (sata? d31:f2) bits name description access 15:1 1 pme_support indicates pme# cannot be generated form the sata host controller. when in low power state, resume events are not allowed. 10 d2_support the d2 state is not supported 9 d1_support the d1 state is not supported table 683. offset 54h: ide_config?ide i/o configuration register (sata? d31:f2) (sheet 2 of 2) bits name description access device: 31 function: 2 offset: 54h attribute: read-write default value: 00h size: 32-bit device: 31 function: 2 offset: 70-71h attribute: read-only default value: 0001h size: 16-bit device: 31 function: 2 offset: 72-73h attribute: read-only default value: 0002 size: 16-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 756 order number: 300641-004us 20.1.27 offset 74 - 75h: pmcs?pci power management control and status (sata?d31:f2) 8:6 aux_current reports 375ma maximum suspend well current required when in the d3cold state. 5 device specific initial- ization (dsi) indicates that no device-specific initialization is required. 4 reserved reserved. 3 pme clock (pmec) indicates that pci clock is not required to generate pme#. 2:0 version (vs) indicates support for revision 1.1 of the pci power management specification. table 686. offset 74 - 75h: pmcs?pci power management control and status (sata?d31:f2) bits name description access 15 pme status (pmes) reserved as ?0?. 14:9 reserved reserved. 8 pme enable (pmee). reserved as ?0?. 7:2 reserved reserved. 1:0 power state (ps) power state (ps). these bits are used both to determine the current power state of the sata controller and to set a new power state. 00: d0 state 01: d1 state 10: d2 state 11: d3hot state when in the d3hot state, the controller?s configuration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. table 685. offset 72 - 73h: pc?pci power management capabilities (sata? d31:f2) bits name description access device: 31 function: 2 offset: 72-73h attribute: read-only default value: 0002 size: 16-bit device: 31 function: 2 offset: 74-75h attribute: read-only, read/write default value: 0000h size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 757 20?intel ? 6300ESB ich 20.1.28 offset 80 - 81h: mid?message signaled interrupt identifiers (sata?d31:f2) 20.1.29 offset 82 - 83h: mc?message signaled interrupt message control (sata?d31:f2) table 687. offset 80 - 81h: mid?message signaled interrupt identifiers (sata?d31:f2) bits name description access 15:8 next pointer (next) indicates that the next item in the list the pci power management pointer. 7:0 capability id (cid) capability id indicates msi. table 688. offset 82 - 83h: mc?message signaled interrupt message control (sata?d31:f2) bits name description access 15:8 reserved reserved. 7 64 bit address capable (c64) capable of generating 32-bit message only. ro 6:4 multiple message enable (mme) these bits are r/w for software compatibility, but only one message is ever sent by the intel ? 6300ESB ich. r/w 3:1 multiple message capable (mmc) only one message is required. ro 0 msi enable (msie) 0 = disabled. 1 = msi is enabled and traditional interrupt pins are not used to generate interrupts. r/w device: 31 function: 2 offset: 80-81h attribute: read-only default value: 7005h size: 16-bit device: 31 function: 2 offset: 82-83h attribute: read-only, read/write default value: 0000h size: 16-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 758 order number: 300641-004us 20.1.30 offset 84 - 87h: ma?message signaled interrupt message address (sata?d31:f2) table 689. offset 84 - 87h: ma?message signaled interrupt message address (sata?d31:f2) bits name description access 31:2 address (addr) lower 32 bits of the system specified message address, always dword aligned. 1:0 reserved reserved. device: 31 function: 2 offset: 84-87h attribute: read/write default value: 0000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 759 20?intel ? 6300ESB ich 20.1.31 offset 88 - 89h: md?message signaled interrupt message data (sata?d31:f2) 20.1.32 offset 90h: map?address map (sata?d31:f2) table 690. offset 88 - 89h: md?message signaled interrupt message data (sata?d31:f2) bits name description access 15:0 data (data) this field is programmed by system software when msi is enabled. its content is driven onto the lower word (pci ad[15:0]) during the data phase of the msi memory write transaction. table 691. offset 90h: map?address map (sata?d31:f2) bits name description access 7:3 reserved reserved. 2:0 map value the value of these bits indicate the address range the sata port responds to, and whether or not the sata and ide functions are combined. 000 = non-combined. p0 is primary master. p1 is secondary master. 001 = non-combined. p0 is secondary master. p1 is primary master. 100 = combined. p0 is primary master. p1 is primary slave. p-ata is secondary. 101 = combined. p0 is primary slave. p1 is primary master. p-ata is secondary. 110 = combined. p-ata is primary. p0 is secondary master. p1 is secondary slave. 111 = combined. p-ata is primary. p0 is secondary slave. p1 is secondary master. r/w device: 31 function: 2 offset: 88-89h attribute: read/write default value: 0000h size: 16-bit device: 31 function: 2 offset: 90h attribute: read-only, read/write default value: 00h size: 8-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 760 order number: 300641-004us 20.1.33 offset 92h: pcs?port status and control (sata? d31:f2) 20.1.34 offset a0h: sri?sata registers index (sata? d31:f2) table 692. offset 92h: pcs?port status and control (sata?d31:f2) bits name description access 15:6 reserved reserved. 5reserved reserved. bit is read only, reset to ?0? but may be ?1? at any given time 4reserved reserved. bit is read only, reset to ?0? but may be ?1? at any given time. 3:2 reserved reserved. 1port 1 enabled (p1e) 0 = the port is disabled. the port is in the ?off? state and cannot detect any devices. 1 = the port is enabled. the port may transition between the on, partial, and slumber states and may detect devices. 0port 0 enabled (p0e) 0 = the port is disabled. the port is in the ?off? state and cannot detect any devices. 1 = the port is enabled. the port may transition between the on, partial, and slumber states and may detect devices. table 693. offset a0h: sri?sata registers index (sata?d31:f2) bits name description access 7 reserved reserved. 6:0 index (idx) this field is a 7-bit index pointer into the sata registers space. data is written into the srd register (d31:f2:a4h) and read from the srd register. r/w device: 31 function: 2 offset: 92h attribute: read/write default value: 000h size: 16-bit device: 31 function: 2 offset: a0h attribute: read/write default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 761 20?intel ? 6300ESB ich 20.1.35 offset a4h - a7h: srd?sata registers data (sata?d31:f2) index name 00h?01h sata tx termination test register (stt) 02h?1dh reserved 1eh sata tx output test register (stot) 1fh?53h reserved 54h?57h serror register port 0 (ser0) 58h?63h reserved 64h?67h serror register port 1 (ser1) 68h?ffh reserved table 694. offset a4h - a7h: srd?sata registers data (sata?d31:f2) bits name description access 31:0 data (dta) this field is a 32-bit data value that is written to the register pointed to by sri (d31:f2:a0h) or read from the register pointed to by sri. r/w table 693. offset a0h: sri?sata registers index (sata?d31:f2) bits name description access device: 31 function: 2 offset: a0h attribute: read/write default value: 00h size: 8-bit device: 31 function: 2 offset: a4h?a7h attribute: read/write default value: xxh size: 8-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 762 order number: 300641-004us 20.1.36 sttt?sata tx termination test register a (sata?d31:f2) 20.1.37 stot ? sata tx output test register (sata? d31:f2) table 695. sttt?sata tx termination test register a (sata?d31:f2) bits name description access 15:2 reserved reserved. 1 port 1 tx termination tes t e n a b le setting this bit will enable testing of the port?s tx termination. this bit is only to be used for system board testing. r/w 0 port 0 tx termination tes t e n a b le setting this bit will enable testing of the port?s tx termination. this bit is only to be used for system board testing. r/w table 696. stot ? sata tx output test register (sata?d31:f2) bits name description access 15:2 reserved reserved. 1force align tx bit this bit will force the intel ? 6300ESB ich to repeatedly transmit the sata align primitive when set. this bit is only used for system board testing. r/w 0 reserved reserved. r/w device: 31 function: 2 index address: index 00h?01h attribute: read/write default value: xxxxh size: 16-bit device: 31 function: 2 index address: index 1eh attribute: read/write default value: xxxxh size: 16-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 763 20?intel ? 6300ESB ich 20.1.38 offset index 54h - 57h: ser0?sata serror register port 0 (sata?d31:f2) 20.1.39 offset index 64h - 67h: ser1?sata serror register port 1 (sata?d31:f2) 20.1.40 offset e0h - e3h: bfcs?bist fis control/status register (sata?d31:f2) table 697. offset index 54h - 57h: ser0?sata serror register port 0 (sata? d31:f2) bits name description access 31:0 ser0 this register is implemented in accordance with the serror register description in section 10.1.2 of the sata 1.0 specification . r/w table 698. offset index 64h - 67h: ser1?sata serror register port 1 (sata? d31:f2) bits name description access 31:0 ser1 this register is implemented in accordance with the serror register description in section 10.1.2 of the sata 1.0 specification . r/w table 699. offset e0h - e3h: bfcs?bist fis control/status register (sata? d31:f2) (sheet 1 of 3) bits name description access 31:1 2 reserved reserved. device: 31 function: 2 offset: index 54h?57h attribute: read/write default value: xxxxxxxxh size: 32-bit device: 31 function: 2 offset: index 64h?67h attribute: read/write default value: xxxxxxxxh size: 32-bit device: 31 function: 2 offset: e0h?e3h attribute: read/write, read/write clear default value: 00000000h size: 32-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 764 order number: 300641-004us 11 bist fis successful (bfs) 0 = software clears this bit by writing a ?1? to it. 1 = this bit is set any time a bist fis transmitted by the intel ? 6300ESB ich receives an r_ok completion status from the device. note: this bit must be cleared by software prior to initiating a bist fis. r/wc 10 bist fis failed (bff) 0 = software clears this bit by writing a ?1? to it. 1 = this bit is set any time a bist fis transmitted by the intel ? 6300ESB ich receives an r_err completion status from the device. note: this bit must be cleared by software prior to initiating a bist fis. r/wc 9 port 1 bist fis initiate (p1bfi) when a rising edge is detected on this bit field, the intel ? 6300ESB ich initiates a bist fis to the device on port 1, using the parameters specified in this register and the data specified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 1 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re-enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the intel ? 6300ESB ich to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p1bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. r/w 8 port 0 bist fis initiate (p0bfi) when a rising edge is detected on this bit field, the intel ? 6300ESB ich initiates a bist fis to the device on port 0, using the parameters specified in this register and the data specified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 0 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re-enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the intel ? 6300ESB ich to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p0bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. r/w table 699. offset e0h - e3h: bfcs?bist fis control/status register (sata? d31:f2) (sheet 2 of 3) bits name description access device: 31 function: 2 offset: e0h?e3h attribute: read/write, read/write clear default value: 00000000h size: 32-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 765 20?intel ? 6300ESB ich 20.1.41 offset e4h - e7h: bftd1?bist fis transmit data1 register (sata?d31:f2) 7:2 bist fis parameters these 6 bits form the contents of the upper 6 bits of the bist fis pattern definition in any bist fis transmitted by the intel ? 6300ESB ich. this field is not port specific ? its contents will be used for any bist fis initiated on port 0 on port 1. the specific bit definitions are: bit 7: t ? far end transmit mode bit 6: a ? align bypass mode bit 5: s ? bypass scrambling bit 4: l ? far end retimed loopback bit 3: f ? far end analog loopback bit 2: p ? primitive bit for use with transmit mode 1:0 reserved reserved. table 700. offset e4h - e7h: bftd1?bist fis transmit data1 register (sata? d31:f2) bits name description access 31:0 bist fis transmit data 1 the data programmed into this register will form the contents of the second dword of any bist fis initiated by the intel ? 6300ESB ich. this register is not port specific ? its contents will be used for bist fis initiated on port 0 or port 1. although the 2nd and 3rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 2nd dw regardless of whether or not the ?t? bit is indicated in the bfcs register. r/w table 699. offset e0h - e3h: bfcs?bist fis control/status register (sata? d31:f2) (sheet 3 of 3) bits name description access device: 31 function: 2 offset: e0h?e3h attribute: read/write, read/write clear default value: 00000000h size: 32-bit device: 31 function: 2 offset: e4h?e7h attribute: read/write default value: 00000000h size: 32-bit
20? intel ? 6300ESB ich intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 766 20.1.42 offset e8h - ebh: bftd2?bist fis transmit data2 register (sata?d31:f2) 20.2 bus master ide i/o registers (d31:f2) the bus master ide function uses 16 bytes of i/o space, allocated through the bmiba register, located in device 31:function 1 configuration space, offset 20h. all bus master ide i/o space registers may be accessed as byte, word, or dword quantities. reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). the description of the i/o registers is shown below in table 702 . table 701. offset e8h - ebh: bftd2?bist fis transmit data2 register (sata? d31:f2) bits name description access 31:0 bist fis transmit data 2 the data programmed into this register will form the contents of the third dword of any bist fis initiated by the intel ? 6300ESB ich. this register is not port specific ? its contents will be used for bist fis initiated on port 0 or port 1. although the 2nd and 3rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 3rd dw regardless of whether or not the ?t? bit is indicated in the bfcs register. r/w device: 31 function: 2 offset: e8h?ebh attribute: read/write default value: 00000000h size: 32-bit table 702. bus master ide i/o registers offset mnemonic register default type 00 bmicp command register primary 00h r/w 01 reserved ro 02 bmisp status register primary 00h r/wc 03 reserved ro 04-07 bmidp descriptor table pointer primary xx r/w 08 bmics command register secondary 00h r/w 09 reserved ro 0a bmiss status register secondary 00h r/wc 0b reserved ro 0c-0f bmids descriptor table pointer secondary xx r/w
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 767 20?intel ? 6300ESB ich 20.2.1 bmic[p,s]?bus master ide command register (d31:f2) table 703. bmic[p,s]?bus master ide command register (d31:f2) bits name description access 7:4 reserved reserved. returns ?0?. 3 read / write control (rwc) this bit sets the direction of the bus master transfer: this bit must not be changed when the bus master function is active. 0 = memory reads 1 = memory writes r/w 2:1 reserved reserved. returns ?0?. 0 start/stop bus master (start) 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. when this bit is reset while bus master operation is still active (i.e., the bus master ide active bit of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bit in the bus master ide status register for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controller. bus master operation begins when this bit is detected changing from a ?0? to a ?1?. the controller will transfer data between the ide device and memory only when this bit is set. master operation may be halted by writing a '0' to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bus master ide active bit being cleared or the interrupt bit of the bus master ide status register for that ide channel being set, or both. hardware does not clear this bit automatically. r/w device: 31 function: 2 offset: primary: 00h secondary: 08h attribute: read/write default value: 01h size: 8-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 768 order number: 300641-004us 20.2.2 bmis[p,s]?bus master ide status register (d31:f2) table 704. bmis[p,s]?bus master ide status register (d31:f2) bits name description access 7 prd interrupt status (prdis) 0 = when this bit is cleared by software, the interrupt is cleared. 1 = this bit is set when the host control execution of a prd that has its prd_int bit set. r/wc 6 drive 1 dma capable 0 = not capable. 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 1 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the intel ? 6300ESB ich does not use this bit. it is intended for systems that do not attach bmide to the pci bus. r/w 5 drive 0 dma capable 0 = not capable 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 0 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the intel ? 6300ESB ich does not use this bit. it is intended for systems that do not attach bmide to the pci bus. r/w 4:3 reserved reserved. returns ?0?. 2interrupt software may use this bit to determine if an ide device has asserted its interrupt line (irq 14 for the primary channel, and irq 15 for secondary). 0 = this bit is cleared by software writing a '1' to the bit position. when this bit is cleared while the interrupt is still active, this bit will remain clear until another assertion edge is detected on the interrupt line. 1 = set by the rising edge of the ide interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal i/o apic. when this bit is read as a ?1?, all data transferred from the drive is visible in system memory. r/wc 1error 0 = this bit is cleared by software writing a '1' to the bit position. 1 = this bit is set when the controller encounters a target abort or master abort when transferring data on pci. r/wc 0 bus master ide active (act) 0 = this bit is cleared by the intel ? 6300ESB ich when the last transfer for a region is performed, where eot for that region is set in the region descriptor. it is also cleared by the intel ? 6300ESB ich when the start bit is cleared in the command register. when this bit is read as a ?0?, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the intel ? 6300ESB ich when the start bit is written to the command register. ro device: 31 function: 2 offset: primary: 02h secondary: 0ah attribute: read/write clear default value: 00h size: 8-bit
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 769 20?intel ? 6300ESB ich 20.2.3 bmid[p,s]?bus master ide descriptor table pointer register (d31:f2) table 705. bmid[p,s]?bus master ide descriptor table pointer register (d31:f2) bits name description access 31:2 address of descriptor ta b l e ( a d d r ) corresponds to a[31:2]. the descriptor table must be dword-aligned. the descriptor table must not cross a 64-k boundary in memory. r/w 1:0 reserved reserved. device: 31 function: 2 offset: primary: 04h secondary: 0ch attribute: read/write default value: all bits undefined size: 32-bit
intel ? 6300ESB ich?20 intel ? 6300ESB i/o controller hub ds november 2007 770 order number: 300641-004us
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 771 21?intel ? 6300ESB ich package information 21 21.1 ball location figure 36. ball diagram (top view - left side) 12 34567891011121314 a vss ad[16] ad[20] pirq[b]# vss gpio[5] / pirq[h]# pirq[c] # gpio[3] / pirq[f]# nc nc nc lad[3] b vss ad[7] ad[11] stop# ad[22] ad[18] pirq[d]# vss gpio[2] / pirq[e] # req[2]# nc nc lframe # c vss c/be[0]# ad[2] vss vcc3_3 vss ad[15] vss vcc3_3 vss gnt[2]# vss vcc3_3 vss d ad[14] perr# vcc3_3 ad[5] ad[9] ad[6] vss req[0]# gnt[1]# gpio[4] / pirq[g] # vss req[3] # vss thrm# e ad[17] ad[10] irdy# serr# vss vcc3_3 ad[26] ad[24] vcc3_3 gnt[0]# v5ref pirq[a] # nc vss f ad[27] ad[19] vss c/be[2]# ad[3] ad[13] vss vss trdy# ad[4] vss vcc1_5 nc ldrq[0] # g gpio[33] / pxirq[0]# ad[31] vcc3_3 vss devsel# ad[12] c/be[1]# ad[1] par frame# ad[30] req[1] # gnt[3] # ldrq[1] # h gpio[34] / pxirq[1]# gpio[35] / pxirq[2]# vcc3_3 ad[29] c/be[3]# vss ad[23] ad[8] vcc3_3 vss ad[0] ad[28] j gpio[0] / pxreq[2] # pxpclko[0 ] gpio[36] / pxirq[3]# vss pciclk plock# vcc3_3 vcc1_5 k pxgnt0# pxad[31] vcc3_3 pxpclko[3 ] vcc3_3 pxpclko[ 2] ad[25] ad[21] l pxad[27] pxreq[0]# pxad[28] vss pxpclko[ 4] pxreq[1] # vss pxpclko[ 1] m pxad[25] pxad[26] vss vcc3_3 pxad[30] vss pxad[29] vcc3_3 vss vss vss n pxad[22] pxad[20] pxad[23] pxad[24] vcc3_3 pxc/ be[3]# vcc1_5 vss vss vss p pxad[17] pxad[18] vss vcc3_3 pxad[19] vss pxad[21] vss vss vss r pxad[16] pxc/be[2]# vcc3_3 pxirdy# vcc3_3 pxframe# pxpcixcap vss vss vss tpxplock# pxstop# pxdevsel # vss pxtrdy# vss pxad[15] vss vss vss u pxserr# pxc/be[1]# vss pxpar vcc3_3 pxperr# vcc3_3 vss vss vss v pxad[12] pxad[11] vss pxad[13] vss vccref pxad[2] vcc1_5 vss vss vss w pxad[8] pxad[9] vcc3_3 pxm66en vcc3_3 vcc3_3 pxad[1] pxad[5] y pxad[14] pxad[6] vss pxad[3] vss pxad[43] gpio[17] / pxgnt[3]# gpio[1] / pxreq[3] # aa pxc/ be[0]# pxad[4] vcc3_3 pxad[10] vcc3_3 pxad[7] pcixsbrst # vccpll0 ab pxad[47] pxad[45] pxad[42] vss pxgnt1# vcc3_3 pxad[44] vcc1_5 pxad[54 ] vcc1_5 vcc3_3 vss ac pxad[46] gpio[16] / pxgnt[2]# vss pxpclki pxpciclk pxad[39] vss vccref vcc3_3 pxad[50 ] vss pxrcom p vcc1_5 gpio[13] ad pxad[41] pxad[40] vcc3_3 pxad[38] vss pxad[37] pxad[36] pxpar64 vss pxad[48 ] vss vss nc slp_s4# ae raserr# pxad[35] pxad[34] pxad[33] pxreq64 # vss pxc/ be[4]# vcc3_3 pxad[51 ] pxad[49 ] vcc3_3 gpio[8] vss gpio[24] af pxad[32] pxad[0] vss pxack64# vcc3_3 pxc/ be[7]# pxc/ be[6]# vss pxad[53 ] vss gpio[12] vss vccsus 3_3 vss ag vss pxc/be[5]# vcc3_3 vss pxad[60] vss vcc3_3 vss vss gpio[27] vss vccsus3 _3 vss slp_s3# ah vss pxad[63] pxad[62] pxad[59 ] pxad[57] pxad[55] pxpcirst # gpio[25 ] ri# sysrese t# smlin k[1] smlin k[0] smbclk aj vss pxad[61] pxad[58 ] pxad[56] pxad[52] pme# gpio[28 ] pwrbtn # slp_s5# suscl k smbd ata nc 12 34567891011121314
intel ? 6300ESB ich?21 intel ? 6300ESB i/o controller hub ds november 2007 772 order number: 300641-004us figure 37. ball diagram (top view - right side) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 lad[2] siu0_ri# siu0_txd uart_clk siu1_dcd # siu1_cts # nc nc vccsus3_3 usbp3p vss usbp2p vss a lad[1] siu0_dcd # siu0_rxd siu1_dtr # siu1_dsr # nc nc gpio[7] vccsus3_3 usbp3n vss usbp2n vss vss b lad[0] vss vcc3_3 vss siu1_txd vss gpio[6] gpio[56] vccsus3_3 vss usbp1n vss usbp0p vss vss c vcc3_3 siu0_cts # siu1_ri# siu1_rxd nc gpio[37] vccsus1_5 gpio[57] vccsus3_3 vccsus3_3 usbp1p vss usbp0n vss usbrbias n d siu0_dtr # vss siu0_dsr # vss gpio[39] ac_sdou t ac_sdin1 ac_sdin2 ac_rst# oc[3]# vss vss vss usbrbias p clk48 e vss siu0_rts # vss vss vss ac_sync vccsus1_5 ac_sdin0 oc[1]# oc[0]# vss vss nc nc gpio[38] f vcc3_3 siu1_rts # serirq nc ac_bit_c lk vcc1_5 vccsus3_3 v5ref_su s oc[2]# vccsus1_5 nc vss nc nc gpio[42] g vss vcc1_5 vccsus3_3 vcc1_5 vccsus1_5 vccsus1_5 nc nc gpio[41] vss gpio[20] gpio[40] h vccpll3 nc vss vccsus1_5 vcc3_3 gpio[18] sataled# nc j vss vcc3_3 gpio[43] gpio[21] vss spkr nc nc k gpio[23] vss gpio[19] vss clk14 vss nc nc l vss vss vss vss vss vcc3_3 gpio[32] / wdt _tout# nc vss vcc3_3 hi11 nc m vss vss vss vss vcc1_5 vccsus1_5 hi9 vss vcchi hi10 hi8 n vss vss vss vss vcchi hiref vswing vcchi vss hi1 hi0 p vss vss vss vss vcchi hi7 vcchi vss vcchi hi3 hi2 r vss vss vss vss vcc1_5 hiclk vss hi6 hicomp hi_stb/ hi_stbs hi_stb#/ hi_stbf t vss vss vss vss vccsus1_5 ignne# v_cpu_io vss v_cpu_io hi5 hi4 u vss vss vss vss vss irq[15] sda[0] vss rcin# vss cpuslp# smi# v sdd[6] vcc3_3 siordy / (sdrstb/ swdmard y#) sdior# / (sdwstb/ prdmard y#) v_cpu_io a20m# init# stpclk# w vss sdd[8] sddack# sdiow# / (sdstop) vrmpwrg d vss intr nmi y vcca pda[2] sdd[4] vss sdd[0] sdcs3# thrmtrip # ferr# aa vss v5ref pdd[9] pdior# (/ pdwstb / prdmard y#) pddack# pdiow# (/pdstop) sdd[10] sdd[13] vcc3_3 sdd[2] sdcs1# a20gate ab vss vcc1_5 vcc1_5 vss vccrtc pdd[7] vcc3_3 pdd[10] irq[14] vss vcc3_3 sdd[11] vss sdd[15] sda[2] ac sus_stat # vccpll1 vss vcc1_5 vbias rtcx2 pdd[5] pdd[3] vss vcc3_3 pdcs3# sdd[3] sdd[14] sddreq sda[1] ad vccsus1_5 vccpll2 vcc1_5 vcc1_5 vss vcc1_5 rtcx1 vcc3_3 pdd[12] pdd[14] vss sdd[9] vss sdd[12] sdd[1] ae gpio[11] / smbalert # vcc1_5 vss sata[0]tx p vss sata[1]tx p vcc3_3 pwrok pdd[8] pddreq pdd[0] piordy (/ pdrstb / pwdmard y#) pdcs1# sdd[7] sdd[5] af vccsus1_5 vcc1_5 vss sata[0]tx n vss sata[1]tx n vss rtcrst# intruder # vss pdd[1] vss pda[1] pda[0] vss ag vss vss sataclkp vcc1_5 sata[0]rx p vss sata[1]rx p vss satarbia sp pdd[6] pdd[11] pdd[2] pdd[15] vss ah nc vss sataclkn vss sata[0]rx n vss sata[1]rx n vss satarbia sn rsmrst# pdd[4] pdd[13] vss aj 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 773 21?intel ? 6300ESB ich figure 38. mechanical drawing
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 774 table 706. signal list (alphabetical list) signal location a20gate ab29 a20m# w27 ac_bit_clk g19 ac_rst# e23 ac_sdin0 f22 ac_sdin1 e21 ac_sdin2 e22 ac_sdout e20 ac_sync f20 ad[0] h11 ad[1] g8 ad[2] c3 ad[3] f5 ad[4] f10 ad[5] d4 ad[6] d6 ad[7] b3 ad[8] h8 ad[9] d5 ad[10] e2 ad[11] b4 ad[12] g6 ad[13] f6 ad[14] d1 ad[15] c7 ad[16] a4 ad[17] e1 ad[18] b7 ad[19] f2 ad[20] a5 ad[21] k8 ad[22] b6 ad[23] h7 ad[24] e8 ad[25] k7 ad[26] e7 ad[27] f1 ad[28] h12 ad[29] h4 ad[30] g11 ad[31] g2 c/be[0]# c2 c/be[1]# g7 c/be[2]# f4 c/be[3]# h5 clk14 l26 clk48 e29 cpuslp# v28 devsel# g5 ferr# aa29 frame# g10 gnt[0]# e10 gnt[1]# d9 gnt[2]# c11 gnt[3]# g13 gpio[0] / pxreq[2]# j1 gpio[1] / pxreq[3]# y8 gpio[2] / pirq[e]# b10 gpio[3] / pirq[f]# a10 gpio[4] / pirq[g]# d10 gpio[5] / pirq[h]# a8 gpio[6] c21 gpio[7] b22 gpio[8] ae12 gpio[11] / smbalert# af15 gpio[12] af11 gpio[13] ac14 gpio[16] / pxgnt[2]# ac2 gpio[17] / pxgnt[3]# y7 gpio[18] j27 gpio[19] l24 gpio[20] h28 gpio[21] k25 gpio[23] l22 gpio[24] ae14 gpio[25] ah9 gpio[27] ag10 gpio[28] aj9 gpio[32] / wdt _tout# m24 gpio[33] / pxirq[0]# g1 gpio[34] / pxirq[1]# h1 gpio[35] / pxirq[2]# h2 gpio[36] / pxirq[3]# j3 gpio[37] d20 gpio[38] f29 gpio[39] e19 gpio[40] h29 gpio[41] h26 gpio[42] g29 table 706. signal list (alphabetical list) signal location
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 775 gpio[43] k24 gpio[56] c22 gpio[57] d22 hi_stb#/hi_stbf t29 hi_stb/hi_stbs t28 hiref p24 hihihihi0 p29 hi1 p28 hi2 r29 hi3 r28 hi4 u29 hi5 u28 hi6 t26 hi7 r24 hi8 n29 hi9 n25 hi10 n28 hi11 m28 hiclk t24 hicomp t27 ignne# u24 init# w28 intr y28 intruder# ag23 irdy# e3 irq[14] ac23 irq[15] v23 lad[0] c15 lad[1] b15 lad[2] a15 lad[3] a14 ldrq[0]# f14 ldrq[1]# g14 lframe# b14 nc b20 nc b21 nc b13 nc b12 nc a11 nc a12 nc a13 nc a21 nc a22 nc ad13 nc aj14 nc aj15 nc d19 nc e13 nc f13 nc f27 nc f28 table 706. signal list (alphabetical list) signal location nc g18 nc g25 nc g27 nc g28 nc h24 nc h25 nc j23 nc j29 nc k28 nc k29 nc l28 nc l29 nc m25 nc m29 nmi y29 oc[0]# f24 oc[1]# f23 oc[2]# g23 oc[3]# e24 par g9 pciclk j5 pcixsbrst# aa7 pda[0] ag28 pda[1] ag27 pda[2] aa23 pdcs1# af27 pdcs3# ad25 pdd[0] af25 pdd[1] ag25 pdd[2] ah26 pdd[3] ad22 pdd[4] aj25 pdd[5] ad21 pdd[6] ah24 pdd[7] ac20 pdd[8] af23 pdd[9] ab20 pdd[10] ac22 pdd[11] ah25 pdd[12] ae23 pdd[13] aj26 pdd[14] ae24 pdd[15] ah27 pddack# ab22 pddreq af24 pdior# (/ pdwstb / prdmardy#) ab21 pdiow# (/ pdstop) ab23 perr# d2 table 706. signal list (alphabetical list) signal location
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 776 piordy (/pdrstb /pwdmardy#) af26 pirq[a]# e12 pirq[b]# a6 pirq[c]# a9 pirq[d]# b8 plock# j6 pme# aj8 pwrbtn# aj10 pwrok af22 pxack64# af4 pxad[0] af2 pxad[1] w7 pxad[2] v7 pxad[3] y4 pxad[4] aa2 pxad[5] w8 pxad[6] y2 pxad[7] aa6 pxad[8] w1 pxad[9] w2 pxad[10] aa4 pxad[11] v2 pxad[12] v1 pxad[13] v4 pxad[14] y1 pxad[15] t7 pxad[16] r1 pxad[17] p1 pxad[18] p2 pxad[19] p5 pxad[20] n2 pxad[21] p7 pxad[22] n1 pxad[23] n3 pxad[24] n4 pxad[25] m1 pxad[26] m2 pxad[27] l1 pxad[28] l3 pxad[29] m7 pxad[30] m5 pxad[31] k2 pxad[32] af1 pxad[33] ae4 pxad[34] ae3 pxad[35] ae2 pxad[36] ad7 pxad[37] ad6 pxad[38] ad4 pxad[39] ac6 table 706. signal list (alphabetical list) signal location pxad[40] ad2 pxad[41] ad1 pxad[42] ab3 pxad[43] y6 pxad[44] ab7 pxad[45] ab2 pxad[46] ac1 pxad[47] ab1 pxad[48] ad10 pxad[49] ae10 pxad[50] ac10 pxad[51] ae9 pxad[52] aj7 pxad[53] af9 pxad[54] ab9 pxad[55] ah7 pxad[56] aj6 pxad[57] ah6 pxad[58] aj5 pxad[59] ah5 pxad[60] ag5 pxad[61] aj4 pxad[62] ah4 pxad[63] ah3 pxc/be[0]# aa1 pxc/be[1]# u2 pxc/be[2]# r2 pxc/be[3]# n6 pxc/be[4]# ae7 pxc/be[5]# ag2 pxc/be[6]# af7 pxc/be[7]# af6 pxdevsel# t3 pxframe# r6 pxgnt0# k1 pxgnt1# ab5 pxirdy# r4 pxm66en w4 pxpar u4 pxpar64 ad8 pxpciclk ac5 pxpcirst# ah8 pxpcixcap r7 pxpclki ac4 pxpclko[0] j2 pxpclko[1] l8 pxpclko[2] k6 pxpclko[3] k4 pxpclko[4] l5 pxperr# u6 pxplock# t1 table 706. signal list (alphabetical list) signal location
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 777 pxrcomp ac12 pxreq[0]# l2 pxreq[1]# l6 pxreq64# ae5 pxserr# u1 pxstop# t2 pxtrdy# t5 raserr# ae1 rcin# v26 req[0]# d8 req[1]# g12 req[2]# b11 req[3]# d12 ri# ah10 rsmrst# aj24 rtcrst# ag22 rtcx1 ae21 rtcx2 ad20 sata[0]rxn aj19 sata[0]rxp ah19 sata[0]txn ag18 sata[0]txp af18 sata[1]rxn aj21 sata[1]rxp ah21 sata[1]txn ag20 sata[1]txp af20 sataclkn aj17 sataclkp ah17 sataled# j28 satarbiasn aj23 satarbiasp ah23 sda[0] v24 sda[1] ad29 sda[2] ac29 sdcs1# ab28 sdcs3# aa27 sdd[0] aa26 sdd[1] ae29 sdd[2] ab27 sdd[3] ad26 sdd[4] aa24 sdd[5] af29 sdd[6] w22 sdd[7] af28 sdd[8] y23 sdd[9] ae26 sdd[10] ab24 sdd[11] ac26 sdd[12] ae28 sdd[13] ab25 sdd[14] ad27 table 706. signal list (alphabetical list) signal location sdd[15] ac28 sddack# y24 sddreq ad28 sdior# / (sdwstb/ prdmardy#) w25 sdiow# / (sdstop) y25 serirq g17 serr# e4 siordy / (sdrstb/ swdmardy#) w24 siu0_cts# d16 siu0_dcd# b16 siu0_dsr# e17 siu0_dtr# e15 siu0_ri# a16 siu0_rts# f16 siu0_rxd b17 siu0_txd a17 siu1_cts# a20 siu1_dcd# a19 siu1_dsr# b19 siu1_dtr# b18 siu1_ri# d17 siu1_rts# g16 siu1_rxd d18 siu1_txd c19 slp_s3# ag14 slp_s4# ad14 slp_s5# aj11 smbclk ah14 smbdata aj13 smi# v29 smlink[0] ah13 smlink[1] ah12 spkr k27 stop# b5 stpclk# w29 sus_stat# ad15 susclk aj12 sysreset# ah11 thrm# d14 thrmtrip# aa28 trdy# f9 uart_clk a18 usbp0n d27 usbp0p c27 usbp1n c25 usbp1p d25 usbp2n b26 table 706. signal list (alphabetical list) signal location
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 778 usbp2p a26 usbp3n b24 usbp3p a24 usbrbiasn d29 usbrbiasp e28 v_cpu_io u25 v_cpu_io u27 v_cpu_io w26 v5ref ab19 v5ref e11 v5ref_sus g22 vbias ad19 vcc1_5 ab10 vcc1_5 ab8 vcc1_5 ac13 vcc1_5 ac16 vcc1_5 ac17 vcc1_5 ad18 vcc1_5 ae17 vcc1_5 ae18 vcc1_5 ae20 vcc1_5 af16 vcc1_5 ag16 vcc1_5 ah18 vcc1_5 f12 vcc1_5 g20 vcc1_5 h19 vcc1_5 h21 vcc1_5 j8 vcc1_5 n23 vcc1_5 n7 vcc1_5 t23 vcc1_5 v8 vcc3_3 aa3 vcc3_3 aa5 vcc3_3 ab11 vcc3_3 ab26 vcc3_3 ab6 vcc3_3 ac21 vcc3_3 ac25 vcc3_3 ac9 vcc3_3 ad24 vcc3_3 ad3 vcc3_3 ae11 vcc3_3 ae22 vcc3_3 ae8 vcc3_3 af21 vcc3_3 af5 vcc3_3 ag3 vcc3_3 ag7 vcc3_3 c13 table 706. signal list (alphabetical list) signal location vcc3_3 c17 vcc3_3 c5 vcc3_3 c9 vcc3_3 d15 vcc3_3 d3 vcc3_3 e6 vcc3_3 e9 vcc3_3 g15 vcc3_3 g3 vcc3_3 h3 vcc3_3 h9 vcc3_3 j26 vcc3_3 j7 vcc3_3 k23 vcc3_3 k3 vcc3_3 k5 vcc3_3 m23 vcc3_3 m27 vcc3_3 m4 vcc3_3 m8 vcc3_3 n5 vcc3_3 p4 vcc3_3 r3 vcc3_3 r5 vcc3_3 u5 vcc3_3 u7 vcc3_3 w23 vcc3_3 w3 vcc3_3 w5 vcc3_3 w6 vcca aa22 vcchi n27 vcchi p23 vcchi p26 vcchi r23 vcchi r25 vcchi r27 vccpll0 aa8 vccpll1 ad16 vccpll2 ae16 vccpll3 j22 vccref ac8 vccref v6 vccrtc ac19 vccsus1_5 ae15 vccsus1_5 ag15 vccsus1_5 d21 vccsus1_5 f21 vccsus1_5 g24 vccsus1_5 h22 vccsus1_5 h23 table 706. signal list (alphabetical list) signal location
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 779 vccsus1_5 j25 vccsus1_5 n24 vccsus1_5 u23 vccsus3_3 b23 vccsus3_3 a23 vccsus3_3 af13 vccsus3_3 ag12 vccsus3_3 c23 vccsus3_3 d23 vccsus3_3 d24 vccsus3_3 g21 vccsus3_3 h20 vrmpwrgd y26 vss b2 vss b25 vss b27 vss b28 vss b9 vss a25 vss a27 vss a3 vss a7 vss aa25 vss ab12 vss ab18 vss ab4 vss ac11 vss ac15 vss ac18 vss ac24 vss ac27 vss ac3 vss ac7 vss ad11 vss ad12 vss ad17 vss ad23 vss ad5 vss ad9 vss ae13 vss ae19 vss ae25 vss ae27 vss ae6 vss af10 vss af12 vss af14 vss af17 vss af19 vss af3 vss af8 table 706. signal list (alphabetical list) signal location vss ag1 vss ag11 vss ag13 vss ag17 vss ag19 vss ag21 vss ag24 vss ag26 vss ag29 vss ag4 vss ag6 vss ag8 vss ag9 vss ah15 vss ah16 vss ah2 vss ah20 vss ah22 vss ah28 vss aj16 vss aj18 vss aj20 vss aj22 vss aj27 vss aj3 vss c1 vss c10 vss c12 vss c14 vss c16 vss c18 vss c20 vss c24 vss c26 vss c28 vss c29 vss c4 vss c6 vss c8 vss d11 vss d13 vss d26 vss d28 vss d7 vss e14 vss e16 vss e18 vss e25 vss e26 vss e27 vss e5 table 706. signal list (alphabetical list) signal location
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 780 vss f11 vss f15 vss f17 vss f18 vss f19 vss f25 vss f26 vss f3 vss f7 vss f8 vss g26 vss g4 vss h10 vss h18 vss h27 vss h6 vss j24 vss j4 vss k22 vss k26 vss l23 vss l25 vss l27 vss l4 vss l7 vss m12 vss m13 vss m14 vss m15 vss m16 vss m17 vss m18 vss m22 vss m26 vss m3 vss m6 vss n12 vss n13 vss n14 vss n15 vss n16 vss n17 vss n18 vss n26 vss p12 vss p13 vss p14 vss p15 vss p16 vss p17 vss p18 table 706. signal list (alphabetical list) signal location vss p27 vss p3 vss p6 vss r12 vss r13 vss r14 vss r15 vss r16 vss r17 vss r18 vss r26 vss t12 vss t13 vss t14 vss t15 vss t16 vss t17 vss t18 vss t25 vss t4 vss t6 vss u12 vss u13 vss u14 vss u15 vss u16 vss u17 vss u18 vss u26 vss u3 vss v12 vss v13 vss v14 vss v15 vss v16 vss v17 vss v18 vss v22 vss v25 vss v27 vss v3 vss v5 vss y22 vss y27 vss y3 vss y5 vswing p25 table 706. signal list (alphabetical list) signal location
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 781 table 707. signal list (by location) location signal a3 vss a4 ad[16] a5 ad[20] a6 pirq[b]# a7 vss a8 gpio[5] / pirq[h]# a9 pirq[c]# a10 gpio[3] / pirq[f]# a11 nc a12 nc a13 nc a14 lad[3] a15 lad[2] a16 siu0_ri# a17 siu0_txd a18 uart_clk a19 siu1_dcd# a20 siu1_cts# a21 nc a22 nc a23 vccsus3_3 a24 usbp3p a25 vss a26 usbp2p a27 vss aa1 pxc/be[0]# aa2 pxad[4] aa3 vcc3_3 aa4 pxad[10] aa5 vcc3_3 aa6 pxad[7] aa7 pcixsbrst# aa8 vccpll0 aa22 vcca aa23 pda[2] aa24 sdd[4] aa25 vss aa26 sdd[0] aa27 sdcs3# aa28 thrmtrip# aa29 ferr# ab1 pxad[47] ab2 pxad[45] ab3 pxad[42] ab4 vss ab5 pxgnt1# ab6 vcc3_3 ab7 pxad[44] ab8 vcc1_5 ab9 pxad[54] ab10 vcc1_5 ab11 vcc3_3 ab12 vss ab18 vss ab19 v5ref ab20 pdd[9] ab21 pdior# (/ pdwstb / prdmardy#) ab22 pddack# ab23 pdiow# (/ pdstop) ab24 sdd[10] ab25 sdd[13] ab26 vcc3_3 ab27 sdd[2] ab28 sdcs1# ab29 a20gate ac1 pxad[46] ac2 gpio[16] / pxgnt[2]# ac3 vss ac4 pxpclki ac5 pxpciclk ac6 pxad[39] ac7 vss ac8 vccref ac9 vcc3_3 ac10 pxad[50] ac11 vss ac12 pxrcomp ac13 vcc1_5 ac14 gpio[13] ac15 vss ac16 vcc1_5 ac17 vcc1_5 ac18 vss ac19 vccrtc ac20 pdd[7] ac21 vcc3_3 ac22 pdd[10] ac23 irq[14] ac24 vss ac25 vcc3_3 ac26 sdd[11] ac27 vss ac28 sdd[15] ac29 sda[2] ad1 pxad[41] ad2 pxad[40] ad3 vcc3_3 ad4 pxad[38] ad5 vss table 707. signal list (by location) location signal
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 782 ad6 pxad[37] ad7 pxad[36] ad8 pxpar64 ad9 vss ad10 pxad[48] ad11 vss ad12 vss ad13 nc ad14 slp_s4# ad15 sus_stat# ad16 vccpll1 ad17 vss ad18 vcc1_5 ad19 vbias ad20 rtcx2 ad21 pdd[5] ad22 pdd[3] ad23 vss ad24 vcc3_3 ad25 pdcs3# ad26 sdd[3] ad27 sdd[14] ad28 sddreq ad29 sda[1] ae1 raserr# ae2 pxad[35] ae3 pxad[34] ae4 pxad[33] ae5 pxreq64# ae6 vss ae7 pxc/be[4]# ae8 vcc3_3 ae9 pxad[51] ae10 pxad[49] ae11 vcc3_3 ae12 gpio[8] ae13 vss ae14 gpio[24] ae15 vccsus1_5 ae16 vccpll2 ae17 vcc1_5 ae18 vcc1_5 ae19 vss ae20 vcc1_5 ae21 rtcx1 ae22 vcc3_3 ae23 pdd[12] ae24 pdd[14] ae25 vss ae26 sdd[9] ae27 vss ae28 sdd[12] table 707. signal list (by location) location signal ae29 sdd[1] af1 pxad[32] af2 pxad[0] af3 vss af4 pxack64# af5 vcc3_3 af6 pxc/be[7]# af7 pxc/be[6]# af8 vss af9 pxad[53] af10 vss af11 gpio[12] af12 vss af13 vccsus3_3 af14 vss af15 gpio[11] / smbalert# af16 vcc1_5 af17 vss af18 sata[0]txp af19 vss af20 sata[1]txp af21 vcc3_3 af22 pwrok af23 pdd[8] af24 pddreq af25 pdd[0] af26 piordy (/ pdrstb / pwdmardy#) af27 pdcs1# af28 sdd[7] af29 sdd[5] ag1 vss ag2 pxc/be[5]# ag3 vcc3_3 ag4 vss ag5 pxad[60] ag6 vss ag7 vcc3_3 ag8 vss ag9 vss ag10 gpio[27] ag11 vss ag12 vccsus3_3 ag13 vss ag14 slp_s3# ag15 vccsus1_5 ag16 vcc1_5 ag17 vss ag18 sata[0]txn ag19 vss table 707. signal list (by location) location signal
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 783 ag20 sata[1]txn ag21 vss ag22 rtcrst# ag23 intruder# ag24 vss ag25 pdd[1] ag26 vss ag27 pda[1] ag28 pda[0] ag29 vss ah2 vss ah3 pxad[63] ah4 pxad[62] ah5 pxad[59] ah6 pxad[57] ah7 pxad[55] ah8 pxpcirst# ah9 gpio[25] ah10 ri# ah11 sysreset# ah12 smlink[1] ah13 smlink[0] ah14 smbclk ah15 vss ah16 vss ah17 sataclkp ah18 vcc1_5 ah19 sata[0]rxp ah20 vss ah21 sata[1]rxp ah22 vss ah23 satarbiasp ah24 pdd[6] ah25 pdd[11] ah26 pdd[2] ah27 pdd[15] ah28 vss aj3 vss aj4 pxad[61] aj5 pxad[58] aj6 pxad[56] aj7 pxad[52] aj8 pme# aj9 gpio[28] aj10 pwrbtn# aj11 slp_s5# aj12 susclk aj13 smbdata aj14 nc aj15 nc aj16 vss aj17 sataclkn table 707. signal list (by location) location signal aj18 vss aj19 sata[0]rxn aj20 vss aj21 sata[1]rxn aj22 vss aj23 satarbiasn aj24 rsmrst# aj25 pdd[4] aj26 pdd[13] aj27 vss b2 vss b3 ad[7] b4 ad[11] b5 stop# b6 ad[22] b7 ad[18] b8 pirq[d]# b9 vss b10 gpio[2] / pirq[e]# b11 req[2]# b12 nc b13 nc b14 lframe# b15 lad[1] b16 siu0_dcd# b17 siu0_rxd b18 siu1_dtr# b19 siu1_dsr# b20 nc b21 nc b22 gpio[7] b23 vccsus3_3 b24 usbp3n b25 vss b26 usbp2n b27 vss b28 vss c1 vss c2 c/be[0]# c3 ad[2] c4 vss c5 vcc3_3 c6 vss c7 ad[15] c8 vss c9 vcc3_3 c10 vss c11 gnt[2]# c12 vss c13 vcc3_3 c14 vss table 707. signal list (by location) location signal
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 784 c15 lad[0] c16 vss c17 vcc3_3 c18 vss c19 siu1_txd c20 vss c21 gpio[6] c22 gpio[56] c23 vccsus3_3 c24 vss c25 usbp1n c26 vss c27 usbp0p c28 vss c29 vss d1 ad[14] d2 perr# d3 vcc3_3 d4 ad[5] d5 ad[9] d6 ad[6] d7 vss d8 req[0]# d9 gnt[1]# d10 gpio[4] / pirq[g]# d11 vss d12 req[3]# d13 vss d14 thrm# d15 vcc3_3 d16 siu0_cts# d17 siu1_ri# d18 siu1_rxd d19 nc d20 gpio[37] d21 vccsus1_5 d22 gpio[57] d23 vccsus3_3 d24 vccsus3_3 d25 usbp1p d26 vss d27 usbp0n d28 vss d29 usbrbiasn e1 ad[17] e2 ad[10] e3 irdy# e4 serr# e5 vss e6 vcc3_3 e7 ad[26] table 707. signal list (by location) location signal e8 ad[24] e9 vcc3_3 e10 gnt[0]# e11 v5ref e12 pirq[a]# e13 nc e14 vss e15 siu0_dtr# e16 vss e17 siu0_dsr# e18 vss e19 gpio[39] e20 ac_sdout e21 ac_sdin1 e22 ac_sdin2 e23 ac_rst# e24 oc[3]# e25 vss e26 vss e27 vss e28 usbrbiasp e29 clk48 f1 ad[27] f2 ad[19] f3 vss f4 c/be[2]# f5 ad[3] f6 ad[13] f7 vss f8 vss f9 trdy# f10 ad[4] f11 vss f12 vcc1_5 f13 nc f14 ldrq[0]# f15 vss f16 siu0_rts# f17 vss f18 vss f19 vss f20 ac_sync f21 vccsus1_5 f22 ac_sdin0 f23 oc[1]# f24 oc[0]# f25 vss f26 vss f27 nc f28 nc f29 gpio[38] table 707. signal list (by location) location signal
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 785 g1 gpio[33] / pxirq[0]# g2 ad[31] g3 vcc3_3 g4 vss g5 devsel# g6 ad[12] g7 c/be[1]# g8 ad[1] g9 par g10 frame# g11 ad[30] g12 req[1]# g13 gnt[3]# g14 ldrq[1]# g15 vcc3_3 g16 siu1_rts# g17 serirq g18 nc g19 ac_bit_clk g20 vcc1_5 g21 vccsus3_3 g22 v5ref_sus g23 oc[2]# g24 vccsus1_5 g25 nc g26 vss g27 nc g28 nc g29 gpio[42] h1 gpio[34] / pxirq[1]# h2 gpio[35] / pxirq[2]# h3 vcc3_3 h4 ad[29] h5 c/be[3]# h6 vss h7 ad[23] h8 ad[8] h9 vcc3_3 h10 vss h11 ad[0] h12 ad[28] h18 vss h19 vcc1_5 h20 vccsus3_3 h21 vcc1_5 h22 vccsus1_5 h23 vccsus1_5 h24 nc h25 nc table 707. signal list (by location) location signal h26 gpio[41] h27 vss h28 gpio[20] h29 gpio[40] j1 gpio[0] / pxreq[2]# j2 pxpclko[0] j3 gpio[36] / pxirq[3]# j4 vss j5 pciclk j6 plock# j7 vcc3_3 j8 vcc1_5 j22 vccpll3 j23 nc j24 vss j25 vccsus1_5 j26 vcc3_3 j27 gpio[18] j28 sataled# j29 nc k1 pxgnt0# k2 pxad[31] k3 vcc3_3 k4 pxpclko[3] k5 vcc3_3 k6 pxpclko[2] k7 ad[25] k8 ad[21] k22 vss k23 vcc3_3 k24 gpio[43] k25 gpio[21] k26 vss k27 spkr k28 nc k29 nc l1 pxad[27] l2 pxreq[0]# l3 pxad[28] l4 vss l5 pxpclko[4] l6 pxreq[1]# l7 vss l8 pxpclko[1] l22 gpio[23] l23 vss l24 gpio[19] l25 vss l26 clk14 l27 vss table 707. signal list (by location) location signal
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 786 l28 nc l29 nc m1 pxad[25] m2 pxad[26] m3 vss m4 vcc3_3 m5 pxad[30] m6 vss m7 pxad[29] m8 vcc3_3 m12 vss m13 vss m14 vss m15 vss m16 vss m17 vss m18 vss m22 vss m23 vcc3_3 m24 gpio[32] / wdt _tout# m25 nc m26 vss m27 vcc3_3 m28 hi11 m29 nc n1 pxad[22] n2 pxad[20] n3 pxad[23] n4 pxad[24] n5 vcc3_3 n6 pxc/be[3]# n7 vcc1_5 n12 vss n13 vss n14 vss n15 vss n16 vss n17 vss n18 vss n23 vcc1_5 n24 vccsus1_5 n25 hi9 n26 vss n27 vcchi n28 hi10 n29 hi8 p1 pxad[17] p2 pxad[18] p3 vss p4 vcc3_3 p5 pxad[19] table 707. signal list (by location) location signal p6 vss p7 pxad[21] p12 vss p13 vss p14 vss p15 vss p16 vss p17 vss p18 vss p23 vcchi p24 hiref p25 vswing p26 vcchi p27 vss p28 hi1 p29 hi0 r1 pxad[16] r2 pxc/be[2]# r3 vcc3_3 r4 pxirdy# r5 vcc3_3 r6 pxframe# r7 pxpcixcap r12 vss r13 vss r14 vss r15 vss r16 vss r17 vss r18 vss r23 vcchi r24 hi7 r25 vcchi r26 vss r27 vcchi r28 hi3 r29 hi2 t1 pxplock# t2 pxstop# t3 pxdevsel# t4 vss t5 pxtrdy# t6 vss t7 pxad[15] t12 vss t13 vss t14 vss t15 vss t16 vss t17 vss t18 vss t23 vcc1_5 table 707. signal list (by location) location signal
package information intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 787 t24 hiclk t25 vss t26 hi6 t27 hicomp t28 hi_stb/ hi_stbs t29 hi_stb#/ hi_stbf u1 pxserr# u2 pxc/be[1]# u3 vss u4 pxpar u5 vcc3_3 u6 pxperr# u7 vcc3_3 u12 vss u13 vss u14 vss u15 vss u16 vss u17 vss u18 vss u23 vccsus1_5 u24 ignne# u25 v_cpu_io u26 vss u27 v_cpu_io u28 hi5 u29 hi4 v1 pxad[12] v2 pxad[11] v3 vss v4 pxad[13] v5 vss v6 vccref v7 pxad[2] v8 vcc1_5 v12 vss v13 vss v14 vss v15 vss v16 vss v17 vss v18 vss v22 vss v23 irq[15] v24 sda[0] v25 vss v26 rcin# v27 vss v28 cpuslp# v29 smi# table 707. signal list (by location) location signal w1 pxad[8] w2 pxad[9] w3 vcc3_3 w4 pxm66en w5 vcc3_3 w6 vcc3_3 w7 pxad[1] w8 pxad[5] w22 sdd[6] w23 vcc3_3 w24 siordy / (sdrstb/ swdmardy#) w25 sdior# / (sdwstb/ prdmardy#) w26 v_cpu_io w27 a20m# w28 init# w29 stpclk# y1 pxad[14] y2 pxad[6] y3 vss y4 pxad[3] y5 vss y6 pxad[43] y7 gpio[17] / pxgnt[3]# y8 gpio[1] / pxreq[3]# y22 vss y23 sdd[8] y24 sddack# y25 sdiow# / (sdstop) y26 vrmpwrgd y27 vss y28 intr y29 nmi table 707. signal list (by location) location signal
21? intel ? 6300ESB ich intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 788
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 789 22?intel ? 6300ESB ich electrical characteristics 22 this chapter provides the absolute maximum ratings, dc characteristics, ac characteristics and ac timing diagrams for the intel ? 6300ESB ich component. 22.1 absolute maximum ratings voltage on any 3.3 v pin with respect to ground = ?0.5 to vcc3_3 +0.5 v voltage on any 5 v tolerant pin with respect to ground (v5ref = 5 v) = ?0.5 to v5ref + 0.5 v 1.5 v supply voltage with respect to vss = ?0.5 to +2.1 v 3.3 v supply voltage with respect to vss = ?0.5 to +4.6 v 5.0 v supply voltage (v5ref) with respect to vss = ?0.5 to +5.5 v warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. see section 22.2, ?functional operating range? for the functional operating range of the intel ? 6300ESB ich. 22.2 functional operating range all of the ac and dc characteristics specified in this document assume that the intel ? 6300ESB ich component is operating within the functional operating range given in this section. operation outside of the functional operating range is not recommended, and extended exposure outside of the functional operating range may affect component reliability. ? 1.5 v supply voltage (vcc1_5, vcchi, vccsus1_5) with respect to vss = 1.425 v to 1.575 v ? 3.3 v supply voltage (vcc3_3, vccsus3_3) with respect to vss = 3.135 v to 3.465 v ? 5 v supply voltage (v5ref, v5ref_sus) with respect to vss = 4.75 v to 5.25 v ? v_cpu_io voltage with respect to vss = 0.8 v?1.75 v ? vccrtc voltage with respect to vss = 2.0 v to 3.6 v ? case temperature under bias = 0 o c to +105 o c note: a non-condensing environment is required to maintain rtc accuracy.
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 790 order number: 300641-004us 22.3 dc characteristics table 708. dc current characteristics (preliminary) power plane maximum power consumption symbol so s1 s3/s4/s5 g3 vcc1_5 core 1184 ma 573 ma n/a n/a vcc3_3 i/o 875 ma 1.3 ma n/a n/a vccsus1_5 75 ma 45 ma 15.6 ma n/a vccsus3_3 142 ma 2.1 ma 2.3 ma n/a vcchi 99 ma 99 ma n/a n/a v5ref 10 a 10 a n/a n/a v5ref_sus 10 a 10 a 10 a n/a vccref (3.3v) 150 a 150 a n/a n/a v_cpu_io 2.5 ma 2.5 ma n/a n/a vccrtc n/a n/a n/a 8.5a (1) 1. icc(rtc) data is taken with vcc(rtc) at 3.0 v while the system is in a mechanical off (g3) state at room temperature (25 o c). table 709. dc characteristic input signal association (sheet 1 of 2) symbol associated signals v ih0 /v il0 pci-x signals: pxad[63:0], pxc/be[7:0]#, pxdevsel#, pxframe#, pxirdy#, pxtrdy#, pxstop#, pxpar, pxperr#, pxplock#, pxserr#, pxreq[1:0]#,pxreq[2]#/gpio[0], pxreq[3]#/gpio[1], pxrcomp, pxpar64, pxreq64#, pxack64#, pxm66en, pxpcixcap, pxirq[3:0]/gpio[36:33] clock signals : pxpclki, pxpciclk v ih1 /v il1 (5v tolerant) pci signals: ad[31:0], c/be[3:0]#, devsel#, frame#, irdy#, trdy#, stop#, par, perr#, plock#, serr#, req[3:0]# v ih2 /v il2 (5v tolerant) interrupt signals: irq[15:14], pirq[d:a]#, pirq[h:e]#/gpio[5:2] legacy signals: rcin#, a20gate v ih3 /v il3 clock signals : clk48, clk14 interrupt signals: serirq power management signals: pme#, pwrbtn#, ri#, sys_reset#, thrm# gpio signals: gpio[43:37,31, 28:27, 25:24, 13:12, 8:6] v ih4 /v il4 clock signals: pciclk lpc/fwh signals: ldrq[1:0]#, lad[3:0]/fwh[3:0], lframe# siu signals: siu0_cts#, siu0_dcd#, siu0_dsr#, siu0_ri#, siu0_rxd, siu1_cts#; siu1_dcd#, siu1_dsr#, siu1_ri#, siu1_rxd , uart_clk v ih5 /v il5 smbus signals: smbclk, smbdata system management signals: intruder#, smlink[1:0], smbalert#/gpio[11] power management signals: rsmrst#, rtcrst#, pwrok v il6 /v ih6 cpu signals: ferr#, thrmtrip# v il7 /v ih7 hub interface signals : hi[11:0], hi_stbs, hi_stbf v il8 /v ih8 real time clock signals: rtcx1, rtcx2
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 791 22?intel ? 6300ESB ich v il9 /v ih9 sata signals: sata[1:0]rx[p,n] v il10 /v ih10 (5v tolerant) usb signals: oc[3:0]# v il11 /v ih11 ac?97 signals: ac_bitclk, ac_sdin[2:0] v il12 /v ih12 clock signals: sataclkp, sataclkn (clk100p, clk100n) v+/v-/vhys/ vthravg/vring (5v tolerant) ide signals: pdd[15:0], sdd[15:0], pddreq, piordy, sddreq, siordy for ultra dma mode 4 and lower these signals, follow the dc characteristics for v ih2 /v il2. v di / v cm / v se usb signals: usbp[3:0][p,n] (low-speed and full-speed) v hssq / v hsdsc / v hscm usb signals: usbp[3:0][p,n] (in high-speed mode) table 710. dc input characteristics (sheet 1 of 2) symbol parameter min max unit notes v il0 input low voltage -0.5 0.35vcc3_3 v v ih0 input high voltage 0.5vcc3_3 vcc3_3 + 0.5 v v il1 input low voltage -0.5 0.3vcc3_3 v v ih1 input high voltage 0.5vcc3_3 v5ref + 0.5 v v il2 input low voltage -0.5 0.8 v v ih2 input high voltage 2.0 v5ref + 0.5 v v il3 input low voltage -0.5 0.8 v v ih3 input high voltage 2.0 vcc3_3 + 0.5 v v il4 input low voltage -0.5 0.3vcc3_3 v v ih4 input high voltage 0.5vcc3_3 vcc3_3 + 0.5 v v il5 input low voltage -0.5 0.8 v v ih5 input high voltage 2.1 vccsus3_3 + 0.5 v v il6 input low voltage -0.15 0.58(v_cpu_io) v v ih6 input high voltage 0.73(v_cpu_io) v_cpu_io v v il7 input low voltage -0.3 hiref - 0.10 v note 7 v ih7 input high voltage hiref + 0.10 1.2 v note 7 v il8 input low voltage -0.5 0.10 v v ih8 input high voltage 0.40 1.0 v notes: 1. applies to ultra dma modes greater than ultra dma mode 4. 2. this is an ac characteristic that represents transient values for these signals. 3. v di = | usbpx[p] - usbpx[n]. 4. includes v di range. 5. applies to high-speed usb 2.0. 6. sata vdiff,rx is measured at the sata connector on the receive side. 7. when probed at the receiver pin of the ich for data/strobe, the waveform may show a ?knee? due to package parasitics. simulation verifies that this ?knee? represents no risk, since a clean waveform is present at the ich ball input due to internal receiver termination. table 709. dc characteristic input signal association (sheet 2 of 2) symbol associated signals
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 792 order number: 300641-004us v il9 differential input low voltage 325 mvp-p note 6 v ih9 differential input high voltage 600 mvp-p note 6 v il10 input low voltage -0.5 0.8 v v ih10 input high voltage 2.0 v5ref_sus + 0.5 v v il11 input low voltage -0.5 0.35vcc3_3 v v ih11 input high voltage 0.65vcc3_3 vcc3_3 + 0.3 v v il12 input low voltage -0.150 0.150 v v ih12 input high voltage 0.660 1.850 v v+ low to high input threshold 1.5 2.0 v note 1 v- high to low input threshold 1.0 1.5 v note 1 vhys difference between input thresholds: (v+current value) - (v-current value) 320 mv note 1 vthravg average of thresholds: ((v+current value) + (v-current value))/2 1.3 1.7 v note 1 vring ac voltage at recipient connector -1 6 v note 1 , 2 v di differential input sensitivity 0.2 v note 3 , 5 v cm differential common mode range 0.8 2.5 v note 4 , 5 v se single-ended receiver threshold 0.8 2.0 v note 5 v hssq hs squelch detection threshold 100 150 mv note 5 v hsdsc hs disconnect detection threshold 525 625 mv note 5 v hscm hs data signaling common mode voltage range -50 500 mv note 5 v hssq hs squelch detection threshold 100 150 mv note 5 v hsdsc hs disconnect detection threshold 525 625 mv note 5 v hscm hs data signaling common mode voltage range -50 500 mv note 5 table 710. dc input characteristics (sheet 2 of 2) symbol parameter min max unit notes notes: 1. applies to ultra dma modes greater than ultra dma mode 4. 2. this is an ac characteristic that represents transient values for these signals. 3. v di = | usbpx[p] - usbpx[n]. 4. includes v di range. 5. applies to high-speed usb 2.0. 6. sata vdiff,rx is measured at the sata connector on the receive side. 7. when probed at the receiver pin of the ich for data/strobe, the waveform may show a ?knee? due to package parasitics. simulation verifies that this ?knee? represents no risk, since a clean waveform is present at the ich ball input due to internal receiver termination.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 793 22?intel ? 6300ESB ich table 711. dc characteristic output signal association symbol associated signals v oh1 /v ol1 ide signals: pdd[15:0], sdd[15:0], pdiow#/pdstop, sdiow#/sdstop, pdior#/ pdwstb/prdmardy, sdior#/stwstb/srdmardy, pddack#, sddack#, pda[2:0], sda[2:0], pdcs[3,1]#, sdcs[3,1]# v oh2 /v ol2 cpu signals: a20m#, cpuslp#, ignne#, init#, intr, nmi, smi#, stpclk#, v oh4 /v ol4 pci-x signals: pxad[63:0], pxc/be[7:0]#, pxpcirst#, pxgnt[3]#/gpio [17], pxgnt[2]#/gpio [16], pxgnt[1:0]#, pxpar, pxdevsel#, pxperr#, pxplock#, pxstop#, pxtrdy#, pxirdy#, pxframe#, pxserr#,pxpclk[0:4], pxserr#, raserr#,pxrcomp, pxirq[3:0]/gpio[36:33 ], pxpar64, pxreq64#, pxack64#, pcixsbrst# pci signals: ad[31:0], c/be[3:0]#, gnt[3:0]#, par, devsel#, perr#, plock#, stop#, trdy#, irdy#, frame#, serr# (1) lpc/fwh: lad[3:0]/fwh[3:0], lframe# ac?97 signals: ac_rst#, ac_sdout, ac_sync siu signals: siu0_txd, siu1_txd, siu0_dtr#, siu1_dtr#, siu0_rts#, siu1_rts# gpio signals: gpio [43:40] v ol5 /v oh5 smbus signals: smbclk (1) , smbdata (1) system management signals: smlink[1:0] (1) v ol6 /v oh6 power management signals: pme# (1) , slp_s3#, slp_s4#, slp_s5#, sus_stat#, susclk gpio signals: gpio[57:56 (1) , 39:37, 31, 28:27, 25:23, 21:18]; interrupt signals: serirq, pirq[d:a]# (1) , pirq[h:e]#/gpio[5:2] (1) other signals: spkr, wdt_tout#/gpio[32], sataled# (1) v ol7 /v oh7 usb signals : usbp[3:0][p,n] in low and full speed modes v ol8 /v oh8 zpd/zpu hub interface signals : hi[11:0], hi_stbs, hi_stbf v ol9 /v oh9 sata signals: sata[1:0]tx[p,n] v hsoi v hsoh v hsol v chirpj v chirpk usb signals: usbp[3:0][p:n] in high speed modes 1. these signals are open drain.
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 794 order number: 300641-004us table 712. dc output characteristics symbol parameter min max unit i ol / i oh notes v ol1 output low voltage 0.51 v 6 ma v oh1 output high voltage vcc3_3 - 0.51 v -6 ma v ol2 output low voltage -0.15 .25(v_cpu_io ) v 1.5 ma v oh2 output high voltage 0.9(v_cpu_io) v -.5 ma note 1 v ol4 output low voltage 0.55 v 6 ma v oh4 output high voltage 0.9vcc3_3 v -0.5 ma note 1 v ol5 output low voltage 0.4 v 4 ma v oh5 output high voltage n/a v n/a note 1 v ol6 output low voltage 0.4 v 4 ma v oh6 output high voltage vcc3_3 - 0.5 v -2 ma note 1 v ol7 output low voltage 0.4 v 5 ma v oh7 output high voltage vcc3_3 - 0.5 v -2 ma v ol8 output low voltage 0.05 v 1 ma v oh8 output high voltage 0.750 .850 v -12 ma v ol9 output low voltage 400 mvp- p note 2 v oh9 output high voltage 600 mvp- p note 2 zpd pull down impedance 48 ohm zpu pull up impedance 46 ohm v hsoi hs idle level -10.0 10.0 mv v hsoh hs data signaling high 360 440 mv v hsol hs data signaling low -10.0 10.0 mv v chirpj chirp j level 700 1100 mv v chirpk chirp k level -900 -500 mv notes: 1. the cpupwrgd, serr#, pirq[a:h], sataled#, smbdata, smbclk, and smlink[1:0], raserr#, pxserr#, pme#, gpio [57:56] signals have an open drain driver, and the v oh spec does not apply. this signal must have external pull up resistor. 2. sata vdiff,tx is measured at the sata connector on the transmit side. table 713. other dc characteristics (sheet 1 of 2) symbol parameter min max unit notes v5ref intel ? 6300ESB ich core well reference voltage 4.75 v5ref + 0.5 v vcc3_3 i/o buffer voltage 3.135 3.465 v vccref reference voltage for pci-x 3.135 3.465 v notes: 1. includes clk14, clk48, hiclk, pciclk and pxpciclk.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 795 22?intel ? 6300ESB ich vcc1_5, vcchi, vccpll internal logic voltage 1.425 1.575 v hiref hub interface reference voltage 0.343 0.357 v hivswing hub interface voltage swing (input to hi_vswing pin) 0.784 0.816 v v5ref_sus suspend well reference voltage 4.75 5.25 v vccsus3_3 suspend well i/o buffer voltage 3.135 3.465 v vccsus1_5 suspend well logic voltage 1.425 1.575 v vccrtc battery voltage 2.0 3.6 v v it+ hysteresis input rising threshold 1.9 v applied to usbp[3:0][p,n] v it- hysteresis input falling threshold 1.3 v applied to usbp[3:0]p,n] v di differential input sensitivity 0.2 v |(usbpx+,usbpx- )| v cm differential common mode range 0.8 2.5 v includes v di v crs output signal crossover voltage 1.3 2.0 v v se single ended rcvr threshold 0.8 2.0 v i li1 ata input leakage current -200 200 a (0 v < v in < 5v) i li2 pci_3v hi-z state data line leakage -10 10 a (0 v < v in < 3.3v) i li3 pci_5v hi-z state data line leakage -70 70 a max v in = 2.7 v min v in = 0.5 v i li4 input leakage current - clock signals -100 +100 a note 1 i li5 pci-x hi-z state data line leakage -10 10 a (0 v < v in < 3.3v) c in input capacitance - hub interface input capacitance - all other 8 12 pf f c = 1 mhz c out output capacitance 12 pf f c = 1 mhz c i/o i/o capacitance 12 pf f c = 1 mhz typical value c l xtal1 6 pf c l xtal2 6 pf table 713. other dc characteristics (sheet 2 of 2) symbol parameter min max unit notes notes: 1. includes clk14, clk48, hiclk, pciclk and pxpciclk.
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 796 order number: 300641-004us 22.4 ac characteristics table 714. clock timings (sheet 1 of 3) sym parameter min max unit notes figure pci-x clock (pxpclko[0:4]) tcyc clk cycle time 15 30 ns 7 , 9 , 10 figure 39 thigh clk high time 6 ns figure 39 tlow clk low time 6 ns figure 39 clk slew rate 1.5 4 v/ns 8 , 10 spread spectrum requirements fmod modulation frequency 30 33 khz fspread frequency spread -1 0 % pci clock (pciclk) period 30 33.3 ns figure 44 high time 11 ns figure 44 low time 11 ns figure 44 rise time 4 ns figure 44 fall time 4 ns figure 44 oscillator clock (clk14) period 67 70 ns figure 44 high time 20 figure 44 low time 20 ns figure 44 usb clock (clk48) f clk48 operating frequency 48 mhz 1 frequency tolerance 500 ppm 2 high time 7 ns figure 44 low time 7 ns figure 44 rise time 1.2 ns figure 44 fall time 1.2 ns figure 44 smbus clock (smbclk) f smb operating frequency 10 16 khz t18 high time 4.0 50 us 3figure59 t19 low time 4.7 us figure 59 t20 rise time 1000 ns figure 59 t21 fall time 300 ns figure 59 ac?97 clock (bitclk) f ac97 operating frequency 12.288 mhz t26 output jitter 750 ps
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 797 22?intel ? 6300ESB ich t27 high time 32.56 48.84 ns figure 44 t28 low time 32.56 48.84 ns figure 44 t29 rise time 2.0 6.0 ns 4figure44 t30 fall time 2.0 6.0 ns 4figure44 hub interface clock (hiclk) f hi operating frequency 66 mhz t31 high time 6.0 ns figure 44 t32 low time 6.0 ns figure 44 t33 rise time 0.25 1.2 ns figure 44 t34 fall time 0.25 1.2 ns figure 44 t35 hiclk leads pciclk 1.0 4.5 ns 5 sata clock (sataclkp, sataclkn) t36 period 9.997 10.003 ns t37 rise time 175 700 ps t38 fall time 175 700 ps suspend clock (susclk) f susclk operating frequency 32 khz 6 t39 high time 10 us 6 t40a low time 10 us 6 uart clock (uart_clk) t8a operating frequency 14.745 6 48 mhz t9a frequency tolerance 2500 ppm t10a high time 7 ns t11a low time 7 ns t12a rise time 3 ns t13a fall time 3 ns table 714. clock timings (sheet 2 of 3) sym parameter min max unit notes figure
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 798 order number: 300641-004us notes: 1. clk48 is a 48 mhz clock that expects a 40/60% duty cycle. 2. clk48 is a pass-thru clock that is not altered by the intel ? 6300ESB ich. this frequency tolerance specification is required for usb 2.0 compliance and is affected by external elements such as the clock generator and the system board. 3. the maximum high time (t18 max) provide a simple ensured method for devices to detect bus idle conditions. 4. bitclk rise and fall times are measured from 10%vdd and 90%vdd. 5. this specification includes pin-to-pin skew from the clock generator as well as board skew. 6. susclk duty cycle can range from 30% minimum to 70% maximum. 7. for clock frequencies above 33 mhz, the clock frequency may not change beyond the spread-spectrum limits except while rst# is asserted. 8. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in figure 43 . 9. the minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 10.all pci-x devices must be capable of operating in conventional pci 33 mode and optionally are capable of conventional pci 66 mode. table 714. clock timings (sheet 3 of 3) sym parameter min max unit notes figure
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 799 22?intel ? 6300ESB ich table 715. pci-x interface timings symbol parameter min max units notes t val pxclko[4:0] to signal valid delay-bused signals 0.7 3.8 ns 1 , 2 , 3 , 10 , 11 t val (ptp) pxclko[4:0] to signal valid delay-point to point signals 0.7 3.8 ns 1 , 2 , 3 , 10 , 11 t on float to active delay 0 ns 1 , 7 , 10 , 11 t off active to float delay 7 ns 1 , 7 , 11 t su input setup time to pxclko[4:0]-bused signals 1.7 ns 3 , 4 , 8 t su (ptp) input setup time to pxclko[4:0]-point to point 1.7 ns 3 , 4 t h input hold time from pxclko[4:0] 0.5 ns 4 t rst reset active time after power stable 1 ms 5 t rst-clk reset active time after pxclko[4:0] stable 100 s 5 t rst-off reset active to output float delay 40 ns 5 , 6 t rrsu pxreq64# to pxpcirst# setup time 10 ns t rrh pxpcirst# to pxreq64# hold time 0 50 ns t rhfa pxpcirst# high to first configuration access 2 26 clocks t rhff pxpcirst# high to first pxframe# assertion 5 clocks t pvrh power valid to pxpcirst# high 100 ms t prsu pci-x initialization pattern to pxpcirst# setup time 10 clocks t prh pxpcirst# to pci-x initialization pattern hold time 0 50 ns 9 t rlcx delay from pxpcirst# low to pxclko[4:0] frequency change 0ns notes: 1. refer to figure 41 . for timing and measurement condition details, refer to the pci-x addendum to the pci local bus specification document. 2. minimum times are measured at the package pin (not a test point). 3. setup time for point-to-point signals applies to pxreq[3:0] and pxgnt[3:0] only. all other signals are bused. 4. see timing measurement conditions in figure 42 . 5. pxpcirst# is asserted and deasserted asynchronously with respect to pxclko[4:0]. 6. all output drivers must be floated when rstin# is active. 7. for purposes of active/float timing measurements, the hi-z or ?off? state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification 8. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 9. maximum value is also limited by delay to the first transaction (t rhfa ). the pci-x initialization pattern control signals after the rising edge of pxpcirst# must be deasserted no later than two clocks before the first frame# and must be floated no later than one clock before frame# is asserted. 10.a pci-x device is permitted to have the minimum values shown for t val , t val(ptp) , and t on only in pci-x mode. in conventional mode, the device must meet the requirements specified in pci local bus specification, revision 2.2, for the appropriate clock frequency. 11.device must meet this specification independent of how many outputs switch simultaneously.
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 800 order number: 300641-004us table 716. pci interface timing sym parameter min max units notes figure t40 ad[31:0] valid delay 2 11 ns min: 0 pf max: 50 pf figure 4 5 t41 ad[31:0] setup time to pciclk rising 7 ns figure 4 6 t42 ad[31:0] hold time from pciclk rising 0 ns figure 4 6 t43 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, devsel# valid delay from pciclk rising 211ns min: 0 pf max: 50 pf figure 4 5 t44 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, idsel, devsel# output enable delay from pciclk rising 2ns figure 4 9 t45 c/be[3:0]#, frame#, trdy#, irdy#, stop#, perr#, plock#, devsel#, gnt[a:b]# float delay from pciclk rising 228ns figure 4 7 t46 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, setup time to pciclk rising 7ns figure 4 6 t47 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, req[a:b]# hold time from pciclk rising 0ns figure 4 6 t48 pxpcirst# low pulse width 1 ms figure 4 8 t49 gnt[a:b}#, gnt[5:0]# valid delay from pciclk rising 2 12 ns t50 req[a:b]#, req[5:0]# setup timer to pciclk rising 12 ns
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 801 22?intel ? 6300ESB ich table 717. ide pio and multiword dma modetiming sym parameter min max unit s notes figure t60 pdior#/pdiow#/sdior#/sdiow# active from hiclk rising 220ns figure 50 figure 51 t61 pdior#/pdiow#/sdior#/sdiow# inactive from hiclk rising 220ns figure 50 figure 51 t62 pda[2:0]/sda[2:0] valid delay from hiclk rising 2 30 ns figure 50 t63 pdcs1#/sdcs1#, pdcs3#/sdcs3# active from hiclk rising 230ns figure 50 t64 pdcs1#/sdcs1#, pdcs3#/sdcs3# inactive from hiclk rising 230ns figure 50 t65 pddack#/sddack# active from hiclk rising 2 20 ns figure 51 t66 pddack#/sddack# inactive from hiclk rising 2 20 ns t67 pddreq/sddreq setup time to hiclk rising 7 ns figure 51 t68 pddreq/sddreq hold from hiclk rising 7 ns figure 51 t69 pdd[15:0]/sdd[15:0] valid delay from hiclk rising 2 30 ns figure 50 figure 51 t70 pdd[15:0]/sdd[15:0] setup time to hiclk rising 10 ns figure 50 figure 51 t71 pdd[15:0]/sdd[15:0] hold from hiclk rising 7 ns figure 50 figure 51 t72 piordy/siordy setup time to hiclk rising 7 ns 1figure50 t73 piordy/siordy hold from hiclk rising 7 ns 1figure50 t74 piordy/siordy inactive pulse width 48 ns figure 50 t75 pdior#/pdiow#/sdior#/sdiow# pulse width low 2 , 3 figure 50 figure 51 t76 pdior#/pdiow#/sdior#/sdiow# pulse width high 3 , 4 figure 50 figure 51 notes: 1. iordy is internally synchronized. this timing is to ensure recognition on the next clock. 2. piordy sample point from diox# assertion and pdiox# active pulse width is programmable from 2-5 pci clocks when the drive mode is mode 2 or greater. refer to the isp field in the ide timing register. 3. piordy sample point from diox# assertion, pdiox# active pulse width and pdiox# inactive pulse width cycle time is the compatible timing when the drive mode is mode 0/1. refer to the tim0/1 field in the ide timing register. 4. pdiox# inactive pulse width is programmable from 1-4 pci clocks when the drive mode is mode 2 or greater. refer to the rct field in the ide timing register.
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 802 order number: 300641-004us table 718. ultra ata timing (mode 0, mode 1, mode 2) (sheet 1 of 2) sym parameter (1) mode 0 (ns) mode 1 (ns) mode 2 (ns) measurin g location figure min max min max min max t80 sustained cycle time (t2cyctyp) 240 160 120 sender connector t81 cycle time (tcyc) 112 73 54 end recipient connector figure 5 3 t82 two cycle time (t2cyc) 230 153 115 sender connector figure 5 3 t83a data setup time (tds) 15 10 7 recipient connector figure 5 3 t83b recipient ic data setup time (from data valid until strobe edge) (see note 2 ) (tdsic) 14. 7 9.7 6.8 intel ? 6300ESB ich ball t84a data hold time (tdh) 5 5 5 recipient connector figure 5 3 t84b recipient ic data hold time (from strobe edge until data may become invalid) (see note 2 ) (tdhic) 4.8 4.8 4.8 intel ? 6300ESB ich ball t85a data valid setup time (tdvs) 70 48 31 sender connector figure 5 3 t85b sender ic data valid setup time (from data valid until strobe edge) (see note 2 ) (tdvsic) 72. 9 50.9 33.9 intel ? 6300ESB ich ball t86a data valid hold time (tdvh) 6.2 6.2 6.2 sender connector figure 5 3 t86b sender ic data valid hold time (from strobe edge until data may become invalid) (see note 2 ) (tdvhic) 99 9 intel ? 6300ESB ich ball t87 limited interlock time (tli) 0 150 0 150 0 150 see note 2 figure 5 5 t88 interlock time w/ minimum (tmli) 20 20 20 host connector figure 5 5 t89 envelope time (tenv) 20 70 20 70 20 70 host connector figure 5 2 t90 ready to pause time (trp) 160 125 100 recipient connector figure 5 4 t91 dmack setup/hold time (tack) 20 20 20 host connector figure 5 2 , figure 5 5 t92a crc word setup time at host (tcvs) 70 48 31 host connector notes: 1. the specification symbols in parentheses correspond to the at attachment - 6 with packet interface (ata/ atapi - 6) specification name. 2. see the at attachment - 6 with packet interface (ata/atapi - 6) specification for further details on measuring these timing parameters.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 803 22?intel ? 6300ESB ich t92b crc word valid hold time at sender (from dmack# negation until crc may become invalid) (see note 2) (tcvh) 6.2 6.2 6.2 host connector t93 strobe output released-to-driving to the first transition of critical timing (tzfs) 00 0 device connector figure 5 5 t94 data output released-to-driving until the first tunisian of critical timing (tdzfs) 70 48 31 sender connector figure 5 2 t95 unlimited interlock time (tui) 0 0 0 host connector figure 5 2 t96a maximum time allowed for output drivers to release (from asserted or negated) (taz) 10 10 10 see note 2 t96b minimum time for drivers to assert or negate (from released) (tzad) 00 0 device connector t97 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy#) (trfs) 75 70 60 sender connector figure 5 2 t98a maximum time before releasing iordy (tiordyz) 20 20 20 device connector t98b minimum time before driving iordy (see note 2) (tziordy) 00 0 device connector t99 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) (tss) 50 50 50 sender connector figure 5 4 table 718. ultra ata timing (mode 0, mode 1, mode 2) (sheet 2 of 2) sym parameter (1) mode 0 (ns) mode 1 (ns) mode 2 (ns) measurin g location figure min max min max min max notes: 1. the specification symbols in parentheses correspond to the at attachment - 6 with packet interface (ata/ atapi - 6) specification name. 2. see the at attachment - 6 with packet interface (ata/atapi - 6) specification for further details on measuring these timing parameters.
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 804 order number: 300641-004us table 719. ultra ata timing (mode 3, mode 4, mode 5) (sheet 1 of 2) sym parameter (1) mode 3 (ns) mode 4 (ns) mode 5 (ns) measuring location figure minmaxminmaxminmax t80 sustained cycle time (t2cyctyp) 90 60 40 sender connector t81 cycle time (tcyc) 39 25 16.8 end recipient connector figure 5 3 t82 two cycle time (t2cyc) 86 57 38 sender connector figure 5 3 t83 data setup time (tds) 7 5 4.0 recipient connector figure 5 3 t83b recipient ic data setup time (from data valid until strobe edge) (see note 2 ) (tdsic) 6.8 4.8 2.3 intel ? 6300ESB ich balls t84 data hold time (tdh) 5 5 4.6 recipient connector figure 5 3 t84b recipient ic data hold time (from strobe edge until data may become invalid) (see note 2 ) (tdhic) 4.8 4.8 2.8 intel ? 6300ESB ich balls t85 data valid setup time (tdvs) 20 6.7 4.8 sender connector figure 5 2 figure 5 3 t85b sender ic data valid setup time (from data valid until strobe edge) ( see note 2 ) (tdvsic) 22.6 9.5 6.0 intel ? 6300ESB ich balls t86 data valid hold time (tdvh) 6.2 6.2 4.8 sender connector figure 5 2 figure 5 3 t86b sender ic data valid hold time (from strobe edge until data may become invalid) (see note 2 ) (tdvhic) 9.0 9.0 6.0 intel ? 6300ESB ich balls t87 limited interlock time (tli) 0 100 0 100 0 75 see note 2 figure 5 5 t88 interlock time w/ minimum (tmli) 20 20 20 host connector figure 5 5 t89 envelope time (tenv) 20 55 20 55 20 50 host connector figure 5 3 t90 ready to pause time (trp) 100 100 85 recipient connector figure 5 4 notes: 1. the specification symbols in parentheses correspond to the at attachment - 6 with packet interface (ata/ atapi - 6) specification name. 2. see the at attachment - 6 with packet interface (ata/atapi - 6) specification for further details on measuring these timing parameters.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 805 22?intel ? 6300ESB ich t91 dmack setup/hold time (tack) 20 20 20 host connector figure 5 5 t92a crc word setup time at host (tcvs) 20 6.7 10 host connector t92b crc word hold time at sender crc word valid hold time at sender (from dmack# negation until crc may become invalid) (see note 2 ) (tcvh) 6.2 6.2 10.0 host connector t93 strobe output released-to- driving to the first transition of critical timing (tzfs) 0035 device connector figure 5 5 t94 data output released-to-driving until the first transition of critical timing (tdzfs) 20.0 6.7 25 sender connector figure 5 2 t95 unlimited interlock time (tui) 0 0 0 host connector figure 5 2 t96a maximum time allowed for output drivers to release (from asserted or negated) (taz) 10 10 10 see note 2 t96b drivers to assert or negate (from released) (tzad) 000 device connector t97 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy#) (trfs) 60 60 50 sender connector figure 5 2 t98a maximum time before releasing iordy (tiordyz) 20 20 20 device connector t98b minimum time before driving iordy (see note 2 ) (tziordy) 000 device connector t99 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) (tss) 50 50 50 sender connector figure 5 4 table 719. ultra ata timing (mode 3, mode 4, mode 5) (sheet 2 of 2) sym parameter (1) mode 3 (ns) mode 4 (ns) mode 5 (ns) measuring location figure minmaxminmaxminmax notes: 1. the specification symbols in parentheses correspond to the at attachment - 6 with packet interface (ata/ atapi - 6) specification name. 2. see the at attachment - 6 with packet interface (ata/atapi - 6) specification for further details on measuring these timing parameters.
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 806 order number: 300641-004us table 720. universal serial bus timing sy m parameter min max units notes fig full speed source (note 7) t10 0 usbpx+, usbpx- driver rise time 4 20 ns 1 , c l = 50 pf figure 56 t10 1 usbpx+, usbpx- driver fall time 4 20 ns 1 , c l = 50 pf figure 56 t10 2 source differential driver jitter to ne x t tra n sit i o n for paired transitions -3.5 -4 3.5 4 ns ns 2 , 3figure57 t10 3 source se0 interval of eop 160 175 ns 4figure58 t10 4 source jitter for differential transition to se0 tra n sit io n -2 5 ns 5 t10 5 receiver data jitter tolerance to ne x t tra n sit i o n for paired transitions -18.5 -9 18.5 9 ns ns 3figure57 t10 6 eop width: must accept as eop 82 ns 4figure58 t10 7 width of se0 interval during differential transition 14 ns low speed source (note 8) t10 8 usbpx+, usbpx- driver rise time 75 300 ns 1 , 6 c l = 50 pf c l = 350 pf figure 56 t10 9 usbpx+, usbpx- driver fall time 75 300 ns 1 , 6 c l = 50 pf c l = 350 pf figure 56 t11 0 source differential driver jitter to ne x t tra n sit i o n for paired transitions -25 -14 25 14 ns ns 2 , 3figure57 t11 1 source se0 interval of eop 1.25 1.50 s 4figure58 t11 2 source jitter for differential transition to se0 tra n sit io n -40 100 ns 5 t11 3 receiver data jitter tolerance to ne x t tra n sit i o n for paired transitions -152 -200 152 200 ns ns 3figure57 notes: 1. driver output resistance under steady state drive is spec?d at 28 ohms at minimum and 43 ohms at maximum. 2. timing difference between the differential data signals. 3. measured at crossover point of differential data signals. 4. measured at 50% swing point of data signals. 5. measured from last crossover point to 50% swing point of data line at leading edge of eop. 6. measured from 10% to 90% of the data signal. 7. full speed data rate has minimum of 11.97 mbps and maximum of 12.03 mbps. 8. low speed data rate has a minimum of 1.48 mbps and a maximum of 1.52 mbps. 9. refer to the latest revision of the universal serial bus specification for high speed source timings
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 807 22?intel ? 6300ESB ich t11 4 eop width: must accept as eop 670 ns 4figure58 t11 5 width of se0 interval during differential transition 210 ns table 720. universal serial bus timing sy m parameter min max units notes fig full speed source (note 7) notes: 1. driver output resistance under steady state drive is spec?d at 28 ohms at minimum and 43 ohms at maximum. 2. timing difference between the differential data signals. 3. measured at crossover point of differential data signals. 4. measured at 50% swing point of data signals. 5. measured from last crossover point to 50% swing point of data line at leading edge of eop. 6. measured from 10% to 90% of the data signal. 7. full speed data rate has minimum of 11.97 mbps and maximum of 12.03 mbps. 8. low speed data rate has a minimum of 1.48 mbps and a maximum of 1.52 mbps. 9. refer to the latest revision of the universal serial bus specification for high speed source timings
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 808 order number: 300641-004us table 721. sata interface timings sym parameter min max units notes figure operating data period 666.43 670.1 2 ps rise time 0.2 0.41 ui 1 fall time 0.2 0.41 ui 2 tx differential skew 20 ps comreset 310.4 329.6 ns 3 comwake transmit spacing 103.5 109.9 ns 3 oob operating data period 646.67 686.6 7 ns 4 notes: 1. 20% - 80% at transmitter 2. 80% - 20% at transmitter 3. as measured from 100 mv differential crosspoints of last and first edges of burst. 4. operating data period during out-of-band burst transmissions. table 722. smbus timing sy m parameter min max units note s fig t13 0 bus tree time between stop and start condition 4.7 s figure 59 t13 1 hold time after (repeated) start condition. after this period, the first clock is generated. 4.0 s figure 59 t13 2 repeated start condition setup time 4.7 s figure 59 t13 3 stop condition setup time 4.0 s figure 59 t13 4 data hold time 0 ns 4figure59 t13 5 data setup time 250 ns figure 59 t13 6 device time out 25 35 ms 1 t13 7 cumulative clock low extend time (slave device) 25 ms 2figure60 t13 8 cumulative clock low extend time (master device) 10 ms 3figure60 notes: 1. a device will timeout when any clock low exceeds this value. 2. t137 is the cumulative time a slave device is allowe d to extend the clock cycles in one message from the initial start to stop. if a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. 4. t134 has a minimum timing for i 2 c of 0 ns, while the minimum timing for smbus is 300 ns.
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 809 22?intel ? 6300ESB ich table 723. ac?97 timing sym parameter min max units note s fig t setup acsdin[2:0] setup to falling edge of bitclk 10 ns figure 65 t hold acsdin[2:0] hold from falling edge of bitclk 10 ns figure 65 t co acsync, acsdout valid delay from rising edge of bitclk 15 ns figure 65 table 724. lpc timing sy m parameter min max units notes fig t15 0 lad[3:0] valid delay from pciclk rising 2 11 ns figure 45 t15 1 lad[3:0] output enable delay from pciclk rising 2 ns figure 49 t15 2 lad[3:0] float delay from pciclk rising 28 ns figure 47 t15 3 lad[3:0] setup time to pciclk rising 7 ns figure 46 t15 4 lad[3:0] hold time from pciclk rising 0 ns figure 46 t15 5 ldrq[1:0]# setup time to pciclk rising 12 ns figure 46 t15 6 ldrq[1:0]# hold time from pciclk rising 0 ns figure 46 t15 7 lframe# valid delay from pciclk rising 2 12 ns figure 45 table 725. miscellaneous timings sy m parameter min max units notes fig t16 0 serirq setup time to pciclk rising 7 ns figure 46 t16 1 serirq hold time from pciclk rising 0 ns figure 46 t16 2 ri# pulse width 2 rtcclk figure 48 t16 3 spkr valid delay from clk14 rising 200 ns figure 45 t16 4 serr# active to nmi active 200 ns t16 5 ignne# inactive from ferr# inactive 230 ns
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 810 order number: 300641-004us table 726. uart timings sym parameter min max units notes fig t150a siu0_txd, siu1_txd valid delay from uart_clk rising 2 13 ns t151a siu0_dtr#, siu0_rts#, siu1_dtr#, and siu1_rts# valid delay from pciclk rising 213 ns t152a siu0_rxd, siu1_rxd setup time to uart_clk rising 7 ns t153a siu0_rxd, siu1_rxd hold time to uart_clk rising 0 ns t154a siu0_cts#, siu0_dsr#, siu0_dcd#, siu0_ri#, siu1_cts#, siu1_dsr#, siu1_dcd#, and siu1_ri# high time 100 ns t155a siu0_cts#, siu0_dsr#, siu0_dcd#, siu0_ri#, siu1_cts#, siu1_dsr#, siu1_dcd#, and siu1_ri# low time 100 ns
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 811 22?intel ? 6300ESB ich table 727. power sequencing and reset signal timings sym parameter min max units notes fig t170 vccrtc active to rtcrst# inactive 5 - ms figure 61 t171 v5refsus active to vccsus3_3, vccsus1_5 active 0 - ms 1 , 2figure61 t172 vccrtc supply active to vccsus supplies active 0 - ms 3figure61 t173 vccsus supplies active to rsmrst# inactive 10 - ms figure 61 figure 62 t174 v5ref active to vcc3_3, vcc1_5, vcchi active 0 - ms 1 , 2figure61 t175 vccsus supplies active to vcc3_3, vcc1_5, vcchi supplies active 0-ms 3figure61 t176 vcc3_3, vcc1_5, vcchi supplies active to pwrok. 99 - ms figure 61 figure 62 figure 64 t177 pwrok active to sus_stat# inactive 32 38 rtcclk 4 figure 62 figure 64 t178 sus_stat# inactive to pxpcirst# inactive 1 3 rtcclk figure 62 figure 64 t179 ac_rst# active low pulse width 1 us t180 ac_rst# inactive to bit_clk startup delay 162.8 ns notes: 1. the v5ref supply must power up before or simultaneous with its associated 3.3 v supply, and must power down simultaneous with or after the 3.3 v supply. see the intel ? 6300ESB ich design guide for details. 2. the associated 3.3 v and 1.5 v supplies must power up or down simultaneously. 3. the vccsus supplies must never be active while the vccrtc supply is inactive. 4. sysreset# is not checked for pwrok transitions (t177).
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 812 order number: 300641-004us table 728. power management timings sym parameter min max units notes fig t181 vccsus active to slp_s5#, sus_stat# and pxpcirst# active 50 ns figure 62 t182 t183 rsmrst# inactive to susclk running, slp_s5# inactive 110 ms 6figure62 t183a slps5# inactive to slp_s4# inactive 1 2 rtcclk figure 62 t183b slps4# inactive to slp_s3# inactive 1 2 rtcclk figure 62 t184 50 ns figure 62 figure 64 t187 stpclk# active to stop grant cycle n/a n/a 2figure63 t188 stop grant cycle to cpuslp# active 60 63 pciclk 3 figure 63 figure 64 t189 s1 wake event to cpuslp# inactive 1 25 pciclk 4figure63 t190 cpuslp# inactive to stpclk# inactive 3.87 245 s figure 63 t192 cpuslp# active to sus_stat# active 2 4 rtcclk 1figure64 t193 sus_stat# active to pxpcirst# active 9 21 rtcclk 1 t194 pxpcirst# active to slp_s3# active 1 2 rtcclk 1figure64 t194a slp_s3# active to slp_s4# active 1 2 rtcclk 1figure64 t195 slp_s4# active to slp_s5# active 1 2 rtcclk 1 , 5figure64 t196 slp_s3# active to pwrok inactive 0 ms 4figure64 t197 pwrok inactive to vcc supplies inactive 20 ns figure 64 t198 wake event to slp_s5# inactive 1 10 rtcclk 1 t198a wake event to slp_s4# inactive(s4 wake) 1 10 rtcclk 1 t198b s3 wake event to slp_s3# inactive(s3 wake) 0 2 rtcclk 1 t198d slp_s5# inactive to slp_s4# inactive 1 2 rtcclk 1figure64 t198e slp_s4# inactive to slp_s3# inactive 1 2 rtcclk 1figure64 t220 thrmtrip# active to slp_s3#, slp_s4#, slp_s5# active 2 pci clk notes: 1. these transitions are clocked off the internal rtc. 1 rtc clock is approximately 32 s. 2. the intel ? 6300ESB ich stpclk# assertion will trigger the processor to send a stop grant acknowledge cycle. the timing for this cycle getting to the intel ? 6300ESB ich is dependant on the processor and the memory controller. 3. these transitions are clocked off the 33 mhz pciclk. 1 pciclk is approximately 30ns. 4. the intel ? 6300ESB ich has no maximum timing requirement for this transition. it is up to the system designer to determine if the slp_s3#, slp_s4# and slp_s5# signals are used to control the power planes. 5. if the transition to s5 is due to power button override, slp_s3#, slp_s4# and slp_s5# are asserted together similar to timing t194 (pxpcirst# active to slp_s3# active). 6. if there is no rtc battery in the system, so vccrtc and the vccsus supplies come up together, the delay from rtcrst# and rsmrst# inactive to susclk toggling may be as much as 2.5 s. 7. this value is programmable in multiples of 1024 pci clks. maximum is 8192 pci clks (245.6 s).).
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 813 22?intel ? 6300ESB ich 22.5 timing diagrams and test conditions 22.5.1 pci-x figure 39. pci-x 3.3v clock figure 40. clock uncertainty (pxpclk[0:4]) table 729. clock uncertainty parameters symbol parameter units vtest-clk 0.4vcc v ts ke w 0 . 4 ( m a x) n s 0.6 vcc 0.2 vcc 0.5 vcc 0.4 vcc 0.3 vcc t_cyc t_high t_low 0.4 vcc, p-to-p (minimum) 3.3 volt clock
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 814 order number: 300641-004us figure 41. pci-x output timing figure 42. pci-x input timing clk output delay output delay tri-state output v_test t_val v_th v_tl v_tfall v_trise t_val t_on t_off clk input v_th v_tl v_test inputs valid v_test v_max t_su t_h v_test v_th v_tl
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 815 22?intel ? 6300ESB ich 22.5.2 system clocks and general timing table 730. pci-x measurement condition parameters symbol value units notes vth 0.6 vcc v 1 vtl 0.25 vcc v 1 vtest 0.4 vcc v vrise 0.285 vcc v 2 vtfall 0.615 vcc v 2 vmax 0.4 vcc v 1 input signal slew rate 1.5 v/ns 3 notes: 1. the test for the 3.3v environment is done with 0.1*v cc of overdrive. v max specifies the maximum peak-to-peak waveform allowed for measuring input timing. production testing is permitted to use different voltage values but must correlate results back to these parameters. 2. v trise and v tfall are reference voltages for timing measurements only. 3. input signal slew rate in pci-x mode is measured between v il and v ih . figure 43. pci-x rst# timing for switching to pci-x mode pull-ups figure 44. clock timing t_rlcx t_rst_clk(ref) t_rhff(ref) t_prh t_prsu t_rst(ref) pci_clk rst# frame# irdy# trdy# stop# devsel# 2.0v 0.8v period high time low time fall time rise time
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 816 order number: 300641-004us figure 45. valid delay from rising clock edge figure 46. setup and hold times figure 47. float delay figure 48. pulse width clock 1.5v valid delay vt output clock vt input hold time setup time vt 1.5v clock vt output float delay vt pulse width vt
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 817 22?intel ? 6300ESB ich 22.5.3 ide and ultra ata timing figure 49. output enable delay figure 50. ide pio mode clock output output enable delay vt 1.5v b3925-01 hiclk dio x dd[15:0] read dd[15:0] write t60 t61 t76 t71 t70 iordy da[2:0], cs1# t75 write t69 t69 t74 read t64 t62, t63 t73 t72 sample
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 818 order number: 300641-004us figure 51. ide multiword dma figure 52. ultra ata mode (drive initiating a burst read) hiclk idedma.v s d t67 ddreq[1:0] ddack[1:0] t65 diox# dd[15:0] read dd[15:0] write t60 t61 t75 t76 t70 t71 t69 t69 read data write data write data read data t68 dmarq (drive) t91 t89 t89 dmack# (host) stop (host) dmardy# (host) strobe (drive) dd[15:0] da[2:0], cs[1:0] t96 t98 t94 t95 t85 t86 t97 t99b
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 819 22?intel ? 6300ESB ich figure 53. ultra ata mode (sustained burst) figure 54. ultra ata mode (pausing a dma burst) strobe @ sender t81 data @ sender t86 t85 t86 t85 t81 t82 t86 strobe @ receiver data @ receiver t84 t83 t84 t83 t84 t99e t99e t99e t99d t99d t99g t99g t99g t99f t99f t90 strobe data stop (host) dmardy# t99
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 820 order number: 300641-004us 22.5.4 usb figure 55. ultra ata mode (terminating a dma burst) figure 56. usb rise and fall times t88 stop (host) strobe (host) dmardy# (drive) data (host) dmack# (host) t91 t87 dmarq (drive) crc t99c t87 t99a t91 t92 t93 differential data lines 90% 10% 10% 90% tr tf rise time fall time c l c l low speed: 75 ns at c l = 50 pf, 300 ns at c l = 350 pf full speed: 4 to 20 ns at c l = 50 pf high speed: 0.8 to 1.2 ns at c l = 10 pf
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 821 22?intel ? 6300ESB ich 22.5.5 smbus figure 57. usb jitter figure 58. usb eop width figure 59. smbus transaction paired transitions consecutive transitions crossover points t period differential data lines jitter differential data lines eop width data crossover level tperiod t130 smbclk smbdata t131 t19 t134 t20 t21 t135 t132 t18 t13 3
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 822 order number: 300641-004us 22.5.6 power and reset figure 60. smbus timeout figure 61. power sequencing and reset signal timings start stop t137 clk ack clk ack t138 t138 smbclk smbdata vccrtc rtcrst# v5refsus vccsus3_3, vccsus1_5 rsmrst# v5ref vcc3_3, vcc1_5, vcchi pwrok t170 t172 t171 t173 t174 t175 t176
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 823 22?intel ? 6300ESB ich figure 62. g3 (mechanical off) to s0 timings vccsus susclk slp_s4# vcc pwrok sus_stat# pxpcirst# stpclk#, cpuslp# hub interface "cpu reset complete" message rsmrst# g3 s5 s0 s0 state g3 - s5 system state s4 slp_s3# slp_s5# running t181 t181 t173 t182 t183 t183b t183a t176 t177 t178 t184 figure 63. s0 to s1 to s0 timing t187 t188 t189 t190 ich2_s0_s1d_timing.vsd s0 s0 s1 s1 s1 s0 s0 state stpclk# pci stop grant cycle cpuslp# wake event
intel ? 6300ESB ich?22 intel ? 6300ESB i/o controller hub ds november 2007 824 order number: 300641-004us 22.5.7 ac?97 and miscellaneous figure 64. s0 to s5 to s0 timings figure 65. ac?97 data input and output timings stpclk# stop grant cycle cpuslp# sus_stat# pxpcirst# slp_s3# slp_s5# wake event pwrok, vrmpwrgd vcc s0 s0 s3 s3 s5 s0 t188 t192 t193 t194 t196 t197 t176 t177 t178 t184 t187 slp_s4# t194a t195 t198d t198e s4 s4 s3 s3/s4/s5 s0 v oh v ol ac_sdout ac_sdin[2:0] ac_sync ac_bit_clk v i h v i l tco t hold t setup
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 825 23?intel ? 6300ESB ich testability 23 23.1 test mode description the intel ? 6300ESB ich supports two types of test modes, a tri-state test mode and a xor chain test mode. driving rtcrst# low for a specific number of pci clocks while pwrok is high will activate a particular test mode as described in table 731 . note: rtcrst# can be driven low any time after pxpcirst# is inactive. . figure 66 illustrates entry into a test mode. a particular test mode is entered upon the rising edge of the rtcrst# after being asserted for a specific number of pci clocks while pwrok is active. to change test modes, the same sequence should be followed again. to restore the intel ? 6300ESB ich to normal operation, execute the sequence with rtcrst# being asserted so that no test mode is selected as specified in table 731 . table 731. test mode selection number of pci clocks rtcrst# driven low after pwrok active number of pci clocks after rtcrst# driven high test mode <4 n/a no test mode selected 43xor chain 1 53xor chain 2 63xor chain 3 73xor chain 4 8 3 all ?z? 9 - 13 n/a reserved. do not attempt 14 3 long xor 15 - 42 n/a reserved. do not attempt 43 - 51 n/a no test mode selected 52 3 xor chain 6 53 3 xor chain 4 bandgap 59 3 xor chain 5 60 3 xor chain 7 >60 n/a no test mode selected
intel ? 6300ESB ich?23 intel ? 6300ESB i/o controller hub ds november 2007 826 order number: 300641-004us 23.2 tri-state mode when in the tri-state mode, all outputs and bi-directional pin are tri-stated, including the xor chain outputs. 23.3 xor chain mode in the intel ? 6300ESB ich, provisions for automated test equipment (ate) board level testing are implemented with xor chains. the intel ? 6300ESB ich signals are grouped into seven independent xor chains which are enabled individually. when an xor chain is enabled, all output and bi-directional buffers within that chain are tri- stated, except for the xor chain output. every signal in the enabled xor chain (except for the xor chain?s output) functions as an input. all output and bi-directional buffers for pins not in the selected xor chain are tri-stated. figure 67 is a schematic example of xor chain circuitry. 23.3.1 xor chain testability algorithm example xor chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to v cc or gnd). an example algorithm to do this is shown in table 732 . figure 66. test mode entry (xor chain example) number of pci clocks rtcrst# driven low after pwrok active number of pci clocks after rtcrst# driven high test mode entered all output signals tri-stated xor chain output enabled rsmrst# pwrok rtsrst# other signal outputs figure 67. example xor chain circuitry input pin 2 vcc input pin 1 input pin 3 input pin 4 input pin 5 input pin 6 xor chain output
testability intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 827 in this example, vector 1 applies all ?0s? to the chain inputs. the outputs being non-inverting, will consistently produce a ?1? at the xor output on a good board. one short to vcc (or open floating to vcc) will result in a ?0? at the chain output, signaling a defect. likewise, applying vector 7 (all ?1s?) to the chain inputs (given that there are an even number of input signals in the chain), will consistently produce a ?1? at the xor chain output on a good board. one short to vss (or open floating to vss) will result in a ?0? at the chain output, signaling a defect. it is important to note that the number of inputs pulled to ?1? will affect the expected chain output value. if the number of chain inputs pulled to ?1? is even, then expect ?1? at the output. if the number of chain inputs pulled to ?1? is odd, expect ?0? at the output. continuing with the example in ta b le 7 32 , as the input pins are driven to ?1? across the chain in sequence, the xor output will toggle between ?0? and ?1.? any break in the toggling sequence (e.g., ?1011?) w ill identify the location of the short or open. table 732. xor test pattern example vector input pin 1 input pin 2 input pin 3 input pin 4 input pin 5 input pin 6 xor output 1 000000 1 2 100000 0 3 110000 1 4 111000 0 5 111100 1 6 111110 0 7 111111 1 table 733. xor chain #1 (rtcrst# asserted for 4 pci clocks while pwrok active) (sheet 1 of 2) pin name ball # plock# j6 c/be[3]# h5 pciclk j5 gpio[33] / pxirq[0]# g1 gpio[34] / pxirq[1]# h1 gpio[35] / pxirq[2]# h2 gpio[36] / pxirq[3]# j3 pxreq[1]# l6 gpio[0] / pxreq[2]# j1 pxgnt0# k1 pxirdy# r4 pxframe# r6 pxstop# t2 pxtrdy# t5 pxserr# u1 pxc/be[1]# u2 pxpar u4 pxperr# u6 pxc/be[0]# aa1 raserr# ae1 pxreq64# ae5 pxack64# af4 output irq[14] ac23 table 733. xor chain #1 (rtcrst# asserted for 4 pci clocks while pwrok active) (sheet 2 of 2) pin name ball #
testability intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 828 table 734. xor chain #2 (rtcrst# asserted for 5 pci clocks while pwrok active) (sheet 1 of 3) pin name ball # pdd[6] ah24 pdd[4] aj25 pdd[7] ac20 pdd[11] ah25 pdd[5] ad21 pdd[8] af23 pdd[9] ab20 pdd[13] aj26 pdd[2] ah26 pdd[3] ad22 pdd[10] ac22 pddreq af24 pdd[12] ae23 pdd[14] ae24 pdd[1] ag25 pdd[15] ah27 pdd[0] af25 pdior# (/pdwstb / prdmardy#) ab21 piordy (/pdrstb / pwdmardy#) af26 pddack# ab22 pdiow# (/pdstop) ab23 irq[14] ac23 pda[1] ag27 pda[0] ag28 pdcs1# af27 pda[2] aa23 pdcs3# ad25 req[2]# b11 req[3]# d12 gnt[3]# g13 gnt[2]# c11 gpio[2] / pirq[e]# b10 gpio[3] / pirq[f]# a10 pirq[c]# a9 pirq[a]# e12 gpio[5] / pirq[h]# a8 pirq[d]# b8 pirq[b]# a6 gpio[4] / pirq[g]# d10 req[1]# g12 gnt[1]# d9 ad[18] b7 req[0]# d8 ad[28] h12 ad[15] c7 gnt[0]# e10 ad[22] b6 ad[30] g11 ad[20] a5 ad[16] a4 ad[4] f10 ad[24] e8 ad[0] h11 stop# b5 ad[11] b4 ad[26] e7 ad[6] d6 trdy# f9 frame# g10 ad[7] b3 ad[9] d5 ad[2] c3 par g9 ad[5] d4 ad[13] f6 ad[1] g8 serr# e4 c/be[0]# c2 table 734. xor chain #2 (rtcrst# asserted for 5 pci clocks while pwrok active) (sheet 2 of 3) pin name ball #
testability intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 829 c/be[1]# g7 ad[8] h8 ad[3] f5 irdy# e3 perr# d2 ad[14] d1 ad[12] g6 ad[10] e2 ad[23] h7 c/be[2]# f4 devsel# g5 ad[17] e1 ad[19] f2 ad[21] k8 ad[25] k7 ad[27] f1 ad[29] h4 ad[31] g2 output ferr# aa29 table 735. xor chain #3 (rtcrst# asserted for 6 pci clocks while pwrok active) (sheet 1 of 4) pin name ball # irq[15] v23 vrmpwrgd y26 a20gate ab29 rcin# v26 thrmtrip# aa28 ferr# aa29 a20m# w27 intr y28 nmi y29 ignne# u24 init# w28 table 734. xor chain #2 (rtcrst# asserted for 5 pci clocks while pwrok active) (sheet 3 of 3) pin name ball # stpclk# w29 smi# v29 cpuslp# v28 hl6 t26 hl5 u28 hl7 r24 hl4 u29 hlcomp t27 hi_stb/hi_stbs t28 hi_stb#/hi_stbf t29 hl3 r28 hl2 r29 hl1 p28 hl0 p29 hl10 n28 hl8 n29 hl9 n25 hl11 m28 nc m29 nc l29 nc l28 nc m25 nc k29 clk14 l26 gpio[32] / wdt _tout# m24 spkr k27 sataled# j28 gpio[40] h29 gpio[18] j27 gpio[19] l24 gpio[20] h28 gpio[21] k25 gpio[23] l22 gpio[42] g29 gpio[38] f29 gpio[43] k24 gpio[41] h26 nc g28 table 735. xor chain #3 (rtcrst# asserted for 6 pci clocks while pwrok active) (sheet 2 of 4) pin name ball #
testability intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 830 nc j23 nc h25 nc f28 nc g27 nc f27 nc h24 nc g25 ac_bit_clk g19 ac_sync f20 ac_sdout e20 nc g18 gpio[6] c21 gpio[7] b22 nc a22 nc b21 nc a21 nc d19 gpio[39] e19 gpio[37] d20 nc b20 serirq g17 siu1_rxd d18 siu1_txd c19 siu1_cts# a20 siu1_dsr# b19 siu1_dcd# a19 siu1_ri# d17 siu1_dtr# b18 siu1_rts# g16 uart_clk a18 siu0_rxd b17 siu0_txd a17 siu0_cts# d16 siu0_dsr# e17 siu0_dcd# b16 siu0_ri# a16 siu0_dtr# e15 siu0_rts# f16 lad[0] c15 table 735. xor chain #3 (rtcrst# asserted for 6 pci clocks while pwrok active) (sheet 3 of 4) pin name ball # lad[1] b15 ldrq[0]# f14 lad[2] a15 lad[3] a14 ldrq[1]# g14 lframe# b14 thrm# d14 nc b13 nc a13 nc f13 nc b12 nc a11 nc e13 output irq[14] ac23 table 735. xor chain #3 (rtcrst# asserted for 6 pci clocks while pwrok active) (sheet 4 of 4) pin name ball #
testability intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 831 table 736. xor chain #4 (rtcrst# asserted for 7 pci clocks while pwrok active) (sheet 1 of 2) pin name ball # pxpcirst# ah8 gpio[25] ah9 gpio[8] ae12 gpio[12] af11 nc ad13 gpio[27] ag10 gpio[13] ac14 pme# aj8 ri# ah10 gpio[28] aj9 slp_s4# ad14 pwrbtn# aj10 sysreset# ah11 slp_s5# aj11 smlink[1] ah12 gpio[24] ae14 susclk aj12 sus_stat# ad15 smlink[0] ah13 slp_s3# ag14 smbdata aj13 smbclk ah14 gpio[11] / smbalert# af15 nc aj14 nc aj15 oc[0]# f24 oc[2]# g23 oc[1]# f23 oc[3]# e24 ac_sdin0 f22 ac_rst# e23 ac_sdin2 e22 ac_sdin1 e21 gpio[56] c22 gpio[57] d22 output ferr# aa29 table 737. xor chain #5 (rtcrst# asserted for 59 pci clocks while pwrok active) (sheet 1 of 4) pin name ball # pxpclko[0] j2 pxpclko[1] l8 pxpclko[2] k6 pxpclko[3] k4 pxpclko[4] l5 pxad[31] k2 pxad[29] m7 pxad[28] l3 pxreq[0]# l2 pxad[30] m5 pxad[27] l1 pxad[26] m2 pxad[25] m1 pxc/be[3]# n6 pxad[24] n4 pxad[23] n3 pxad[20] n2 pxad[22] n1 pxad[21] p7 pxad[19] p5 pxad[18] p2 pxad[17] p1 pxad[16] r1 pxc/be[2]# r2 pxplock# t1 pxdevsel# t3 table 736. xor chain #4 (rtcrst# asserted for 7 pci clocks while pwrok active) (sheet 2 of 2) pin name ball #
testability intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 832 pxad[15] t7 pxad[12] v1 pxad[11] v2 pxad[13] v4 pxad[8] w1 pxad[9] w2 pxad[14] y1 pxm66en w4 pxad[6] y2 pxad[2] v7 pxad[4] aa2 pxad[3] y4 pxad[47] ab1 pxad[10] aa4 pxad[45] ab2 pxad[1] w7 pxad[43] y6 pxad[46] ac1 pxad[42] ab3 pxad[5] w8 gpio[16] / pxgnt[2]# ac2 gpio[17] / pxgnt[3]# y7 pxad[41] ad1 pxad[7] aa6 pxad[40] ad2 gpio[1] / pxreq[3]# y8 pxgnt1# ab5 pxpclki ac4 pxpciclk ac5 pcixsbrst# aa7 pxad[44] ab7 pxad[35] ae2 pxad[38] ad4 pxad[32] af1 pxad[34] ae3 table 737. xor chain #5 (rtcrst# asserted for 59 pci clocks while pwrok active) (sheet 2 of 4) pin name ball # pxad[39] ac6 pxad[0] af2 pxad[54] ab9 pxad[33] ae4 pxad[37] ad6 pxc/be[5]# ag2 pxad[36] ad7 pxad[63] ah3 pxpar64 ad8 pxad[50] ac10 pxc/be[4]# ae7 pxc/be[7]# af6 pxad[60] ag5 pxad[62] ah4 pxad[59] ah5 pxad[48] ad10 pxc/be[6]# af7 pxad[51] ae9 pxad[61] aj4 pxad[57] ah6 pxad[58] aj5 pxad[56] aj6 pxad[53] af9 pxad[49] ae10 pxad[55] ah7 pxad[52] aj7 sdd[7] af28 sdd[9] ae26 sdd[5] af29 sdd[8] y23 sdd[3] ad26 sdd[6] w22 sdd[10] ab24 sdd[12] ae28 sdd[11] ac26 table 737. xor chain #5 (rtcrst# asserted for 59 pci clocks while pwrok active) (sheet 3 of 4) pin name ball #
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 833 23?intel ? 6300ESB ich sdd[1] ae29 sdd[4] aa24 sdd[13] ab25 sddreq ad28 sdd[14] ad27 sddack# y24 siordy / (sdrstb/ swdmardy#) w24 sda[1] ad29 sdd[15] ac28 sdd[2] ab27 sda[2] ac29 sdiow# / (sdstop) y25 sdd[0] aa26 sdcs1# ab28 sdior# / (sdwstb/ prdmardy#) w25 sdcs3# aa27 sda[0] v24 output irq[15] v23 table 737. xor chain #5 (rtcrst# asserted for 59 pci clocks while pwrok active) (sheet 4 of 4) pin name ball #
23? intel ? 6300ESB ich intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 834 table 738. xor chain #6 (rtcrst# asserted for 52 pci clocks while pwrok active) pin name ball # intruder# ag23 rtcx1 ae21 output irq[15] v23 table 739. xor chain #7 (rtcrst# asserted for 60 pci clocks while pwrok active) pin name ball # sataclkn aj17 sataclkp ah17 sata[0]rxn aj19 sata[0]rxp ah19 sata[0]txn ag18 sata[0]txp af18 sata[1]rxn aj21 sata[1]rxp ah21 sata[1]txn ag20 sata[1]txp af20 satarbiasn aj23 satarbiasp ah23 output ldrq[1]# g14
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 835 ?intel ? 6300ESB ich index gp_lvl 432, 433 6 channel capability 575, 602 64-bit addressing capability 507 a a20gate pass-through enable (a20passen) 471 ac ?97 cold reset# 574, 601 ac ?97 interrupt routing 590 ac?97 warm reset 574, 601 ac97_en 404 ac97_sts 403 aclink shut off 573, 600 ad3 576, 603 address 539 address increment/decrement select 352 address of descriptor table (addr) 459, 769 adlib_act_sts 412 adlib_lpc_en 337 adlib_trp_en 414 af alarm flag 380 afterg3_en 387 aie alarm interrupt enable 378 alt_a20_gate 382 altacc_en alternate access mode enable 328 apic data 370, 641 apic id 371, 643 apic index 369, 641 apic_en 328 apm_sts 409 apmc_en 406 asynchronous schedule enable 509 asynchronous schedule status 512 audio_act_sts 412 audio_trp_en 414 autoinitialize enable 353 automatic end of interrupt (aeoi) 364 automatically append crc (aac) 544 aux_current 493 b bar number 496 base address 441, 442, 443, 556, 557, 587, 588, 744, 745, 746 base and current address 348 base and current count 349 base class code 441, 743 binary/bcd countdown select 356 bios_en 407 bios_rls bios release 406 bios_sts 409 bioswr_sts 419 bist fis failed 764
intel ? 6300ESB ich? intel ? 6300ESB i/o controller hub ds november 2007 836 order number: 300641-004us bist fis parameters 765 bist fis successful 764 bist fis transmit data 1 765 bist fis transmit data 2 766 bit 1 of slot 12 576, 603 bit 2 of slot 12 576, 603 bit 3 of slot 12 576, 603 bit clock stopped (bcs) 575, 602 block data (bdta) 541 boot_sts 421 buffer completion interrupt status (bcis) 570, 596 buffer descriptor base address 568 buffer descriptor list base address 595 buffered mode (buf) 364 bus master enable (bme) 437, 463, 552, 583, 740 bus master ide active (act) 458, 768 bus_err 535 byte_done_sts 535 c cap id (cap) 562 capability id 499 cascaded interrupt controller irq connection 363 channel 1 select 327 channel 2 select 327 channel 3 select 326 channel 5 select 326 channel 6 select 326 channel 7 select 326 channel mask bits 355 channel mask select 352 channel request status 351 channel terminal count status 351 clear byte pointer 353 clear mask register 354 cnf1_lpc_en 337 cnf2_lpc_en 337 codec access semaphore (cas) 604 codec write in progress (cwip) 578 coma decode range 332 coma_lpc_en 338 comb decode range 332 comb_lpc_en 338 configure flag (cf) 474 connect status change 484, 521 copr_err_en coprocessor error enable 328 coproc_err 383 count register status 359 count_size_cap 606 countdown type status 359 counter 0 select 357 counter 1 select 357 counter 2 select 357 counter latch command 358 counter out pin state 359 counter port 360 counter select 356 counter selection 358 counter_clk_per_cap 606
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 837 ?intel ? 6300ESB ich counter_val 609 cpu thermal trip status (cts 386 cpu_bist_en enables cpu bist 330 cpupwr_flr cpu power failure 386 cpuslp_en 385 current connect status 484, 521 current equals last valid (celv) 570, 597 current index value 569, 595 d d1_support 493 d2_support 493 d29_f0_disable 343 d29_f1_disable 343 d29_f7_disable 343 d31_f1_disable 344 d31_f3_disable 344 d31_f5_disable 343 d31_f6_disable 343 data 761 data_high_byte 548 data_len_cnt 524 data_low_byte 548 data_msg0 data message byte 0 543 data_msg1 data message byte 1 543 data0/count 540 data1 540 date alarm 380 dcb_en dma collection buffer enable 329 debug port number (dp_n) 505 debug port offset 496 delivery mode 374 delivery status 374, 645 destination 373, 644 destination mode 374, 645 dev_err 536 dev_trap_en 411 dev_trap_sts 411 device connects 231 device id value 528 device_address 547 devmon_sts device monitor status 408 devsel# timing status (devt) 464, 529, 553 dm data mode 379 dma channel group enable 350 dma channel select 352, 353 dma controller halted (dch) 570, 597 dma group arbitration priority 345, 350 dma low page 350 dma transfer mode 352 dma transfer type 353 done_sts 523 drive 0 dma capable 457, 768 drive 0 dma timing enable (dte0) 450, 749 drive 0 fast timing bank (time0) 450, 749 drive 0 iordy sample point enable (ie0) 450, 749 drive 0 prefetch/posting enable (ppe0) 450, 749 drive 1 dma capable 457, 768
intel ? 6300ESB ich? intel ? 6300ESB i/o controller hub ds november 2007 838 order number: 300641-004us drive 1 dma timing enable (dte1) 449, 749 drive 1 fast timing bank (time1) 450, 749 drive 1 iordy sample point enable (ie1) 449, 749 drive 1 prefetch/posting enable (ppe1) 449, 749 drive 1 timing register enable (sitre) 448, 748 dse daylight savings enable 379 dsi 493 dt delivery type 373, 644 dte delayed transaction enable 329 dv division chain select 377 e edge/level bank select (ltim) 361 ehc initialization 221 ehc resets 222 ehci extended capabilities pointer (eecp) 507 enable 32-byte buffer (e32b) 544 enable special mask mode (esmm) 366 enable_cnf overall enable 607 enabled_cnt 522 enter global suspend mode (egsm) 475 eos end of smi 407 error 458, 768 error_good#_sts 523 exception_sts 523 extended destination id (edid) 373, 644, 646 f failed 535 fast non-data pio (fndpio) 449 fast_pcb0 fast primary drive 0 base clock 754 fast_pcb1 fast primary drive 1 base clock 754 fast_scb0 fast secondary drive 0 base clock 754 fast_scb1 fast secondary drive 1 base clock 754 fdd decode range 333 fdd_lpc_en 338 fifo error (fifoe) 570, 596 fifo error interrupt enable (feie) 572, 599 force global resume (fgr) 474 force port resume 520 force_thtl 398 frame length timing value 497 frame list current index/frame number 481, 515 frame list rollover 513 frame list rollover enable 514 frame list size 510 freq_strap 330 full_rst 383 fwh_c0_en 336, 342 fwh_c0_idsel 339 fwh_c8_en 336, 342 fwh_c8_idsel 339 fwh_d0_en 336, 342 fwh_d0_idsel 339 fwh_d8_en 335, 342 fwh_d8_idsel 339, 341
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 839 ?intel ? 6300ESB ich fwh_e0_en 335 fwh_e0_idsel 339, 341 fwh_e8_en 335 fwh_e8_idsel 339, 341 fwh_f0_en 335 fwh_f0_idsel 339, 341 fwh_f8_en 335 fwh_f8_idsel 339 g gameh_lpc_en 337 gamel_lpc_en 337 gbl _sts 395 gbl_en 396 gbl_rls global release 397 gbl_smi_en 407 gen1_base generic i/o decode range 1 base 336 gen1_en generic decode range 1 enable 336 gen2_base generic i/o decode range 2 base 340 gen2_en generic i/o decode range 2 enable 340 global reset (greset) 476 go_cnt 523 gp_io_sel2 432 gp_lvl2 433 gpe0_sts 409 gpe1_sts 409 gpi interrupt enable (gie) 574, 601 gpi status change interrupt (gsci) 577, 604 gpi0 route 389 gpi15 route 389 gpin_en 404 gpin_sts 401 gpio_sel 426 gpio11_alert_disable 423 h hc bios owned semaphore 499 hc os owned semaphore 499 hchalted 478, 512 hcrese 223 hide_isa hide isa bridge 327 host controller process error 478 host controller reset 511 host controller reset (hcreset) 476 host system error 478, 513 host system error enable. 514 host_busy 536 host_notify_intren 546 host_notify_sts 546 host_notify_wken 546 hourform hour format 379 hst_en smbus host enable 533 hubnmi_sts 419 hubsci_sts 419 hubserr_sts 419 hubsmi_sts 419
intel ? 6300ESB ich? intel ? 6300ESB i/o controller hub ds november 2007 840 order number: 300641-004us i i/o apic identification 372 i/o space (ios) 583 i/o space enable (iose) 463, 528, 562 i2c 246, 249 i2c_en 533 icw/ocw select 361 icw4 write required (ic4) 361 ide decode enable (ide) 448, 748 idep0_act_sts 413 idep0_trp_en 415 idep1_act_sts 413 idep1_trp_en 415 ides0_act_sts 413 ides0_trp_en 415 ides1_act_sts 413 ides1_trp_en 414 in_use_cnt 523 index 760 init_now 382 intel_usb2_en 405 intel_usb2_sts 408 interrupt 458, 768 interrupt input pin polarity 374, 645 interrupt level select (l2, l1, l0) 365 interrupt line 446, 747 interrupt on async advance 512 interrupt on async advance doorbell 509 interrupt on async advance enable 514 interrupt on complete (ioc) enable 480 interrupt on completion enable (ioce) 572, 599 interrupt pin 447, 748 interrupt request level 362 interrupt request mask 364 interrupt threshold control 509 interrupt vector base address 362 intr 536 intrd_det intruder detect 421 intrd_sel 423 intren 539 inuse_sts 535 iochk_nmi_en 381 iochk_nmi_sts iochk# nmi source status 381 iordy sample point (isp) 448, 748 iose i/o space enable (iose) 437, 740 irq number 370, 642 irq routing 324 irq1_cause 424 irq10 ecl 368 irq11 ecl 368 irq12 ecl 367 irq12_cause 424 irq12len mouse irq12 latch enable 328 irq14 ecl 367 irq15 ecl 367 irq1len keyboard irq1 latch enable 328 irq3 ecl 367 irq4 ecl 367 irq5 ecl 367
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 841 ?intel ? 6300ESB ich irq6 ecl 367 irq7 ecl 367 irq9 ecl 368 irqen 324 irqf interrupt request flag 380 isochronous scheduling threshold 507 k kbc_act_sts 412 kbc_lpc_en 337 kbc_trp_en 414 kill 539 l l128lock lower 128-byte lock 331 last codec read data input (ldi) 579 last valid buffer completion interrupt (lvbci) 570, 597 last valid buffer interrupt enable (lvbie) 572, 600 last valid index 569, 596 latch count of selected counters 357 latch status of selected counters 357 latency 728 leg_act_sts 413 leg_io_trp_en 414 leg_rt_cap 606 leg_rt_cnf 607 legacy_usb_en 406 legacy_usb_sts 409 legacy_usb2_en 405 legacy_usb2_sts 408 light host controller reset 509 line status 484, 519 link pointer low 517 link_id_sts 523 loop back test mode 474 low speed device attached (ls) 483 lpt decode range 333 lpt_lpc_en 338 m mas (master-abort status) 584 mask 374, 645 master clear 354 master/slave in buffered mode 364 master-abort status (mas) 553 max packet (maxp) 474 maximum redirection entries 372, 643 mc_lpc_en 337 mcsmi_en microcontroller smi enable 406 mcsmi_sts microcontroller smi# status 409 md3 575, 603 memory space (ms) 552 memory space enable (mse) 437, 740 mic in interrupt (mint) 576, 604 microphone 2 in interrupt (m2int) 575, 602 microprocessor mode 364
? intel ? 6300ESB ich intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 842 midi decode range 334 midi_act_sts 412 midi_lpc_en 337 midi_trp_en 414 mmt_addr_en 328 mmt_addr_sel 328 mode selection status 359 modem in interrupt (miint) 577, 604 modem out interrupt (moint) 577, 604 mon_trap_base 391 mon4_fwd_en 390 mon4_mask 391 mon5_fwd_en 390 mon5_mask 391 mon6_fwd_en 390 mon6_mask 391 mon7_fwd_en 390 mon7_mask 391 mss decode range 334 mss_lpc_en 337 multi-function bit 466 n gp_blink 429 gp_inv 430 gp_lvl 427 n_ports 506 newcentury_sts 420 next capability (next) 562 next ehci capability pointer 499 nmi_en 382 nmi_now 422 nmi2smi_en 420, 422 no_reboot 329 num_tim_cap 606 number of companion controllers (n_cc) 506 number of ports per companion controller (n_pcc) 506 o ocw2 select 365 ocw3 select 366 over-current active 521 overcurrent active 483 over-current change 520 overcurrent indicator 483 owner_cnt 522 p pass through state (pstate) 471 pcb0 755 pcb1 755 pci interrupt enable (usbpirqen) 470 pci_serr_en 381 pcm 4/6 enable 573 pcm in 1, microphone in 1 data in line (di1l) 578 pcm in 2 interrupt (p2int) 575, 602 pcm in 2, microphone in 2 data in line (di2l) 578 pcm in interrupt (piint) 577, 604 pcm out interrupt (point) 577, 604 pcm out mode (pom) 573 pec_data 542 pec_en 537 per_smi_sel 385 periodic list execution 224 periodic schedule enable 510 periodic schedule status 512 periodic_en 406 periodic_sts 408 pf periodic interrupt flag 380 pie periodic interrupt enable 378 pirqae_act_sts 413 pirqbf_act_sts 413 pirqcg_act_sts 413 pirqdh_act_sts 412 pm1_sts_reg 409 pme clock 494 pme status (pmes) 563, 591 pme_b0_en 404 pme_b0_sts 401 pme_en 404, 494 pme_status 494 pme_sts 402 pme_support 493 poll mode command 366 pop_mode_cap 439, 742 pop_mode_sel 439, 742 port 0 bist fis initiate 764 port 1 bist fis initiate 764 port change detect 513 port change interrupt enable 514 port enable/disable change 484, 521 port enabled/disabled 521 port enabled/disabled (port_en) 484 port owner 518 port power (pp) 518 port reset 483, 519 port test control 518 port wake implemented 498 port wake up capability mask 498 port0en 472 port1en 472 port-routing logic 230 position in current buffer 571, 597, 599 power management event enable (pmee) 564, 592 power sequencing 811 power state (ps) 564, 592 powerstate 495 prbtnor_sts power button override status 394 prefetched index value 571 primany resume interrupt enable 573, 600 primary codec ready (pcr) 576, 603 primary drive 0 cycle time (pct0) 454, 753 primary drive 0 synchronous dma mode enable (psde0) 452, 751 primary drive 1 cycle time (pct1) 454, 753
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 843 ?intel ? 6300ESB ich primary drive 1 iordy sample point (pisp1) 451, 750 primary drive 1 recovery time (prct1) 451, 750 primary drive 1 synchronous dma mode enable (psde1) 452, 751 primary resume interrupt 576, 603 programmable baud rate generator 722 programmable frame list flag 507 prq 372, 643 pwr_flr power failure 387 pwrbtn__sts 395 pwrbtn_en 396 pwrbtn_lvl 385 pwrok_flr pwrok failure 386 r read / write control (rwc) 456, 767 read back command 357 read completion status 576, 603 read policies for periodic dma 224 read/write select 356 read/write selection status 359 received master-abort status (rma 464 received master-abort status (rma) 438, 741 received_pid_sts 525 receiver interrupts 723 reclamation 512 recovery time (rct) 449, 749 redirection entry clear 371, 642 ref_toggle refresh cycle toggle 381 register read command 366 remote irr 374, 645 reset registers(rr) 600 reset registers(rr). 572 resource type indicator (rte) 441, 442, 443, 556, 557, 558, 587, 588, 744, 745, 746 resume detect (rsm_det 484 resume detect (rsm_det) 479 resume interrupt enable 480 ri_en 404 ri_sts 402 rotate and eoi codes (r, sl, eoi) 365 rs rate select 377 rst_cpu 383 rtc_en rtc event enable 396 rtc_indx real time clock index address 382 rtc_pwr_sts 387 rtc_sts 395 run/pause bus master (rpbm) 572, 600 run/stop (rs) 476, 511 rw 539 s s/pdif interrupt (spint) 575, 602 safe_mode 329 sample capabilities 575, 602 sata setup data a 762 sata setup data b 762 sb16 decode range 334 sb16_lpc_en 338
intel ? 6300ESB ich? intel ? 6300ESB i/o controller hub ds november 2007 844 order number: 300641-004us scb1 754 scbo 755 sci_en 397 second_to_sts 421 secondary codec id (scid) 561 secondary codec ready (scr) 576, 603 secondary drive 0 cycle time (sct0) 453, 752 secondary drive 0 synchronous dma mode enable (ssde0) 452, 751 secondary drive 1 cycle time (sct1) 453, 752 secondary drive 1 iordy sample point (sisp1) 451, 750 secondary drive 1 recovery time (srct1) 451, 750 secondary drive 1 synchronous dma mode enable (ssde1) 452, 751 secondary resume interrupt 576, 603 secondary resume interrupt enable 573, 600 secondary slave channel cable reporting 754 send_pid_cnt 525 sendnow 422 serirq_smi_sts 408 serr#_nmi_sts serr# nmi source status 381 set update cycle inhibit 378 short packet interrupt enable 479 signaled target-abort status 529 signaled target-abort status (sta) 438, 464, 741 single or cascade (sngl) 361 slave identification code 363 slave_addr 542 slp_en 397 slp_smi_en 406 slp_smi_sts 409 slp_typ 397 smb_cmd 538 smb_for_bios 344 smb_smi_en 533 smb_wak_sts smbus wake status 402 smbalert_dis 546 smbalert_sts 535 smbclk_ctl 545 smbclk_cur_sts 545 smbdata_cur_sts 545 smbus smi status (smbus_smi_sts) 408 smi at end of pass-through enable (smiatendps) 471 smi caused by end of pass-through (smibyendps) 470 smi caused by port 60 read (trapby60r) 471 smi caused by port 60 write (trapby60w) 471 smi caused by port 64 read (trapby64r) 470 smi caused by port 64 write (trapby64w) 470 smi caused by usb interrupt (smibyusb) 470 smi on async 501 smi on async advance 500 smi on async advance enable 500 smi on async enable 502 smi on bar 500 smi on bar enable 500 smi on cf 502 smi on cf enable 502 smi on frame list rollover 500 smi on frame list rollover enable 501 smi on hchalted 502 smi on hchalted enable 502 smi on hcreset 502
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 845 ?intel ? 6300ESB ich smi on hcreset enable 502 smi on host system error 500 smi on host system error enable 501 smi on os ownership change 500 smi on os ownership enable 500 smi on pci command 500 smi on pci command enable 500 smi on periodic 502 smi on periodic enable 502 smi on pmcsr 501 smi on pmscr enable 502 smi on port 60 reads enable (60ren) 472 smi on port 60 writes enable (60wen) 472 smi on port 64 reads enable (64ren) 472 smi on port 64 writes enable (64wen) 471 smi on port change detect 500 smi on port change enable 501 smi on portowner 501 smi on portowner enable 502 smi on usb complete 500 smi on usb complete enable 501 smi on usb error 500 smi on usb error enable 501 smi on usb irq enable (usbsmien) 471 smlink_clk_ctl 544 smlink_slv_smi_sts?r/w. smlink slave smi status 421 smlink0_cur_sts 544 smlink1_cur_sts 544 sof timing value 482 software debug (swdbg) 474 sop_mode_cap 439, 742 sop_mode_sel 439, 742 special fully nested mode (sfnm) 364 special mask mode (smm) 366 spkr_dat_en 381 sqwe square wave enable 378 start 537 start/stop bus master (start) 456, 767 steer enable (se) 579 stpclk_de 388 sub class code 440, 742 subsystem id (sid) 446, 747 subsystem vendor id (svid) 445, 746 suspend 483 sw_tco_smi 420 swsmi_rate_sel 387 swsmi_tmr_en software smi# timer enable 406 swsmi_tmr_sts 409 sys_rst 383 system reset status (srs) 386 t t00_int_sts 608 t01_int_sts 608 t02_int_sts 608 tco_en 406 tco_int_sts 420 tco_message 423 tco_sts 408
intel ? 6300ESB ich? intel ? 6300ESB i/o controller hub ds november 2007 846 order number: 300641-004us tco_tmr_hlt tco timer halt 422 tcosci_en 404 tcosci_sts 402 tertiary codec id (tid 561 tertiary codec ready (tcr) 575, 602 tertiary resume interrupt (tri) 575, 602 tertiary resume interrupt enable (tre) 573, 600 thrm#_pol 405 thrm_dty 399 thrm_en 405 thrm_sts thermal interrupt status 403 thrmor_sts thermal interrupt override status 403 tht_en 399 thtl_dty 399 thtl_sts throttle status 398 tim_cnt2_en timer counter 2 enable 381 timeout 420 timeout/crc interrupt enable 480 timern_32mode_cnf 611 timern_int_enb_cnf 612 timern_int_rout_cap 610 timern_int_rout_cnf 611 timern_int_type_cn 612 timern_per_int_cap 611 timern_size_cap 611 timern_type_cnf 612 timern_val_set_cnf 611 tmr_val 398 tmr2_out_sts timer counter 2 out status 381 tmrof_en timer overflow interrupt enable 396 tmrof_sts timer overflow status 395 token_pid_cnt 525 top_swap 330 trigger mode 374, 645 u u128e upper 128-byte enable 331 u128lock upper 128-byte lock 331 uf update-ended flag 380 uhci v/s ehci 221 uie update-ended interrupt enable 378 uip update in progress 377 usb error interrupt 479, 513 usb error interrupt enable 514 usb interrupt 513 usb interrupt (usbint) 479 usb interrupt enable 514 usb_address_cnf 526 usb_endpoint_cnf 526 usb1_en 405 usb1_sts 403 usb2.0 controller (d29 f7) 221 usb2_en 405 usb2_sts 403
intel ? 6300ESB i/o controller hub november 2007 ds order number: 300641-004us 847 ?intel ? 6300ESB ich v vector 374 vendor id value 527 vendor_id_cap 606 vrt valid ram and time bit 380 w wak_sts 394 wdstatus watchdog status 424 write policies for periodic dma 225 write_read#_cnt 524 wrt_rdonly 503
intel ? 6300ESB ich? intel ? 6300ESB i/o controller hub ds november 2007 848 order number: 300641-004us

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